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HM62W8128 Series
131,072-word x 8-bit High Speed CMOS Static RAM
Description
The Hitachi HM62W8128 is a CMOS static RAM organized 131,072-word x 8-bit. It realizes higher density, higher performance and low power consumption by employing 0.8 m Hi-CMOS process technology. It offers low power standby power dissipation; therefore, it is suitable for battery backup systems. The device, packaged in a 525-mil SOP (460-mil body SOP) or a 8 x 20 mm TSOP with thickness of 1.2 mm, is available for high density mounting. TSOP package is suitable for cards, and reverse type TSOP is also provided.
Features
* High speed Fast access time: 100/120 ns (max) * Low power Active: 23 mW (typ) Standby: 4 W (typ) * Single 3.3 V supply * Completely static memory No clock or timing strobe required * Equal access and cycle times * Common data input and output Three state output * All inputs and outputs CMOS compatible. * Capability of battery backup operation 2 chip selection for battery backup
HM62W8128 Series
Ordering Information
Type No. HM62W8128LFP-10 HM62W8128LFP-12 HM62W8128LFP-10SL HM62W8128LFP-12SL HM62W8128LT-10 HM62W8128LT-12 HM62W8128LT-10SL HM62W8128LT-12SL HM62W8128LR-10 HM62W8128LR-12 HM62W8128LR-10SL HM62W8128LR-12SL Access Time 100 ns 120 ns 100 ns 120 ns 100 ns 120 ns 100 ns 120 ns 100 ns 120 ns 100 ns 120 ns 8mm x 20mm 32-pin TSOP (reverse type) (TFP-32DR) 8mm x 20mm 32-pin TSOP (normal type) (TFP-32D) Package 525-mil 32-pin plastic SOP (FP-32D)
2
HM62W8128 Series
Pin Arrangement
HM62W8128LFP Series NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top View) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CS2 WE A13 A8 A9 A11 OE A10 CS1 I/O7 I/O6 I/O5 I/O4 I/O3 HM62W8128LR Series A4 A5 A6 A7 A12 A14 A16 NC VCC A15 CS2 WE A13 A8 A9 A11 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 (Top View) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7 CS1 A10 OE HM62W8128LT Series A11 A9 A8 A13 WE CS2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top View) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CS1 I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 A1 A2 A3
3
HM62W8128 Series
Pin Description
Pin Name A0 - A16 I/O0 - I/O7 CS1 CS2 WE OE NC VCC VSS Function Address Input/output Chip select 1 Chip select 2 Write enable Output enable No connection Power supply Ground
4
HM62W8128 Series
Block Diagram
(MSB) V CC V SS
* * * * *
A13 A15 A6 A7 A12 A14 A16 A5 A4 Row Decoder
Memory Matrix 512 x 2,048
(LSB)
I/O0 Input Data Control I/O7
* *
Column I/O Column Decoder
* *
(LSB)
A8 A9 A11 A10 A0 A1 A2 A3
* *
(MSB)
CS2 CS1 WE OE
Timing Pulse Generator Read/Write Control
5
HM62W8128 Series
Function Table
CS1 H X L L L L CS2 X L H H H H OE X X H L H L WE X X H H L L Mode Standby Standby Output disable Read Write Write VCC Current I SB , I SB1 I SB , I SB1 I CC I CC I CC I CC I/O Pin High-Z High-Z High-Z Dout Din Din Ref. Cycle -- -- -- Read cycle Write cycle (1) Write cycle (2)
Note: X: H or L
Absolute Maximum Ratings
Parameter Supply voltage relative to VSS Voltage on any pin relative to V SS Power dissipation Operating temperature Storage temperature Storage temperature under bias
*1
Symbol VCC VT PT Topr Tstg Tbias
Value -0.5 to +5.5 -0.5 to V CC + 0.3 1.0 0 to +70 -55 to +125 -10 to +85
*2 *3
Unit V V W C C C
Notes: 1. With respect to V SS 2. -1.2 V for pulse half-width 30 ns 3. Maximum voltage is 5.5 V
Recommended DC Operating Conditions (Ta = 0 to +70C)
Parameter Supply voltage Symbol VCC VSS Input voltage VIH VIL Note: Min 3.0 0 2.2 -0.3
*1
Typ 3.3 0 -- --
Max 3.6 0 VCC + 0.3 0.4
Unit V V V V
1. -1.2 V for pulse half-width 30 ns
6
HM62W8128 Series
DC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, VSS = 0 V)
Parameter Input leakage current Output leakage current Symbol |ILI| |ILO | Min Typ*1 -- -- -- -- Max Unit Test Conditions 1 1 A A Vin = VSS to V CC CS1 = VIH or CS2 = VIL or OE = VIH or WE = VIL, VI/O = VSS to V CC CS1 = VIL, CS2 = VIH, Others = VIH/V IL I I/O = 0 mA Min cycle, duty = 100%, CS1= VIL, CS2 = VIH, Others = VIH/V IL I I/O = 0 mA Cycle time = 1 s, duty = 100%, I I/O = 0 mA, CS1 0.2 V, CS2 V CC - 0.2 V VIH V CC - 0.2 V, VIL 0.2 V (1) CS1 = VIH, CS2 = VIH or (2) CS2 = VIL 0 V Vin V CC (1) CS1 V CC- 0.2 V, CS2 V CC - 0.2 V or (2) 0 V CS2 0.2 V I SB1 (L-SL version) -- Output voltage VOL VOH Note: -- 2.9 1.2 -- -- 30 0.1 -- A V V I OL = 100 A I OH = -100 A
Operating power supply current: DC Operating power supply current
I CC
--
6
10
mA
I CC1
--
20
25
mA
I CC2
--
7
10
mA
Standby power supply current: DC Standby power supply current (1): DC
I SB I SB1 (L version)
-- --
0.5 1.2
2 70
mA A
1. Typical values are at VCC = 3.3 V, Ta = +25C and not guaranteed.
Capacitance (Ta = 25C, f = 1.0 MHz)*1
Parameter Input capacitance Input/output capacitance Note: Symbol Min Cin CI/O -- -- Typ -- -- Max 8 10 Unit pF pF Test Conditions Vin = 0 V VI/O = 0 V
1. This parameter is sampled and not 100% tested.
7
HM62W8128 Series
AC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, unless otherwise noted.)
Test Conditions * * * * Input pulse levels: 0.4 V to 2.4 V Input rise and fall time: 5 ns Input and output timing reference levels: 1.5 V Output load: 1 TTL Gate and CL (50 pF) (Including scope & jig)
Read Cycle
HM62W8128-10 Parameter Read cycle time Address access time Chip selection to output valid Symbol t RC t AA t CO1 t CO2 Output enable to output valid Chip selection to output in low-Z t OE t LZ1 t LZ2 Output enable to output in low-Z t OLZ Min 100 -- -- -- -- 15 15 10 0 0 0 15 Max -- 100 100 100 80 -- -- -- 40 40 40 -- HM62W8128-12 Min 120 -- -- -- -- 15 15 10 0 0 0 15 Max -- 120 120 120 100 -- -- -- 50 50 50 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns 2, 3 2, 3 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Notes
Chip deselection to output in high-Z t HZ1 t HZ2 Output disable to output in high-Z Output hold from address change t OHZ t OH
Notes: 1. t HZ and t OHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. At any given temperature and voltage condition, t HZ max is less than tLZ min both for a given device and from device to device. 3. This parameter is sampled and not 100% tested.
8
HM62W8128 Series
Read Timing Waveform (WE = VIH)
t RC
Address
Valid address t AA
CS1 t CO1 t LZ1 CS2 t CO2 t LZ2 t HZ2 t HZ1
OE t OE t OLZ Dout High Impedance t OHZ t OH Valid data
9
HM62W8128 Series
Write Cycle
HM62W8128-10 Parameter Write cycle time Chip selection to end of write Address setup time Address valid to end of write Write pulse width Write recovery time Write to output in high-Z Data to write time overlap Write hold from write time Output active from end of write Output disable to output in High-Z Symbol t WC t CW t AS t AW t WP t WR t WHZ t DW t DH t OW t OHZ Min 100 90 0 90 80 0 0 50 0 10 0 Max -- -- -- -- -- -- 40 -- -- -- 40 HM62W8128-12 Min 120 110 0 110 100 0 0 60 0 10 0 Max -- -- -- -- -- -- 50 -- -- -- 50 Unit ns ns ns ns ns ns ns ns ns ns ns 10 10 Notes
Notes: 1. A write occures during the overlap of a low CS1, a high CS2, and a low WE. A write begins at the latest transition among CS1 going low, CS2 going high, and WE going low. A write ends at the earliest transition among CS1 going high, CS2 going low, and WE going high. tWP is measured from the beginning of write to the end of write. 2. t CW is measured from the later of CS1 going low or CS2 going high to the end of write. 3. t AS is measured from the address valid to the beginning of write. 4. t WR is measured from the earliest of CS1 or WE going high or CS2 going low to the end of write cycle. 5. During this period, I/O pins are in the output state; therefore, the input signals of the opposite phase to the outputs must not be applied. 6. This parameter is sampled and not 100% tested. 7. In the cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of data bus contention. t WP tDW min + tWHZ max
10
HM62W8128 Series
Write Timing Waveform (1) (OE Clock)
t WC Address Valid address t AW OE t CW
CS1
*1
t WR
CS2 t AS WE t OHZ High Impedance Dout t DW Din t DH t WP
Valid data Note: 1. If CS1 goes low simultaneously with WE going low or after WE going low, the outputs remain in a high impedance state.
11
HM62W8128 Series
Write Timing Waveform (2) (OE Low Fixed)
t WC Address
Valid address t CW t WR
CS1
*1
CS2
t AW t WP WE t AS t WHZ t OW
*2 *3
t OH
Dout
High Impedance t DW t DH
*4
Din
Valid data Notes: 1. If CS1 goes low simultaneously with WE going low or after WE going low, the outputs remain in a high impedance state. 2.Dout is the same phase of the latest written data in this write cycle. 3.Dout is the read data of next address. 4.If CS1 is low and CS2 high during this period, I/O pins are in the output state. Therefore, the input signals of the opposite phase to the outputs must not be applied to them.
12
HM62W8128 Series
Low VCC Data Retention Characteristics (Ta = 0 to +70C)
Parameter VCC for data retention Symbol VDR Min 2.0 Typ -- Max -- Unit V Test Conditions*3 CS1 V CC -0.2 V, CS2 V CC -0.2 V or 0 V CS2 0.2 V Vin 0 V VCC = 3.0 V, Vin 0V CS1 V CC - 0.2 V, CS2 V CC - 0.2 V or 0 V CS2 0.2 V
Data retention current
I CCDR (L-version)
--
1
50*1
A
I CCDR (L-SL version) Chip deselect to data retention time Operation recovery time t CDR tR
-- 0 5
1 -- --
15*2 -- --
A ns ms See retention waveform
Notes: 1. 20 A max at Ta = 0 to 40C (L-version). 2. 3 A max at Ta = 0 to 40C (L-SL version). 3. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer, and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE, OE, CS1, I/O) can be in the high impedance state. If CS1 controls data retention mode, CS2 must be CS2 V CC - 0.2 V or 0 V CS2 0.2 V. The other input levels (address, WE, OE, I/O) can be in the high impedance state.
Low V CC Data Retention Timing Waveform (1) (CS1 Controlled)
t CDR V CC 3.0 V Data retention mode tR
2.2 V V DR1 CS1 0V CS1 VCC - 0.2 V
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HM62W8128 Series
Low V CC Data Retention Timing Waveform (2) (CS2 Controlled)
t CDR V CC 3.0 V CS2 V DR2 0.4 V 0V 0 V < CS2 < 0.2 V Data retention mode tR
Package Dimensions
HM62W8128LFP Series (FP-32D)
20.45 20.95 Max 32 17 Unit: mm
1 1.00 Max
16 3.00 Max 14.14 0.30
+ 0.13 - 0.07
11.30
1.42
0.22
1.27
0.10 0.40 + 0.05 -
0.10 0.15 M
+ 0.12 - 0.10
0-8 0.80 0.20
14
0.15
HM62W8128 Series
HM62W8128LT Series (TFP-32D)
8.00 8.20 Max 32 17
Unit: mm
1 0.20 0.10
16 0.50 0.08 M 0.45 Max 20.00 0.20 0 - 5 0.17 0.05 0.13 0.05 0.50 0.10 0.80
1.20 Max
0.10
18.40
15
HM62W8128 Series
HM62W8128LR Series (TFP-32DR)
8.00 8.20 Max 17 32
Unit: mm
16 0.20 0.10
1 0.50 0.08 M 0.45 Max 20.00 0.20 0 - 5 0.17 0.05 0.13 0.05 0.50 0.10 0.80
1.20 Max
0.10
16
18.40

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