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HB56SW464DBJ Series
4,194,304-word x 64-bit High Density Dynamic RAM Module
ADE-203-688A (Z) Rev. 1.0 May. 30, 1997 Description
The HB56SW464DBJ is a 4M x 64 dynamic RAM Small Outline Dual In-line Memory Module (S.O.DIMM), mounted 16 pieces of 16-Mbit DRAM (HM51W17805) sealed in TCP package and 1 piece of serial EEPROM (24C02) for Presence Detect (PD). The HB56SW464DBJ offers Extended Data Out (EDO) Page Mode as a high speed access mode. An outline of the HB56SW464DBJ is 144-pin Zig Zag Dual tabs socket type compact and thin package. Therefore, the HB56SW464DBJ makes high density mounting possible without surface mount technology. The HB56SW464DBJ provides common data inputs and outputs. Decoupling capacitors are mounted beside each TCP on the module board.
Features
* 144-pin Zig Zag Dual tabs socket type Lead pitch: 0.80 mm * Single 3.3 V (+0.3, -0.15 V) supply * High speed Access time: tRAC = 60 ns (max) tCAC = 15 ns (max) * Low power dissipation Active mode: 3.024 W (max) Standby mode (TTL): 115 mW (max) (CMOS): 58 mW (max) (CMOS): 8.64 mW (max) (L/LS-version) * EDO mode capability * Refresh period 2048 refresh cycles: 32 ms 128 ms (L/LS-version) * 3 variations of refresh RAS-only refresh CAS-before-RAS refresh Self refresh (LS-version)
HB56SW464DBJ Series
Ordering Information
Type No. HB56SW464DBJ-6 HB56SW464DBJ-6L HB56SW464DBJ-6LS Access time 60 ns 60 ns 60 ns Package Small Outline DIMM (144-pin) Contact pad Gold
Pin Arrangement
--Front Side--
1 pin 2 pin
59 pin 60 pin
61 pin 62 pin
143 pin 144 pin
--Back Side--
Pin Arrangement
Front side Pin No. 1 3 5 7 9 11 13 15 17 Pin name VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 Pin No. 73 75 77 79 81 83 85 87 89 Pin name OE VSS NC NC VCC DQ16 DQ17 DQ18 DQ19 Back side Pin No. 2 4 6 8 10 12 14 16 18 Pin name VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 Pin No. 74 76 78 80 82 84 86 88 90 Pin name NC VSS NC NC VCC DQ48 DQ49 DQ50 DQ51
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HB56SW464DBJ Series
Pin Arrangement (cont)
Front side Pin No. 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 Pin name DQ7 VSS CE0 CE1 VCC A0 A1 A2 VSS DQ8 DQ9 DQ10 DQ11 VCC DQ12 DQ13 DQ14 DQ15 VSS NC NC NC VCC NC WE RE0 RE1 Pin No. 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 Pin name VSS DQ20 DQ21 DQ22 DQ23 VCC A6 A8 VSS A9 A10 VCC CE2 CE3 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS SDA VCC Back side Pin No. 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 Pin name DQ39 VSS CE4 CE5 VCC A3 A4 A5 VSS DQ40 DQ41 DQ42 DQ43 VCC DQ44 DQ45 DQ46 DQ47 VSS NC NC NC VCC NC NC NC NC Pin No. 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 Pin name VSS DQ52 DQ53 DQ54 DQ55 VCC A7 NC VSS NC NC VCC CE6 CE7 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS SCL VCC
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HB56SW464DBJ Series
Pin Description
Pin name A0 to A10 Function Address input Row address Column address Refresh address DQ0 to DQ63 RE0, RE1 CE0 to CE7 WE OE VCC VSS SDA SCL NC Note: Serial-PD Data are not protected. Data-in/data-out Row address strobe (RAS) Column address strobe (CAS) Read/Write enable Output enable Power supply Ground Serial data for PD Serial clock for PD No connection : A0 to A10 : A0 to A9 : A0 to A10
4
HB56SW464DBJ Series
Serial PD Matrix*1
Byte No. Function described 0 1 2 3 4 5 6 7 8 9 10 11 12 Number of bytes used by module manufacturer Total SPD memory size Memory type Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 x 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 x 0 0 1 0 1 0 1 1 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 x 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 1 0 0 1 0 x 0 0 1 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 x 0 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 x 0 0 1 80 08 02 0B 0A 02 40 00 01 3C 0F 00 00 04 84 08 00 00 00 01 36 3A BA 07 00 xx 48 42 35 ASCII-8bit code*2 H B 5 Hitachi Future offerings Rev. 1 128 256 byte EDO 11 10 2 64 0 (+) LVTTL t RAC = 60 ns t CAC = 15 ns Non-parity Normal (15.625 s) (62.5s) Self refresh (62.5 s) x8
Number of row addresses bits 0 Number of column addresses 0 bits Number of banks Module data width 0 0
Module data width (continued) 0 Module interface signal levels 0 RAS access time CAS access time Module configuration type Refresh rate/type -6 -6L (L-version) -6LS (LS-version) 0 0 0 0 0 1 0 0 0 0 0 0 0 1
13 14
DRAM width Error checking DRAM width
15 to 31 Reserved for future offerings 32 to 61 Superset information 62 63 SPD data revision code Checksum for bytes 0 to 62 -6 -6L -6LS 64
Manuf ac t urer's JEDEC ID code 0 x 0 0 0
65 to 71 Manuf ac t urer's JEDEC ID code 0 72 73 74 75 Manufacturing location Manufacturer's part number Manufacturer's part number Manufacturer's part number
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HB56SW464DBJ Series
Byte No. Function described 76 77 78 79 80 81 82 83 84 85 86 87 Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number -6 -6L, -6LS 88 Manufacturer's part number -6, -6L -6LS 89 90 91 92 93 94 Manufacturer's part number Manufacturer's part number Revision code Revision code Manufacturing date Manufacturing date Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x *5 *6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 00 Not use Not use 0 1 1 0 0 0 1 1 1 1 0 0 1 0 1 0 0 0 0 x x 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 1 1 1 x x 1 1 1 1 1 1 0 0 0 1 1 0 0 0 1 0 0 1 0 x x 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 x x 1 0 1 1 1 1 1 0 0 1 1 0 1 0 0 0 0 0 0 x x 1 1 1 0 1 0 0 1 1 1 1 0 0 0 1 0 0 0 0 x x 0 1 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 x x 36 53 57 34 36 34 44 42 4A 5F 36 20 4C 20 53 20 20 30 20 xx xx 6 S W 4 6 4 D B J -- 6 (Space) L (Space) S (Space) (Space) Initial (Space) Year-code (binary) *3 Week-code (binary) *4
95 to 98 Assembly serial number 99 to 125 Manufacturer specific data 126 127 Reserved Reserved
Notes: 1. All serial PD data are not protected. 0: Serial data, "Low level", 1: Serial data, "High level" 2. Byte72 is manufacturing location code. (ex: in case of Japan, byte72 is 4Ah. 4Ah shows "J" on ASCII code.) 3. Byte 93 (Manufacturing date-year code) ex: 61h shows Year 97, 62h shows Year 98. 4. Byte 94 (Manufacturing date-week code) ex: 0Bh shows Week 11, 24h shows Week 36. 5. Bytes 95 through 98 are assembly serial number. 6. All bits of 99 through 125 are not defined ("1" or "0").
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HB56SW464DBJ Series
Block Diagram
RE0 RE1 WE OE CE0 CAS RAS WE OE DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CE1 CAS RAS WE OE DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CE2 CAS RAS WE OE DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 CE3 CAS RAS WE OE DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CAS RAS WE OE DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CAS RAS WE OE DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 CE7 CAS RAS WE OE I/O I/O I/O I/O I/O I/O I/O I/O CAS RAS WE OE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CAS RAS WE OE DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 CE6 CAS RAS WE OE I/O I/O I/O I/O I/O I/O I/O I/O CAS RAS WE OE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CAS RAS WE OE DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 CE5 CAS RAS WE OE I/O I/O I/O I/O I/O I/O I/O I/O CAS RAS WE OE I/O I/O I/O I/O I/O I/O I/O I/O
CE4 CAS RAS WE OE I/O I/O I/O I/O I/O I/O I/O I/O CAS RAS WE OE
U0
U8
U4
U12
U1
U9
U5
U13
U2
U10
U6
U14
U3
U11
U7
U15
SDA SCL SCL SDA A0 D0 A1 A2
A0 to A10 VCC VSS * U0 to U15: HM51W17805 D0: 24C02 C0 to C7: Chip capacitor C0 to C7
U0 to U15 U0 to U15, D0 U0 to U15, D0
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HB56SW464DBJ Series
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout Pt Topr Tstg Value -0.5 to +4.6 -0.5 to +4.6 50 16 0 to +70 -55 to +125 Unit V V mA W C C
Recommended DC Operating Conditions (Ta = 0 to +70C)
Parameter Supply voltage Symbol VSS VCC Input high voltage Input low voltage Note: 1. All voltage referred to VSS . VIH VIL Min 0 3.15 2.0 -0.3 Typ 0 3.3 -- -- Max 0 3.6 VCC + 0.3 0.8 Unit V V V V 1 1 1 Note
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HB56SW464DBJ Series
DC Characteristics (Ta = 0 to +70C, VCC = 3.3 V +0.3, -0.15 V, VSS = 0 V)
60 ns Parameter Operating current Standby current Symbol I CC1 I CC2 Min -- -- Max Unit Test conditions 840 32 mA mA t RC = min TTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z t RC = min RAS = VIH, CAS = VIL Dout = enable t RC = min t HPC = min CMOS interface Dout = High-Z CBR ref. : tRC = 31.3 s t RAS 0.3 s COMS interface RAS, CAS VCC - 0.2 V Dout = High-Z 0 V Vin 4.6 V 0 V Vout 4.6 V Dout = disable High Iout = -2 mA Low Iout = 2 mA 1, 3 4 2 1 Notes 1, 2
--
16
mA
Standby current (L/LS-version)
I CC2
--
2.4
mA
RAS-only refresh current Standby current CAS-before-RAS refresh current EDO page mode current
I CC3 I CC5 I CC6 I CC7
-- -- -- -- --
840 80 840 760 6.4
mA mA mA mA mA
Battery backup current I CC10 (Standby with CBR refresh) (L/LS-version)
Self refresh mode current (LS-version)
I CC11
--
4.0
mA
Input leakage current Output leakage current Output high voltage Output low voltage
I LI I LO VOH VOL
-10 -10 2.4 0
10 10 VCC 0.4
A A V V
Notes: 1. I CC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4. VIH VCC - 0.2 V, 0 V V IL 0.2 V
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HB56SW464DBJ Series
Capacitance (Ta = 25C, VCC = 3.3 V +0.3, -0.15 V)
Parameter Input capacitance (Address) Input capacitance (RAS) Input capacitance (CAS) Input capacitance (WE, OE) I/O capacitance (DQ) Symbol CI1 CI2 CI3 CI4 CI/O Typ -- -- -- -- -- Max 90 64 30 120 24 Unit pF pF pF pF pF Notes 1 1 1, 2 1 1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout.
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HB56SW464DBJ Series
AC Characteristics (Ta = 0 to +70C, VCC = 3.3 V +0.3, -0.15 V, VSS = 0 V)*1, *2, *18, *19
Test Conditions * * * * * Input rise and fall times: 2 ns Input levels: 0 V, 3.0 V Input timing reference levels: 0.8 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
60 ns Parameter Random read or write cycle time RAS precharge time CAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS delay time from Din Transition time (rise and fall) Refresh period (2,048 cycles) Refresh period (2,048 cycles) (L/LS-version) Symbol t RC t RP t CP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP t OED t DZO t DZC tT t REF t REF Min 104 40 10 60 10 0 10 0 10 14 12 13 40 5 15 0 0 2 -- -- Max -- -- -- 10000 10000 -- -- -- -- 45 30 -- -- -- -- -- -- 50 32 128 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms 5 6 6 7 3 4 Notes
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HB56SW464DBJ Series
Read Cycle
60 ns Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Read command hold time to CAS Read command hold time from RAS Read command hold time to RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time Output data hold time from OE Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time Output data hold time from RAS Output buffer turn-off time to RAS Output buffer turn-off to WE WE to Din delay time RAS to Din delay time RAS next CAS delay time Symbol t RAC t CAC t AA t OEA t RCS t RCH t RCHR t RRH t RAL t CAL t CLZ t OH t OHO t OFF t OEZ t CDD t OHR t OFR t WEZ t WED t RDD t RNCD Min -- -- -- -- 0 0 60 5 30 18 0 3 3 -- -- 15 3 -- -- 15 15 60 Max 60 15 30 15 -- -- -- -- -- -- -- -- -- 15 15 -- -- 15 15 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13, 22 13 5 22 22 22 12 12 Notes 8, 9 9, 10, 17 9, 11, 17 9, 21
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HB56SW464DBJ Series
Write Cycle
60 ns Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Symbol t WCS t WCH t WP t RWL t CWL t DS t DH Min 0 10 10 10 10 0 10 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns 15 15 Notes 14
Read-Modify-Write Cycle
60 ns Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time WE Symbol t RWC t RWD t CWD t AWD t OEH Min 135 79 34 49 15 Max -- -- -- -- -- Unit ns ns ns ns ns 14 14 14 Notes
Refresh Cycle
60 ns Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) WE setup time (CBR refresh cycle) WE hold time (CBR refresh cycle) RAS precharge to CAS hold time Symbol t CSR t CHR t WRP t WRH t RPC Min 5 10 0 10 5 Max -- -- -- -- -- Unit ns ns ns ns ns Notes
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HB56SW464DBJ Series
EDO Page Mode Cycle
60 ns Parameter EDO page mode cycle time EDO page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge Output data hole time from CAS low CAS hold time refferred OE CAS to OE setup time Read command hold time from CAS precharge Symbol t HPC t RASP t CPA t CPRH t DOH t COL t COP t RCHC Min 25 -- -- 35 3 10 5 35 Max -- 100000 35 -- -- -- -- -- Unit ns ns ns ns ns ns ns ns 9, 17 Notes 20 16 9, 17
EDO Page Mode Read-Modify-Write Cycle
60 ns Parameter EDO page mode read-modify-write cycle time WE delay time from CAS precharge Symbol t HPRWC t CPW Min 68 54 Max -- -- Unit ns ns 14 Notes
Self Refresh Mode (LS-version)
60 ns Parameter RAS pulse width (Self refresh) RAS precharge time (Self refresh) CAS hold time (Self refresh) Symbol t RASS t RPS t CHS Min 100 110 -50 Max -- -- -- Unit s ns ns Notes
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HB56SW464DBJ Series
Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh cycle or CAS-before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD tRAD (max) + tAA (max)- tCAC (max), then access time is controlled exclusively by t CAC . 4. Operation with the t RAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that t RCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max). 11. Assumes that t RAD tRAD (max) and tRCD + tCAC (max) tRAD + tAA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD , and tCPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics onry; if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD tRWD (min), tCWD tCWD (min), and tAWD tAWD (min) or tCWD tCWD (min), tAWD tAWD (min) and tCPW t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referred to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. t RASP defines RAS pulse width in EDO page mode cycles. 17. Access time is determined by the longest among t AA , t CAC and t CPA. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. After RAS is reset, if tOEH tCWL, the DQ pin will remain open circuit (high impedance); t OEH < tOEH, invalid data will be out at each DQ. 19. All the V CC and VSS pins shall be supplied with the same voltages. 20. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + tCP + 2tT) becomes greater than the specified t HPC (min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). 21. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large V CC / VSS line noise, which causes to degrade V IH min./ V IL max level. 22. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between t OHR and t OH , and between t OFR and t OFF.
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HB56SW464DBJ Series
23. Please do not use tRASS timing, 10 s tRASS 100 s. During this period, the device is in transition state from normal operation mode to self refresh mode. If t RASS 100 s, then RAS precharge time should use tRPS instead of tRP. 24. If you use distributed CBR refresh mode with 15.6 s interval in normal read/write cycle, CBR refresh should be executed within 15.6 s immediately after exiting from and before entering into self refresh mode. 25. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 2048 of distributed CBR refresh with 15.6 s interval should be executed within 32 ms immediately after exiting from and before entering into the self refresh mode. 26. XXX: H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL.
16
HB56SW464DBJ Series
Timing Waveforms*26
Read Cycle
t RC t RAS t RP
RAS t CSH t RCD tT t RSH t CAS t CRP
CAS
t RAD t ASR t ASC t RAL t CAL t CAH
t RAH
Address
Row
Column t RRH t RCHR t RCS t RCH
WE t WED t DZC t CDD t RDD Din High-Z
t DZO
t OEA
t OED
OE t OEZ t OHO t OFF t OH t OFR t OHR t WEZ Dout Dout
t CAC t AA t RAC t CLZ
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HB56SW464DBJ Series
Early Write Cycle
t RC t RAS t RP
RAS t CSH t RCD tT CAS t RSH t CAS t CRP
t ASR
t RAH
t ASC
t CAH
Address
Row
Column
t WCS
t WCH
WE
t DS
t DH
Din
Din
Dout
High-Z* * t WCS t WCS (min)
18
HB56SW464DBJ Series
Delayed Write Cycle*18
t RC t RAS
t RP
RAS t CSH t RCD tT CAS t ASR t RAH t ASC t CAH t RSH t CAS t CRP
Address
Row
Column t CWL t RCS t RWL t WP
WE
t DZC
t DS
t DH
Din
High-Z
Din t OEH t OED
t DZO

OE t OEZ t CLZ Dout High-Z Invalid Dout 19
HB56SW464DBJ Series
Read-Modify-Write Cycle*18
t RWC t RAS
t RP
RAS tT t RCD t CAS t CRP
CAS t RAD t ASR t RAH t ASC t CAH
Address
Row t RCS
Column t CWD t AWD t RWD tCWL t RWL t WP
WE t DZC t DS Din
High-Z Din
t DH
t DZO
t OED t OEA
t OEH
OE t CAC t AA t RAC t OEZ t OHO
High-Z
Dout t CLZ
Dout
20
HB56SW464DBJ Series
RAS-Only Refresh Cycle
t RC t RAS RAS tT t CRP t RPC t CRP t RP
CAS
t ASR Address t OFR t OFF Dout Row
t RAH
High-Z
21
HB56SW464DBJ Series
CAS-Before-RAS Refresh Cycle
t RC t RP RAS t RPC CAS t CSR tT t CHR t RPC t CRP t RAS t RP
,
t CP t WRP t WRH t CP WE Address t OFR t OFF Dout High-Z 22
HB56SW464DBJ Series
EDO Page Mode Read Cycle
t RP t RASP tT CAS t RCS
WE
t RNCD
RAS
t HPC t HPC tCAS t RCHC t CPRH t CP t t CRP
t CSH t CAS t RCHR
t CP
t HPC t CAS
t CP
RSH
tCAS t RRH t RCH
t RCH t RCS
tASR
Address
tRAH tASC Row
tCAH
t ASC t CAH Column 2 t CAL
t ASC t CAH Column 3 t CAL
tASC
t RAL t CAH
Column 4
t WED
Column 1 t CAL tDZC
t CAL tRDD tCDD
Din
High-Z tDZO tCOL tCOP tOED

OE
tOEA
tCPA
tCPA
tCAC tAA
tAA tCAC
tOEZ
tWEZ
tOHO
tCPA tAA tCAC
tAA
tOEZ
tOFR tOHR tOEZ
tCAC
tRAC
tOEA
tDOH
tOHO
tOEA
tOHO tOFF tOH
Dout
Dout 1
Dout 2
Dout 2
Dout 3
Dout 4
23
HB56SW464DBJ Series
EDO Page Mode Early Write Cycle
t RASP t RP
RAS tT t CSH t RCD t CAS t CP t HPC t CAS t CP t RSH t CAS t CRP
CAS
t ASR t RAH
t ASC
t CAH
t ASC
tCAH
t ASC t CAH
Address
Row
Column 1
Column 2
Column N
t WCS
t WCH
t WCS
t WCH
t WCS
t WCH
WE
t DS
t DH
t DS
t DH
t DS
t DH
Din
Din 1
Din 2
Din N
Dout
High-Z*
* t WCS
t WCS (min)
24
HB56SW464DBJ Series
EDO Page Mode Delayed Write Cycle*18
t RASP t RP RAS tT t CSH t RCD t CAS t CP t HPC t CAS t CP t RSH t CAS t CRP
CAS
t RAD t ASR t RAH Address Row t ASC t CAH Column 1 t CWL t RCS WE t WP t DZC t DS t DH Din t DZO t OED Din 1 t DZO t OED t WP t DZC t DS t DH Din 2 t DZO t OED t WP t DZC t DS t DH Din N t RCS t ASC t CAH Column 2 t CWL t RCS t ASC t CAH Column N t CWL t RWL

t OEH t OEH t OEH OE t CLZ t CLZ t CLZ t OEZ t OEZ t OEZ Dout High-Z
Invalid Dout Invalid Dout Invalid Dout
25
HB56SW464DBJ Series
EDO Page Mode Read-Modify-Write Cycle*18
t RASP t RP RAS tT t CP t RCD t CAS t CAS t HPRWC t CP t RSH t CAS
t CRP
CAS
t RAD t ASR t ASC t RAH Row t CAH Column 1 t RWD t AWD t CWD WE t RCS t WP t DZC t DS t DH Din t DZO
t OED
t ASC t CAH Column 2 t CWL t RCS t CPW t AWD t CWD t RCS t CWL
t ASC t CAH Column N t CPW t AWD t CWD t RWL t CWL
Address
t WP t DZC t DS t DH Din 2 t OED t OEH t DZO t OED
t WP t DZC t DS t DH Din N
Din 1 t DZO t OEH
t OEH
*
OE t OHO t OHO t OHO t AA t OEA t CAC t RAC t AA t CPA t OEA t CAC t AA t CPA t OEA t CAC t CLZ t OEZ t CLZ t OEZ t CLZ t OEZ
High-Z
Dout
Dout 1
Dout 2
Dout N
26
HB56SW464DBJ Series
EDO Page Mode Mix Cycle (1)
t RP RAS tT CAS t RCD t WCS WE t ASC tRAH Row t WCH t RCS tCPW tAWD tCAH t ASC t CAH Column 2 t CAL t DS
Din
t RASP t CRP tCAS tRSH t RCS tWP t RAL t CAH Column 4 t CAL t DS High-Z tOED t DH Din 3 tWED tRDD tCDD t RRH t RCH
t CP t CAS t CSH t CAS
t CP tCAS
t CP
tASR Address
tASC t CAH Column 3
tASC
Column 1
t DH Din 1

tCPA tAA tOEA tCPA tCPA tAA t OEZ tAA tOFR tWEZ tOEZ tCAC tOHO tOFF tOH tCAC t DOH tCAC t OHO tOEA Dout Dout 2
Dout 3
OE
Dout 4
27
HB56SW464DBJ Series
EDO Page Mode Mix Cycle (2)
t RP t RASP
t RNCD
RAS
tT CAS
t CSH t CAS t RCD t RCS t RCHR
t CP t CAS
t CP tCAS
t CP tCAS t RCS tCPW tWP t RAL tASC t CAH Column 4 t CAL t DS t DH Din 3 tOED tCOP tRSH
t CRP
t RCH tWCS t WCH
t RCS
t RRH t RCH
WE
tASR
Address
t ASC tRAH Row
tCAH
t ASC t CAH Column 2
t ASC t CAH Column 3 t CAL
Column 1 t CAL
t DS
Din
t DH Din 2
tRDD tCDD
High-Z
tOED
OE
tWED
tCOL t OEA tOEZ t OHO tCPA tAA tCAC tOEZ t OHO
Dout 3
tAA tOEA tCAC tRAC
tCPA tAA tCAC tOEA
tOFR tWEZ tOEZ tOHO tOFF tOH Dout 4
Dout
Dout 1
28
HB56SW464DBJ Series
Self Refresh Cycle (LS-version)* 23, 24, 25
t RASS
t RP
t RPS
RAS t RPC tT t CRP t CHS
, ,
t CP t CSR CAS t WRP WE t OFR t OFF Dout
t WRH
, + & $
High-Z 29
HB56SW464DBJ Series
Physical Outline
Unit: mm/inch
67.60 2.661 24.50 0.965
,,,,,,,,,,,,,,,,,,,,,,,,, 2R0.118Min. ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,, (front) ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,
23.20 0.913 2.50 0.098 B 4.60 0.181 32.80 1.291 A
143 1
63.60 2.504 (Datum -A-)
3.80Max. 0.150Max. 2R3.00Min
,, , ,, , ,, , ,, , ,, , ,, , ,, , ,, , ,, ,
3.20Min. 0.126Min.
20.00 0.787
3.30 0.130
2- o1.80 2- o0.071 2-R2.00 2-R0.079
,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,, (back) ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,
(Datum -A-)
144 2
2.00Min. 0.079Min.
Detail A
Detail B
(DATUM -A-) 0.60 0.05 0.024 0.002 2.5 0.098 R0.75 R0.030
0.25 Max. 0.010 Max.
0.80 0.031
4.00 0.10 0.157 0.004
2.55 Min. 0.100 Min.
4.00 0.10 0.157 0.004
3.70 0.146
2.10 0.083 23.20 0.913
4.60 0.181 32.80 1.291
1.50 0.10 0.059 0.004
30
4.00Min. 0.157Min.
1.00 0.10 0.039 0.004
25.40 1.000 6.00 0.236
HB56SW464DBJ Series
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207
Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00
Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322
Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071
Copyright (c) Hitachi, Ltd., 1997. All rights reserved. Printed in Japan.
31
HB56SW464DBJ Series
Revision Record
Rev. Date 0.0 1.0 Jan. 10, 1997 May. 30, 1997 Contents of Modification Initial issue (referred to HM51W17805 rev. 3.0) Unification of HB56SW464DBJ, HB56SW464DBJ-6 Low power dissipation Active mode max: 3.6 W to 3.024W Addition of Standby mode (CMOS) max: 8.64 mW (L/LS-version) Change of Serial PD matrix DC Characteristics ICC1, I CC3, I CC6 max: 1000 mA to 840 mA ICC7 max: 1000 mA to 760 mA AC Characteristics tRCD min: 20 ns to 14 ns tRAD min: 15 ns to 12 ns tRSH min: 15 ns to 13 ns tCSH min: 48 ns to 40 ns tRRH min: 0 ns to 5 ns Addition of tRNCD tRWC min: 149 ns to 135 ns tRWD min: 82 ns to 79 ns tCWD min: 37 ns to 34 ns tAWD min: 52 ns to 49 ns tRPC min: 0 ns to 5 ns tHPRWC min: 79 ns to 68 ns Addition of notes19, 21 Drawn by T. Sugano Approved by K. Inoue
32

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