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HB56R872ES Series
8,388,608-Word x 72-Bit(ECC) High Density Dynamic RAM Module
Rev. 0 Aug. 17, 1995
The HB56R872ES belongs to 8 Byte DIMM (Dual In-line Memory Module) family, and has been developed as an optimized main memory solution for 4 and 8 Byte processor applications. The HB56R872ES is a 8M x 72 dynamic RAM module, mounted 36 pieces of 16-Mbit DRAM (HM5116400) sealed in TCP package and 2 pieces of 16-bit BiCMOS line driver (74ABT16244DGG) sealed in TSSOP package. An outline of the HB56R872ES is 168-pin socket type package (dual read out). Therefore, the HB56R872ES makes high density mounting possible without surface mount technology. The HB56R872ES provides common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the its module board.
Features
* 168-pin socket type package (Dual read out) Lead pitch : 1.27 mm * Single 5 V (5%) supply * High speed Access time : tRAC = 60 / 70 /80 ns (max.) Access time : tCAC = 20 / 23 /25 (max.) * Low power dissipation Active mode: 8.37 / 7.42 / 6.95 W (max.) Standby mode: 714 mW (max.) * Buffered input except /RAS and DQ * 4 byte interleave enabled, dual address input (A0/B0) * Fast page mode capability * 4,096 refresh cycle/64 ms * 2 variations of refresh /RAS - only refresh /CAS - before - /RAS refresh * TTL compatible
HB56R872ES Series
Ordering Information
Type No. HB56R872ES-6B HB56R872ES-7B HB56R872ES-8B Access time 60ns 70ns 80ns Package 168-pin dual read out socket type Contact pad Gold
Pin Arrangement
Front side Back side
1 pin 85 pin
10 pin 94 pin
11 pin 95 pin
40 pin 124 pin
41 pin 125 pin
84 pin 168 pin
2
HB56R872ES Series
Pin Arrangement
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin Name Vss DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 DQ8 Vss DQ9 DQ10 DQ11 DQ12 DQ13 Vcc DQ14 DQ15 DQ16 DQ17 Vss NC NC Vcc /WE0 /CE0 NC /RE0 /OE0 Vss A0 A2 A4 A6 Pin No. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 Pin Name Vss /OE2 /RE2 /CE4 NC /WE2 Vcc NC NC DQ18 DQ19 Vss DQ20 DQ21 DQ22 DQ23 Vcc DQ24 NC NC NC NC DQ25 DQ26 DQ27 Vss DQ28 DQ29 DQ30 DQ31 Vcc DQ32 DQ33 DQ34 DQ35 Vss Pin No. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Pin Name Vss DQ36 DQ37 DQ38 DQ39 Vcc DQ40 DQ41 DQ42 DQ43 DQ44 Vss DQ45 DQ46 DQ47 DQ48 DQ49 Vcc DQ50 DQ51 DQ52 DQ53 Vss NC NC Vcc NC /CE1 NC /RE1 NC Vss A1 A3 A5 A7 Pin No. 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 Pin Name Vss NC /RE3 /CE5 NC /PDE Vcc NC NC DQ54 DQ55 Vss DQ56 DQ57 DQ58 DQ59 Vcc DQ60 NC NC NC NC DQ61 DQ62 DQ63 Vss DQ64 DQ65 DQ66 DQ67 Vcc DQ68 DQ69 DQ70 DQ71 Vss
3
HB56R872ES Series
37 38 39 40 41 42 A8 A10 NC Vcc NC NC 79 80 81 82 83 84 PD1 PD3 PD5 PD7 IDO(Vss) Vcc 121 122 123 124 125 126 A9 A11 NC Vcc NC B0 163 164 165 166 167 168 PD2 PD4 PD6 PD8 ID1 Vcc
Pin Description
Pin Name A0 to A11, B0 Function Address Input Row Address Column Address Refresh Address Data - in /Data - out Row Address Strobe Column Address Strobe Read / Write Enable Output Enable Power Supply Ground Presence Detect ID bit Presence Detect Enable Non Connection :A0 to A11, B0 :A0 to A11, B0 : A0 to A9, B0 :A0 to A11, B0
DQ0 to DQ71 /RE0 to /RE3 /CEO ,/CE1 ,/CE4 ,/CE5 /WE0 ,/WE2 /OE0 ,/OE2 Vcc Vss PD1 to PD8 ID0, ID1 /PDE NC
Presence Detect Pin Assignment
/PDE=Low Pin Name Pin No. -6B PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 79 163 80 164 81 165 82 166 0 0 1 1 0 1 1 0 -7B 0 0 1 1 0 0 1 0 -8B 0 0 0 1 0 1 0 0 All High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z /PDE=High
1 : High Level (Driver Output)
4
HB56R872ES Series
0 : Low Level (Driver Output)
5
HB56R872ES Series
Block Diagram
/RE0 /CE0 /WE0 /OE0 /RE1 /CE1 R4 R2 R0 R5 /RE2 /CE4 /WE2 /OE2 /RE3 /CE5 R6 R3 R1 R7
/ CAS / RAS / WE / OE DQ0 DQ1 DQ2 DQ3 I/O0 I/O1 I/O2 I/O3 I/O0 I/O1 I/O2 I/O3
/ CAS / RAS / WE / OE DQ36 DQ37 DQ38 DQ39 I/O0 I/O1 I/O2 I/O3
/ CAS / RAS / WE / OE I/O0 I/O1 I/O2 I/O3
/ CAS / RAS / WE / OE
D0
D18
D9
D27
/ CAS / RAS / WE / OE DQ4 DQ5 DQ6 DQ7 I/O0 I/O1 I/O2 I/O3 I/O0 I/O1 I/O2 I/O3
/ CAS / RAS / WE / OE DQ40 DQ41 DQ42 DQ43 I/O0 I/O1 I/O2 I/O3
/ CAS / RAS / WE / OE I/O0 I/O1 I/O2 I/O3
/ CAS / RAS / WE / OE
D1
D19
D10
D28
/ CAS / RAS / WE / OE DQ8 DQ9 DQ10 DQ11 I/O0 I/O1 I/O2 I/O3 I/O0 I/O1 I/O2 I/O3
/ CAS / RAS / WE / OE DQ44 DQ45 DQ46 DQ47 I/O0 I/O1 I/O2 I/O3
/ CAS / RAS / WE / OE I/O0 I/O1 I/O2 I/O3
/ CAS / RAS / WE / OE
D2
D20
D11
D29
/ CAS / RAS / WE / OE DQ12 DQ13 DQ14 DQ15 I/O0 I/O1 I/O2 I/O3 I/O0 I/O1 I/O2 I/O3
/ CAS / RAS / WE / OE DQ48 DQ49 DQ50 DQ51 I/O0 I/O1 I/O2 I/O3
/ CAS / RAS / WE / OE I/O0 I/O1 I/O2 I/O3
/ CAS / RAS / WE / OE
D3
D21
D12
D30
/ CAS / RAS / WE / OE DQ16 DQ17 DQ18 DQ19 I/O0 I/O1 I/O2 /O3 I/O0 I/O1 I/O2 I/O3
/ CAS / RAS / WE / OE DQ52 DQ53 DQ54 DQ55 I/O0 I/O1 I/O2 I/O3
/ CAS / RAS / WE / OE I/O0 I/O1 I/O2 I/O3
/ CAS / RAS / WE / OE
D4
D22
D13
D31
/ CAS / RAS / WE / OE DQ20 DQ21 DQ22 DQ23 I/O0 I/O1 I/O2 I/O3 I/O0 I/O1 I/O2 I/O3
/ CAS / RAS / WE / OE DQ56 DQ57 DQ58 DQ59 I/O0 I/O1 I/O2 I/O3
/ CAS / RAS / WE / OE I/O0 I/O1 I/O2 I/O3
/ CAS / RAS / WE / OE
D5
D23
D14
D32
/ CAS / RAS / WE / OE DQ24 DQ25 DQ26 DQ27 I/O0 I/O1 I/O2 I/O3 I/O0 I/O1 I/O2 I/O3
/ CAS / RAS / WE / OE DQ60 DQ61 DQ62 DQ63 I/O0 I/O1 I/O2 I/O3
/ CAS / RAS / WE / OE I/O0 I/O1 I/O2 I/O3
/ CAS / RAS / WE / OE
D6
D24
D15
D33
/ CAS / RAS / WE / OE DQ28 DQ29 DQ30 DQ31 I/O0 I/O1 I/O2 I/O3 I/O0 I/O1 I/O2 I/O3
/ CAS / RAS / WE / OE DQ64 DQ65 DQ66 DQ67 I/O0 I/O1 I/O2 I/O3
/ CAS / RAS / WE / OE I/O0 I/O1 I/O2 I/O3
/ CAS / RAS / WE / OE
D7
D25
D16
D34
/ CAS / RAS / WE / OE DQ32 DQ33 DQ34 DQ35 I/O0 I/O1 I/O2 I/O3 I/O0 I/O1 I/O2 I/O3
/ CAS / RAS / WE / OE DQ68 DQ69 DQ70 DQ71 I/O0 I/O1 I/O2 I/O3
/ CAS / RAS / WE / OE I/O0 I/O1 I/O2 I/O3
/ CAS / RAS / WE / OE
D8
D26
D17
D35
A0 B0 A1 to A11 Vcc Vss
R8 R9 R10 to R20
D0 to D8, D18 to D26 D9 to D17, D27 to D35
PD1 to PD8
Vcc or Vss J6 ID1
PD1 to PD8
Vss
D0 to D35 D0 to D35 D0 to D35 *D0 to D35 : HM5116405 : 74ABTI6244
0.10 F x 20 pcs 0.68 F x 4 pcs
R0-R20
: Chip Resistor
6
HB56R872ES Series
Physical Outline Unit: mm/inch
Unit : mm inch
Physical Outline
133.35 5.250 3.00 0.118 127.35 5.014 Protective cover (*1)
4.80 0.189
4.00 0.157 25.40 1.000
4.00 min
1
84
C 8.89 0.350 11.43 0.450 36.83 1.450 115.57 4.550
B 54.61 2.150
A 1.27-0.10 0.050-0.004
127.35 5.014 1.175 125.0 4.921
0.882
22.4
2 - 3.0 Optional hole
1 84
3.00 0.118
168 85
0.118
3.00
(*1) Protective cover material will be Fe-Ni or stainless steel
0.157 min
17.78
0.700
0.118
3.00
7
HB56R872ES Series
Absolute Maximum Ratings
Parameter Voltage on any pin relative to Vss. For 10ns or less Supply voltage relative to Vss Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT Vcc Iout Pt Topr Tstg Value -0.5 to +7.0 -1.5 -0.5 to +7.0 50 37 0 to +70 -55 to +125 Unit V V mA W C C
Electrical Characteristics
Recommended DC Operating Condition (Ta = 0 to 70C)
Parameter Supply voltage Symbol Vss Vcc Input high voltage Input low voltage For 10ns or less Note : 1. All voltage referenced to Vss. ViH ViL Min. 0 4.75 2.4 -0.5 -1.5 Typ. 0 5.0 Max. 0 5.25 5.5 0.8 Unit V V V V 1 1 1 Note
8
HB56R872ES Series
DC Characteristics (Ta=0 to 70C, Vcc=5V5 %, Vss=0V)
HB56R872ES Parameter Symbol -6B Min.
Operating current Standby current Icc1 Icc2 -
-7B Max.
1594 136
-8B Max.
1414 136
Unit Test Condition
Note
Min.
-
Min. Max.
1324 136 mA tRC=min. mA TTL interface /RAS/CAS=ViH Dout=High-Z mA CMOS interface /RAS/CASVcc-0.2V Dout=High-Z mA tRC=min. mA /RAS=ViH /CAS=ViL Dout=enable mA tRC=min. mA tPC=min. A A V V 0VVin5.5V 0VVout5.5V Dout=disable High Iout=-5mA Low Iout=4.2mA 1,3 2 1 1,2
-
100
-
100
-
100
/RAS-only refresh current Standby current /CAS-before-/RAS refresh current Fast page mode current Input leakage current output leakage current output high voltage output low voltage
Icc3 Icc5 Icc6 Icc7 ILI ILO VoH VoL
-10 -10 2.4 0
1594 244 1594 1414 10 10 Vcc 0.4
-10 -10 2.4 0
1414 244 1414 1234 10 10 Vcc 0.4
-10 -10 2.4 0
1324 244 1324 1054 10 10 Vcc 0.4
Notes : 1. Icc depends on output load condition when the device is selected, Icc max. is specified at the output open condition. 2. Address can be changed once or less while /RAS=ViL. 3. Address can be changed once or less while /CAS=ViH.
9
HB56R872ES Series
Capacitance (Ta=25C, Vcc=5V5%)
Parameter Input capacitance Input capacitance Input capacitance Output capacitance (Address) (/CE,/WE,/OE) (/RE) (DQ) Symbol CI1 CI2 CI3 CI/O Typ. Max. 20 20 78 27 Unit pF pF pF pF Notes 1 1 1 1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. /CAS=ViH to disable Dout.
AC Characteristics (Ta=0 to 70C, Vcc=5V5%, Vss=0V) *1, *2, *3,, *19, *20 Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HB56R872ES Parameter Symbol -6B Min.
Random read or write cycle time /RAS precharge time /CAS precharge time /RAS pulse width /CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time /RAS to /CAS delay time /RAS to column address delay time /RAS hold time /CAS hold time /CAS to /RAS precharge time /OE to Din delay time /OE delay time from Din /CAS delay time from Din Transition time (rise and fall) Refresh period tRC tRP tCP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tOED tDZO tDZC tT tREF 110 40 10 60 15 5 10 0 10 20 15 20 60 10 20 0 0 3 -
-7B Max.
10000 10000 40 25 50 64
-8B Max.
10000 10000 47 30 50 64
Unit Max.
10000 10000 55 35 50 64 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
Notes
Min.
130 50 10 70 18 5 10 0 15 20 15 23 70 10 23 0 0 3 -
Min.
150 60 10 80 20 5 10 0 15 20 15 25 80 10 25 0 0 3 -
4 5
6 7 7 8 22
10
HB56R872ES Series
Read Cycle
HB56R872ES Parameter Symbol -6B Min.
Access time from /RAS Access time from /CAS Access time from address Access time from /OE Read command setup time Read command hold time to /CAS Read command hold time to /RAS Column address to /RAS lead time Column address to /CAS lead time /CAS to output in Low-Z Output data hold time Output data hold time from /OE Output buffer turn-off time Output buffer turn-off to /OE /CAS to Din delay time tRAC tCAC tAA tOEA tRCS tRCH tRRH tRAL tCAL tCLZ tOH tOHO tOFF tOEZ tCDD 0 0 0 35 30 2 3 3 20
-7B Max.
60 20 35 20 20 20 -
-8B Max.
70 23 40 23 20 20 -
Unit Max.
80 25 45 25 20 20 ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns
Notes
Min.
0 0 0 40 35 2 3 3 23
Min.
0 0 0 45 40 2 3 3 25
9,10,21 10,11,18,21 10,11,18,21 10,21
13 13
14 14 6
Write Cycle
HB56R872ES Parameter Symbol -6B Min.
Write command setup time Write command hold time Write command pulse width Write command to /RAS lead time Write command to /CAS lead time Data-in setup time Data-in hold time tWCS tWCH tWP tRWL tCWL tDS tDH 0 10 10 20 15 0 15
-7B Max.
-
-8B Max.
-
Unit Max.
ns ns ns ns ns ns ns
Notes
Min.
0 15 10 23 18 0 20
Min.
0 15 10 25 20 0 20
15
16 16
11
HB56R872ES Series
Read-Modify-Write Cycle
HB56R872ES Parameter Symbol -6B -7B -8B Max.
ns ns ns ns ns 15 15 15
Unit
Notes
Min. Max. Min. Max. Min.
Read-modify-write cycle time /RAS' to /WE delay time /CAS to /WE delay time Column address to /WE delay time /OE hold time from /WE tRWC tRWD tCWD tAWD tOEH 155 90 40 55 15 181 103 46 63 18 205 115 50 70 20
Refresh Cycle
HB56R872ES Parameter Symbol -6B Min.
/CAS setup time (CBR refresh cycle) /CAS hold time cycle) /WE setup time /WE hold time /RAS precharge to /CAS hold time (CBR refresh tCSR tCHR tWRP tWRH tRPC 10 10 5 10 0
-7B Max.
-
-8B Max.
-
Unit Max.
ns ns ns ns ns
Notes
Min.
10 10 5 10 0
Min.
10 10 5 10 0
Fast Page Mode Cycle
HB56R872ES Parameter Symbol -6B Min. Max.
Fast page mode cycle time Fast page mode /RAS pulse width Access time from /CAS precharge /RAS hold time from /CAS precharge tPC tRASP tCPA tCPRH 40 40 100000 40 -
-7B Min. Max.
45 45 100000 45 -
-8B Min.
50 50
Unit Max.
100000 50 ns ns ns ns
Notes
17 10,18,21
12
HB56R872ES Series
Fast Page Mode Read-Modify-Write Cycle
HB56R872ES Parameter Symbol -6B Min.
Fast page mode read-modify-write cycle time /WE delay time from /CAS precharge tPRWC tCPW 85 60
-7B Max.
-
-8B Max.
-
Unit Max.
ns ns
Notes
Min.
96 68
Min.
105 75
15
13
HB56R872ES Series
Notes 1. AC measurements assume tT=5ns. 2. An initial pause of 200us is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing /RAS-only refresh or /CAS-before/RAS refresh). If the internal refresh counter is used, a minimum of eight /CAS-before-/RAS refresh cycles are required. 3. Only row address is indispensable on address A10 and A11. 4. Operation with the tRCD(max.) limit insures that tRAC(max..) can be met, tRCD(max.) is specified as a reference point only; if tRCD is greater than the specified tRCD(max.) limit, then access time is controlled exclusively by tCAC. 5. Operation with the tRAD(max.) limit insures that tRAC(max.) can be met, tRAD(max.) is specified as a reference point only; if tRAD is greater than the specified tRAD(max.) limit, then access time is controlled exclusively by tAA. 6. Either tOED or tCDD must be satisfied. 7. Either tDZO or tDZC must be satisfied. 8. ViH(min.) and ViL(max.) are reference levels for measuring timing of input signals. Also, transition times are measured between ViH(min.) and ViL(max.). 9. Assumes that tRCD14
HB56R872ES Series
at each I/O and read out from each I/O. If 4 bits of I/O are equal (all 1s or 0s), data output pin is a high state during test mode read cycle, then the device has passed. If they are not equal, data output pin is a low state, then the device has failed. Refresh during test mode operation can be performed by normal read cycle or by WCBR refresh cycle. To get out of test mode and enter a normal operation mode, perform either a regular /CAS-before-/RAS refresh cycle or /RAS-only refresh cycle. 21. In a test mode read cycle, the value of tRAC, tAA, tCAC and tCPA is delayed by 2ns to 5ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 22. tREF is determined by 4,096 refresh cycle.
15
HB56R872ES Series
Timing Waveform *
Read Cycle
tRC tRAS /RAS tCSH tRCD tT /CAS tRSH tCAS tCRP tRP
tRAD tASR tRAH tASC
tRAL tCAL tCAH Column tRRH
Address
Row
tRCS /WE tDZC Din tDZO High-Z
tRCH
tCDD
tOEA
tOED
/OE tOEZ tOHO tOFF tOH
tCAC tAA tRAC tCLZ Dout
Dout
: H or L H : ViHmin Vin ViHmax L : ViLmin Vin ViLmax
16
HB56R872ES Series
Early Write Cycle
tRC tRAS /RAS tCSH tRCD tT /CAS tRSH tCAS tCRP tRP
tASR Address
tRAH
tASC
tCAH
Row
Column tWP tWCS tWCH
/WE tDS Din Din tDH
Dout
High-Z * *
* /OE : H or L
** :tWCStWCS(min.)
17
HB56R872ES Series
Delayed Write Cycle *19
tRC tRAS /RAS tCSH tRCD tT /CAS tRSH tCAS tCRP tRP
tASR tRAH Address Row
tASC
tCAH
Column tCWL tRWL tRCS tWP
/WE tDZC Din High-Z tDS tDH Din tOEH tDZO /OE tOED
tOEZ tCLZ Dout
Invalid Dout
High-Z * *tOEH - tCWL
18
HB56R872ES Series
Read - Modify - Write Cycle *19
tRWC
tRAS
tRP
/RAS
tRCD tT
tCAS
tCRP
/CAS tRAD tASR Address tRAH tASC tCAH
Row tRCS
Column tCWD tAWD tRWD tRWL tWP tCWL
/WE tDH
tDZC Din High-Z
tDS
Din
tDZO
tOED
tOEH
/OE
tOEZ tOHO Dout tRAC tAA tOEA tCAC
Dout tCLZ
High-Z * *tOEH > tCWL =
19
HB56R872ES Series
/RAS - Only Refresh Cycle
tRC tRAS /RAS tRP
tT tCRP /CAS tRPC tCRP
tASR Address
tRAH Row
tOFF High-Z Dout
* /OE, /WE : H or L ** Refresh address : A0 to A11 (RA0 to RA11)
20
HB56R872ES Series
/CAS - Before - /RAS Refresh Cycle
tRC tRP /RAS tT tRPC tCP /CAS tWRH tCSR tCHR tCRP tCP tCSR tRAS tRP tRAS
tRC tRP
tRPC tCHR
tWRP /WE
tWRP
tWRH
Address
tOFF High-Z Dout
* /OE : H or L
21
HB56R872ES Series
Fast Page Mode Read Cycle
tRASP tRP
/RAS tCSH tRCD tT /CAS tRAD tASR tRAH Address Row tRAL tCAL tASC tCAH Column 1 tCAL tASC tCAH Column 2 tRCS tRCS /WE tDZC tDZC tCDD High-Z tCDD High-Z tDZC tCDD High-Z tRCH tRCH tCAL tASC tCAH Column N tRCS tRRH tRCH tCAS tCP tCAS tCP tHPC tRSH tCAS tCRP
Din
tDZO
tOED
tDZO tOED
tDZO
tOED
/OE tOEA tAA tRAC tCLZ Dout tOHO tCAC tOH tAA tOEA tOH tAA tCPA tOEA tOH tOHO tOEZ tOFF Dout N
tCPA tOHO tOEZ tCAC tOEZ tCAC tCLZ tOFF tOFF tCLZ Dout2
Dout1
22
HB56R872ES Series
Fast Page Mode Early Write Cycle
tRASP tRP
/RAS
tCSH tRCD tT tCAS tCP tCAS tCP tCAS tPC tRSH tCRP
/CAS
tASR
tRAH
tASC
tCAH
tASC
tCAH
tASC
tCAH
Address
Row
Column 1
Column 2
Column N
tWP tWCS tWCH tWCS
tWP tWCH tWCS
tWP tWCH
/WE
tDS
tDH
tDS
tDH
tDS
tDH
Din
Din 1
Din 2
Din N
Dout
High-Z**
23
HB56R872ES Series
Fast Page Mode Delayed Write Cycle *19
tRASP
tRP
/RAS tCSH tRCD tT /CAS tRAD tRAH tASR Address Row tASC tCAH Column 1 tCWL tRCS tASC tCAH tASC tCAH tCAS tCP tCAS tCP tCAS tPC tRSH tCRP
Column 2 tCWL tRCS
Column N tCWL tRCS tRWL
/WE tWP tDZC tDZC tDS tDH Din 1 tDZO tOED tDZO tOEH tDS tWP tDZC tDH Din 2 tDZO tOED tOEH tOED tOEH tDS tWP tDH Din N
Din
/OE tOEZ tCLZ Dout Invalid Dout tCLZ Invalid Dout tOEZ tCLZ Invalid Dout High-Z * tOEZ
24
HB56R872ES Series
Fast Page Mode Read - Modify - Write Cycle *19
tRASP tRP
/RAS
tPRCW tT tRCD tCAS tCP tCAS tCP tCAS tCRP
/CAS
tRAD tRAH tASR tASC tCAH tASC tCAH Column 2 tCWL tCWL tASC tCAH Column N tCWL
Address
Row
Column 1
tRWD tAWD tRCS tCWD
tCPW tAWD tCWD
tCPW tAWD
tRCS
tRCS
tCWD
tRWL
/WE
tWP tDZC tDS tDH tWP tDS tDH tWP tDS tDH
tDZC
tDZC
Din
tDZO tOED
Din 1 tDZO tOED tOEH
Din 2 tDZO tOED tOEH
Din N
tOEH
/OE
tOEA tCAC tAA tRAC Dout 1 tCLZ
tOHO tOEZ tOEA tCAC tAA tCPA Dout 2 tCLZ
tOHO tOEZ tOEA tCAC tAA tCPA Dout N tCLZ
tOHO tOEZ
High-Z
*
Dout
25
HB56R872ES Series
Notice
When using this document, keep the following in mind: 1. 2. 3. 4. This document may, wholly or partially, be subject to change without notice. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
5. 6.
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