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HB56HW465DB Series
4196304-word x 64-bit High Density Dynamic RAM Module
ADE-203-666A (Z) Rev. 1.0 May. 20, 1997 Description
The HB56HW465DB Series is a 4 M x 64 Dynamic RAM Small Outline Dual In-line Memory Module (S. O. DIMM), mounted 4 pieces of 64-Mbit DRAM (HM5165165ATT/ALTT) sealed in TSOP package and 1 piece of serial EEPROM (24C02) for Presence Detect (PD). The HB56HW465DB Series offers Extended Data Out (EDO) Page Mode as a high speed access mode. An outline of the HB56HW465DB Series is 144pin Zig Zag Dual tabs socket type compact and thin package. Therefore, the HB56HW465DB Series makes high density mounting possible without surface mount technology. The HB56HW465DB Series provides common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the module board.
Features
* 144-pin Zig Zag Dual tabs socket type Outline: 67.60 mm (Length) x 25.40 mm (Height) x 3.80 mm (Thickness) Lead pitch : 0.80 mm * Single 3.3 V (0.3 V) * High speed Access time: tRAC = 60 ns/70 ns (max) Access time: tCAC = 15 ns/18 ns (max) * Low power dissipation Active mode: 2.60 W/2.24 W (max) Standby mode (TTL): 28.8 mW (max) Standby mode (CMOS): 14.4 mW (max) 2.9 mW (max) (L-version) * JEDEC standard outline S. O. DIMM * EDO page mode capability * 4096 refresh cycles: 64 ms : 128 ms (L-version)
HB56HW465DB Series
* 4 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh Self refresh (L-version)
Ordering Information
Type No. HB56HW465DB-6A HB56HW465DB-7A HB56HW465DB-6AL HB56HW465DB-7AL Access time 60 ns 70 ns 60 ns 70 ns Package Contact pad 144-pin small outline DIMM Gold
Pin Arrangement
Front Side
1pin 2pin
59pin 60pin
61pin 62pin
143pin 144pin
Back Side
Front side Pin No. 1 3 5 7 9 11 Signal name Pin No. VSS DQ0 DQ1 DQ2 DQ3 VCC 73 75 77 79 81 83
Back side Signal name Pin No. OE VSS NC NC VCC DQ16 2 4 6 8 10 12 Signal name Pin No. VSS DQ32 DQ33 DQ34 DQ35 VCC 74 76 78 80 82 84 Signal name NC VSS NC NC VCC DQ48
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HB56HW465DB Series
Front side Pin No. 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 Signal name Pin No. DQ4 DQ5 DQ6 DQ7 VSS CE0 CE1 VCC A0 A1 A2 VSS DQ8 DQ9 DQ10 DQ11 VCC DQ12 DQ13 DQ14 DQ15 VSS NC NC NC VCC NC WE RE0 NC 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 Back side Signal name Pin No. DQ17 DQ18 DQ19 VSS DQ20 DQ21 DQ22 DQ23 VCC A6 A8 VSS A9 A10 VCC CE2 CE3 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS SDA VCC 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 Signal name Pin No. DQ36 DQ37 DQ38 DQ39 VSS CE4 CE5 VCC A3 A4 A5 VSS DQ40 DQ41 DQ42 DQ43 VCC DQ44 DQ45 DQ46 DQ47 VSS NC NC NC VCC NC NC NC NC 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 Signal name DQ49 DQ50 DQ51 VSS DQ52 DQ53 DQ54 DQ55 VCC A7 A11 VSS NC NC VCC CE6 CE7 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS SCL VCC
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HB56HW465DB Series
Pin Description
Pin name A0 to A11 Function Address input Row address Column address Refresh address DQ0 to DQ63 RE0 CE0 to CE7 WE OE SDA SCL VCC VSS NC Data input/output Row address strobe (RAS) Column address strobe (CAS) Read/Write enable Output enable Serial data for PD Serial clock for PD Power supply Ground No connection A0 to A11 A0 to A9 A0 to A11
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HB56HW465DB Series
Serial PD Matrix*1
Byte No. Function described 0 1 2 3 4 5 6 7 8 9 Number of bytes used by module manufacturer Total SPD memory size Memory type Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 1 1 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 0 0 1 0 1 1 0 80 08 02 0C 0A 01 40 00 01 3C 46 0F 12 00 00 83 10 00 00 00 01 3E 4B C1 CE Future offerings Rev. 1 128 256 byte EDO 12 10 1 64 bits 0 (+) LVTTL t RAC = 60 ns t RAC = 70 ns t CAC = 15 ns t CAC = 18 ns Non parity Normal (15.625 s) Self refresh (31.3 s) 4M x 16
Number of row addresses bits 0
Number of column addresses bits 0
Number of banks Module data width
0 0
Module data width (continued) 0 Module interface signal levels 0 RAS access time -6A/-6AL RAS access time -7A/-7AL 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1
10
CAS access time -6A/-6AL CAS access time -7A/-7AL
11 12
Module configuration type Refresh rate/type -6A/-7A Refresh rate/type -6AL/-7AL (L-version)
13 14
DRAM width Error checking DRAM data width
15 to 31 Reserved for future offerings 32 to 61 Superset information 62 63 SPD revision Checksum for bytes 0 to 62 -6A Checksum for bytes 0 to 62 -7A Checksum for bytes 0 to 62 -6AL Checksum for bytes 0 to 62 -7AL
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HB56HW465DB Series
Serial PD Matrix*1 (cont)
Byte No. Function described 64 Manufacturer's JEDEC ID code Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 0 0 x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 x 1 1 0 0 1 1 0 0 0 1 1 1 0 0 1 0 1 0 0 0 x x 0 0 x 0 0 1 1 0 0 1 1 1 0 0 0 1 1 0 1 0 1 1 1 x x 0 0 x 0 0 1 1 0 1 1 1 1 0 0 1 1 1 0 0 0 0 1 0 x x 0 0 x 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 x x 1 0 x 0 0 1 1 0 1 1 1 1 1 0 1 1 1 0 0 1 0 0 0 x x 1 0 x 0 1 0 1 0 1 0 1 0 0 1 1 1 1 0 0 0 0 0 0 x x 1 0 x 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 x x 07 00 xx 48 42 35 36 48 57 34 36 35 44 42 5F 36 37 41 20 4C 20 30 20 xx xx *2 (ASCII8bit code) H B 5 6 H W 4 6 5 D B -- 6 7 A (Space) L (Space) Initial (Space) Year code* 3 (binary) Week code* 4 (binary) Hitachi
65 to 71 Manufacturer's JEDEC ID code 72 73 74 75 76 77 78 79 80 81 82 83 84 85 Manufacturing location Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number -6A/-6AL Manufacturer's part number -7A/-7AL 86 87 Manufacturer's part number Manufacturer's part number -6A/-7A Manufacturer's part number -6AL/-7AL (L-version) 88 to 90 Manufacturer's part number 91 92 93 94 Revision code Revision code Manufacturing date (year code) Manufacturing date (week code)
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HB56HW465DB Series
Serial PD Matrix*1 (cont)
Byte No. Function described 95 to 98 Assembly serial number 99 to 125 Manufacturer specific data 126 127 Reserved Reserved Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments *5 *6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 00
Notes: 1. All serial PD data are not protected. 0: Serial data, "driven Low", 1: Serial data, "driven High" 2. Byte 72 is manufacturing location code. (ex: in case of Japan, byte 72 is 4Ah. 4Ah shows "J" on ASCII code.) 3. Byte 93 (Manufacturing date-year code) ex: 61h shows year `97. 62h shows year `98. 4. Byte 94 (Manufacturing date-week code) ex: 0Bh shows week 11. 24h shows week 36. 5. Byte 95 through 98 are assembly serial number. 6. All bits of byte 99 through 125 are not defined ("1" or "0").
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HB56HW465DB Series
Block Diagram
RE0 WE OE RAS WE OE CE0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CE1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 UCAS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 D0 UCAS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 CE5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 LCAS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 CE4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 LCAS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 D2 RAS WE OE
RAS WE OE CE2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 CE3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 UCAS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 D1 UCAS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 CE7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 SDA SCL SCL A0 A1 A2 LCAS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 CE6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 LCAS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
RAS WE OE
D3
A0 to A11 VCC VSS 0.22 F x 6 pcs
A0 to A11 (D0 to D3) VCC (D0 to D3, U0) VSS (D0 to D3, U0)
SDA
U0
*D0 to D7: HM5165165 U0: 24C02
Notes : 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state.
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HB56HW465DB Series
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout PT Topr Tstg Value -0.5 to +4.6 -0.5 to +4.6 50 4.0 0 to +70 -55 to +125 Unit V V mA W C C
Recommended DC Operating Conditions (Ta = 0 to +70C)
Parameter Supply voltage Input high voltage Input low voltage Symbol VCC VIH VIL Min 3.0 2.0 -0.3 Typ 3.3 -- -- Max 3.6 VCC + 0.3 0.8 Unit V V V Notes 1, 2 1 1
Notes: 1. All voltage referred to VSS . 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level.
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HB56HW465DB Series
DC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, VSS = 0 V)
HB56HW465DB 60 ns Parameter Operating current* , *
1 2
70 ns Max 720 8 Min -- -- Max 620 8 Unit Test conditions mA mA t RC = min TTL interface RAS, UCAS, LCAS = VIH Dout = High-Z CMOS interface RAS, UCAS, LCAS VCC - 0.2 V Dout = High-Z CMOS interface RAS, UCAS, LCAS VCC - 0.2 V Dout = High-Z t RC = min RAS = VIH, UCAS, LCAS = VIL Dout = enable t RC = min t HPC = min CMOS interface Dout = High-Z CBR refresh: tRC = 31.3 s t RAS 0.3 s CMOS interface
RAS, UCAS, LCAS 0.2 V
Symbol Min I CC1 I CC2 -- --
Standby current
--
4
--
4
mA
Standby current (L-version)
I CC2
--
0.8
--
0.8
mA
RAS-only refresh current*2 Standby current*
1
I CC3 I CC5
-- --
720 20
-- --
620 20
mA mA
CAS-before-RAS refresh current EDO page mode current*1, * 3 Battery backup current* (Standby with CBR refresh) (L-version) Self refresh mode current (L-version) Input leakage current Output leakage current Output high voltage Output low voltage
4
I CC6 I CC7 I CC10
-- -- --
560 600 2.6
-- -- --
480 540 2.6
mA mA mA
I CC11
--
2
--
2
mA
Dout = High-Z I LI I LO VOH VOL -10 -10 2.4 0 10 10 VCC 0.4 -10 -10 2.4 0 10 10 VCC 0.4 A A V V 0 V Vin VCC + 0.3 V 0 V Vout VCC Dout = disable High Iout = -2 mA Low Iout = 2 mA
Notes : 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less within one page mode cycle tHPC . 4. VIH VCC - 0.2 V, 0 V VIL 0.2 V.
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HB56HW465DB Series
Capacitance (Ta = 25C, VCC = 3.3 V 0.3 V)
Parameter Input capacitance (Address) Input capacitance (RAS, WE, OE) Input capacitance (CAS) I/O capacitance (DQ) Symbol CI1 CI2 CI3 CI/O Typ -- -- -- -- Max 40 48 22 17 Unit pF pF pF pF Notes 1 1 1 1, 2
Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout.
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HB56HW465DB Series
AC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, VSS = 0 V) *1, *2 , *18,*19
Test Conditions * * * * * Input rise and fall time: 2 ns Input levels: VIL = 0 V, V IH = 3 V Input timing reference levels: 0.8 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HB56HW465DB 60 ns Parameter Random read or write cycle time RAS precharge time CAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS delay time from Din Transition time (rise and fall) Symbol Min t RC t RP t CP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP t OED t DZO t DZC tT 104 40 10 60 10 0 10 0 10 20 15 15 48 5 15 0 0 2 Max -- -- -- 10000 10000 -- -- -- -- 45 30 -- -- -- -- -- -- 50 70 ns Min 124 50 13 70 13 0 10 0 13 20 15 18 58 5 18 0 0 2 Max -- -- -- 10000 10000 -- -- -- -- 52 35 -- -- -- -- -- -- 50 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 6 7 3 4 Notes
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HB56HW465DB Series
Read Cycle
HB56HW465DB 60 ns Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Read command hold time to CAS Read command hold time from RAS Read command hold time to RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time Output data hold time from OE Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time Output data hold time from RAS Output buffer turn-off to RAS Output buffer turn-off to WE WE to Din delay time RAS to Din delay time Symbol Min t RAC t CAC t AA t OEA t RCS t RCH t RCHR t RRH t RAL t CAL t CLZ t OH t OHO t OFF t OEZ t CDD t OHR t OFR t WEZ t WED t RDD -- -- -- -- 0 0 60 0 30 18 0 3 3 -- -- 15 3 -- -- 15 15 Max 60 15 30 15 -- -- -- -- -- -- -- -- -- 15 15 -- -- 15 15 -- -- 70 ns Min -- -- -- -- 0 0 70 0 35 23 0 3 3 -- -- 18 3 -- -- 18 18 Max 70 18 35 18 -- -- -- -- -- -- -- -- -- 15 15 -- -- 15 15 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13 13 5 12 12 Notes 8, 9 9, 10, 17 9, 11, 17 9
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HB56HW465DB Series
Write Cycle
HB56HW465DB 60 ns Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Symbol Min t WCS t WCH t WP t RWL t CWL t DS t DH 0 10 10 10 10 0 10 Max -- -- -- -- -- -- -- 70 ns Min 0 13 10 13 13 0 13 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns 15 15 Notes 14
Read-Modify-Write Cycle
HB56HW465DB 60 ns Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE Symbol Min t RWC t RWD t CWD t AWD t OEH 149 78 33 48 15 Max -- -- -- -- -- 70 ns Min 175 91 39 56 18 Max -- -- -- -- -- Unit ns ns ns ns ns 14 14 14 Notes
Refresh Cycle
HB56HW465DB 60 ns Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) WE setup time (CBR refresh cycle) WE hold time (CBR refresh cycle) RAS precharge to CAS hold time Symbol Min t CSR t CHR t WRP t WRH t RPC 5 10 0 10 0 Max -- -- -- -- -- 70 ns Min 5 10 0 10 0 Max -- -- -- -- -- Unit ns ns ns ns ns Notes
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HB56HW465DB Series
EDO Page Mode Cycle
HB56HW465DB 60 ns Parameter EDO page mode cycle time EDO page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge Output data hold time from CAS low CAS hold time referred OE CAS to OE setup time Read command hold time from CAS precharge Symbol Min t HPC t RASP t CPA t CPRH t DOH t COL t COP t RCHC 25 -- -- 35 3 10 10 35 10 10 Max -- 70 ns Min 30 Max -- Unit ns Notes 20 16 9, 17
100000 -- 35 -- -- -- -- -- -- -- -- 40 3 13 10 40 10 10
100000 ns 40 -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns
9, 17
Write pulse width during CAS precharge t WPE OE precharge time t OEP
EDO Page Mode Read-Modify-Write Cycle
HB56HW465DB 60 ns Parameter EDO page mode read- modify-write cycle time WE delay time from CAS precharge Symbol Min t HPRWC t CPW 68 54 Max -- -- 70 ns Min 79 62 Max -- -- Unit ns ns 14 Notes
Refresh
Parameter Refresh period Refresh period (L-version) Symbol t REF t REF Max 64 128 Unit ms ms Notes 4096 cycles 4096 cycles
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HB56HW465DB Series
Self Refresh Mode (L-version)
HB56HW465DB 60 ns Parameter RAS pulse width (self refresh) RAS precharge time (self refresh) CAS hold time (self refresh) Symbol Min t RASS t RPS t CHS 100 110 -50 Max -- -- -- 70 ns Min 100 130 -50 Max -- -- -- Unit s ns ns Notes 22 22
Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that t RCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max). 11. Assumes that t RAD tRAD (max) and tRCD + tCAC (max) tRAD + tAA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max), tOEZ (max), tWEZ (max) and tOFR (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD tRWD (min), tCWD tCWD (min), and tAWD tAWD (min), or tCWD tCWD (min), tAWD tAWD (min) and tCPW t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referred to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. t RASP defines RAS pulse width in EDO page mode cycles. 17. Access time is determined by the longest among t AA , t CAC and t CPA. 18. All the V CC and VSS pins shall be supplied with the same voltages. 19. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device.
16
HB56HW465DB Series
20. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + tCP + 2 tT) becomes greater than the specified t HPC (min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). Output is disable after both RAS and CAS go to high. 21. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large V CC/V SS line noise, which causes to degrade V IH min/VIL max level. 22. Please do not use tRASS timing, 10 s tRASS 100 s. During this period, the device is in transition state from normal operation mode to self refresh mode. If t RASS 100 s, then RAS precharge time should use tRPS instead of tRP. 23. CBR burst refresh or 4096 cycles of distributed CBR refresh with 15.6 s interval should be executed within 64 ms immediately after exiting from and before entering into the self refresh mode. 24. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 25. XXX: H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL.
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HB56HW465DB Series
Notes concerning 2CAS control
Please do not separate the 2CASs (CAS0 and CAS1 (or CAS2, CAS4, CAS6 and CAS3, CAS5, CAS7)) operation timing intentionally. However skew between 2CASs are allowed under the following conditions. 1. Each of the 2CASs should satisfy the timing specifications individually. 2. Different operation mode for upper/lower byte is not allowed: such as following.
RAS CAS0 (CAS2, CAS4, CAS6) CAS1 (CAS3, CAS5, CAS7) Early write Delayed write
WE
3. Closely separated upper/lower byte control is not allowed. However when the condition (tCP tUL) is satisfied, EDO page mode can be performed.
RAS
CAS0 (CAS2, CAS4, CAS6) CAS1 (CAS3, CAS5, CAS7) t UL
4. Byte control operation by remaining CAS0 (CAS2, CAS4, CAS6) or CAS1 (CAS3, CAS5, CAS7) high is guaranteed.
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HB56HW465DB Series
Timing Waveforms*25
Read Cycle
t RC t RAS t RP
RAS t CSH t RCD tT t RSH t CAS t CRP
CAS
t RAD t ASR t ASC t RAL t CAL t CAH
t RAH
Address
Row
Column t RRH t RCHR t RCS t RCH
WE t WED t DZC t CDD t RDD Din High-Z
t DZO
t OEA
t OED
OE t OEZ t OHO t OFF t OH t OFR t OHR t WEZ Dout Dout
t CAC t AA t RAC t CLZ
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HB56HW465DB Series
Early Write Cycle
t RC t RAS t RP
RAS t CSH t RCD tT CAS t RSH t CAS t CRP
t ASR
t RAH
t ASC
t CAH
Address
Row
Column
t WCS
t WCH
WE
t DS
t DH
Din
Din
Dout
High-Z*
* t WCS
t WCS (min)
20
HB56HW465DB Series
Delayed Write Cycle*19
t RC t RAS
t RP
RAS t CSH t RCD tT CAS t ASR t RAH t ASC t CAH t RSH t CAS t CRP
Address
Row
Column t CWL t RCS t RWL t WP
WE
t DZC
t DS
t DH
Din
High-Z
Din t OEH t OED t OEP
t DZO

OE t OEZ t CLZ Dout High-Z Invalid Dout
21
HB56HW465DB Series
Read-Modify-Write Cycle*19
t RWC t RAS
t RP
RAS tT t RCD t CAS t CRP
CAS t RAD t ASR t RAH t ASC t CAH
Address
Row t RCS
Column t CWD t AWD t RWD tCWL t RWL t WP
WE t DZC t DS Din
High-Z Din
t DH
t DZO
t OED t OEA
t OEH t OEP
OE t CAC t AA t RAC t OEZ t OHO
High-Z
Dout t CLZ
Dout
22
HB56HW465DB Series
RAS-Only Refresh Cycle
t RC t RAS RAS tT t CRP CAS t RPC t CRP t RP
t ASR Address t OFR t OFF Dout Row
t RAH
High-Z
23
HB56HW465DB Series
CAS-Before-RAS Refresh Cycle
t RC t RP t RAS t RP t RAS t RC t RP
RAS tT t RPC t CP CAS t WRP t WRH t WRP t WRH t CSR t CHR t RPC t CP t CRP t CSR t CHR
WE
Address t OFR t OFF Dout High-Z
24
HB56HW465DB Series
Hidden Refresh
t RC t RAS t RC t RAS t RC t RP t RAS t RP
t RP
RAS tT t RSH t RCD t CHR t CRP
CAS
t RAD t ASR t RAH Address Row t ASC t RAL t CAH
Column
t RCS WE
t RRH t RCH
t DZC High-Z Din
t WED t CDD t RDD
t DZO t OEA OE t CAC t AA t RAC t CLZ Dout Dout t OFR t OHR
t OED
t OFF t OH
t OEZ t WEZ t OHO
25
HB56HW465DB Series
EDO Page Mode Read Cycle
t RP
RAS
t RASP tT t CSH t CAS t RCS t RCHR t RCH t RCS t CP t HPC t CAS t CP t HPC tCAS t RCHC
t HPC t CPRH t CP t t CRP
RSH
CAS
tCAS t RRH t RCH
WE
tASR
Address
tRAH tASC Row
tCAH
t WPE t ASC t CAH Column 2 t CAL
t ASC t CAH Column 3 t CAL
tASC
t RAL t CAH
Column 4
t WED
Column 1 t CAL tDZC
t CAL tRDD tCDD
Din
High-Z tDZO tCOL t OEP tOEP tCOP tOED

OE
tOEA
tCPA
tCPA
tCAC tAA
tAA tCAC
tOEZ
tWEZ
tOHO
tCPA tAA tCAC
tAA
tOEZ
tOFR tOHR tOEZ
tCAC
tRAC
tOEA
tDOH
tOHO
tOEA
tOHO tOFF tOH
Dout
Dout 1
Dout 2
Dout 2
Dout 3
Dout 4
26
HB56HW465DB Series
EDO Page Mode Early Write Cycle
t RASP t RP
RAS tT t CSH t RCD t CAS CAS t CP t HPC t CAS t CP t RSH t CAS t CRP
t ASR t RAH
t ASC
t CAH
t ASC
tCAH
t ASC t CAH
Address
Row
Column 1
Column 2
Column N
t WCS
t WCH
t WCS
t WCH
t WCS
t WCH
WE
t DS
t DH
t DS
t DH
t DS
t DH
Din
Din 1
Din 2
Din N
Dout
High-Z*
* t WCS
t WCS (min)
27
HB56HW465DB Series
EDO Page Mode Delayed Write Cycle*19
t RASP t RP RAS tT t CSH t RCD
CAS
t CP t CAS t HPC t CAS
t CP t RSH t CAS
t CRP
t RAD t ASR t RAH Address Row t ASC t CAH Column 1 t CWL t RCS WE t WP t DZC t DS t DH Din t DZO t OED Din 1 t DZO t OED t WP t DZC t DS t DH Din 2 t DZO t OED t WP t DZC t DS t DH Din N t RCS t ASC t CAH Column 2 t CWL t RCS t ASC t CAH Column N t CWL t RWL

t OEP t OEP t OEP
t OEH t OEH t OEH OE t CLZ t CLZ t CLZ t OEZ t OEZ t OEZ Dout High-Z
Invalid Dout Invalid Dout Invalid Dout
28
HB56HW465DB Series
EDO Page Mode Read-Modify-Write Cycle*19
t RASP t RP RAS tT t CP t RCD
CAS
t HPRWC t CP t CAS t CAS
t RSH t CAS
t CRP
t RAD t ASR t ASC t RAH Row t CAH Column 1 t RWD t AWD t CWD WE t RCS t WP t DZC t DS t DH Din t DZO
t OED
t ASC t CAH Column 2 t CWL t RCS t CPW t AWD t CWD t RCS t CWL
t ASC t CAH Column N t CPW t AWD t CWD t RWL t CWL
Address
t WP t DZC t DS t DH Din 2 t OED
t WP t DZC t DS t DH Din N t OED
Din 1
t OEP
t OEH
t DZO
t OEP
t OEH
t DZO
t OEP
t OEH
*
OE t OHO t OHO t OHO t AA t OEA t CAC t RAC t AA t CPA t OEA t CAC t AA t CPA t OEA t CAC t CLZ t OEZ t CLZ t OEZ t CLZ t OEZ
High-Z
Dout
Dout 1
Dout 2
Dout N
29
HB56HW465DB Series
EDO Page Mode Mix Cycle (1)
t RP
RAS
t RASP t CRP tCAS tRSH t RCS tCPW tAWD t ASC tRAH Row tCAH t ASC t CAH Column 2 t CAL tASC t CAH Column 3 t CAL t DS High-Z tOED t DH Din 3 t OEP tWED tWP t RAL t CAH Column 4 t CAL tRDD tCDD t RCS t RRH t RCH
tT
CAS
t CP t CAS t CSH t RCD t WCS t WCH t CAS
t CP tCAS
t CP
WE
tASR
Address
tASC
Column 1 t CAL
t DS
Din
t DH Din 1

OE
tCPA tAA tOEA
tCPA
tCPA tAA
t OEZ
tAA
tOFR tWEZ tOEZ
tCAC
tOHO tOFF tOH
tCAC
t DOH
tCAC t OHO
tOEA
Dout
Dout 2
Dout 3
Dout 4
30
HB56HW465DB Series
EDO Page Mode Mix Cycle (2)
t RP
RAS
t RASP
tT
CAS
t CSH t CAS t RCD t RCS t RCHR
t CP t CAS
t CP tCAS
t CP tCAS t RCS tCPW tWP t RAL tASC t CAH Column 4 t CAL t DS t DH Din 3 t OEP tOED tCOP tRSH
t CRP
t RCH tWCS t WCH
t RCS
t RRH t RCH
WE
tASR
Address
tRAH Row
t ASC
tCAH
t ASC t CAH Column 2 t CAL t DS t DH Din 2 t OEP tOED tCOL
t ASC t CAH Column 3 t CAL
Column 1 t CAL
tRDD tCDD
Din
High-Z
tWED
OE
tAA tOEA tCAC tRAC t OHO
Dout
t OEA tOEZ tCPA tAA tCAC tOEZ t OHO
Dout 3
tCPA tAA tCAC tOEA
tOFR tWEZ tOEZ tOHO tOFF tOH Dout 4
Dout 1
31
HB56HW465DB Series
Self Refresh Mode Cycle*22, 23, 24
t RASS
t RP
t RPS
RAS t RPC tT t CRP t CHS
, ,
t CP t CSR CAS t WRP WE t OFR t OFF Dout 32
t WRH
, + & $
High-Z
HB56HW465DB Series
Physical Outline
HB56HW465DB Series Unit: mm/inch
67.60 2.661 24.50 0.965
,,,,,,,,,,,,,,,,,,,,,,,,, 2R0.118Min. ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,, (front) ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,
23.20 0.913 2.50 0.098 B 4.60 0.181 32.80 1.291 A
143 1
63.60 2.504 (Datum -A-)
3.80Max. 0.150Max. 2R3.00Min
,, , ,, , ,, , ,, , ,, , ,, , ,, , ,, , ,, ,
3.20Min. 0.126Min.
20.00 0.787
3.30 0.130
2- o1.80 2- o0.071 2-R2.00 2-R0.079
,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,, (back) ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,
(Datum -A-)
144 2
2.00Min. 0.079Min.
Detail A
Detail B
(DATUM -A-) 0.60 0.05 0.024 0.002 2.5 0.098 R0.75 R0.030
0.25 Max. 0.010 Max.
0.80 0.031
4.00 0.10 0.157 0.004
2.55 Min. 0.100 Min.
4.00 0.10 0.157 0.004
3.70 0.146
2.10 0.083 23.20 0.913
4.60 0.181 32.80 1.291
1.50 0.10 0.059 0.004
4.00Min. 0.157Min.
1.00 0.10 0.039 0.004
25.40 1.000 6.00 0.236
33
HB56HW465DB Series
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207
Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00
Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322
Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071
34
HB56HW465DB Series
Revision Record
Rev. 0.0 1.0 Date Contents of Modification Drawn by S. Tsukui Approved by K. Tsuneda Sep. 17, 1996 Initial issue May. 20, 1997 Addition of HB56HW465DB-6AL/7AL Series Addition of Self refresh mode (L-version) Change of Serial PD Matrix DC Characteristics I CC1 max: 760/680 mA to 720/620 mA I CC3 max: 760/680 mA to 720/620 mA I CC6 max: 600/520 mA to 560/480 mA I CC7 max: 600/520 mA to 600/540 mA Addition of I CC2 max (L-version): 0.8/0.8 mA Addition of I CC10 max: 2.6/2.6 mA Addition of I CC11 max: 2/2 mA Change I LO Test conditions: 0 V Vout < VCC + 0.3 V to 0 V Vout < VCC Addition of note 4 Timing Waveforms Addition of Self refresh cycle
35

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