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HB56A832BS/SBS Series, HB56A432BR/SBR Series
8,388,608-word x 32-bit High Density Dynamic RAM Module 4,194,304-word x 32-bit High Density Dynamic RAM Module
ADE-203-728A (Z) Rev.1.0 Feb. 20, 1997 Description
The HB56A832BS/SBS is a 8M x 32 dynamic RAM module, mounted 16 pieces of 16-Mbit DRAM (HM5117400) sealed in SOJ package. The HB56A432BR/SBR is a 4M x 32 dynamic RAM module, mounted 8 pieces of 16-Mbit DRAM (HM5117400) sealed in SOJ package. An outline of the HB56A832BS/SBS, HB56A432BR/SBR is 72-pin single in-line package. Therefore, the HB56A832BS/SBS, HB56A432BR/SBR make high density mounting possible without surface mount technology. The HB56A832BS/SBS, HB56A432BR/SBR provide common data inputs and outputs. Decoupling capacitors are mounted on the module board.
Features
* 72-pin single in-line package Outline: 107.95 mm (Length) x 25.40 mm (Height) x 9.14/5.28 mm (Thickness) Lead pitch: 1.27 mm * Single 5 V (5%) supply * High speed Access time: tRAC = 50/60/70ns (max) * Low power dissipation Active mode: 4.41/3.99/3.57 W (max) (HB56A832BS/SBS Series) 4.20/3.78/3.36 W (max) (HB56A432BR/SBR Series) Standby mode (TTL): 168 mW (max) (HB56A832BS/SBS Series) (TTL): 84 mW (max) (HB56A432BR/SBR Series) (CMOS): 12.6 mW (max) (L-version) (HB56A832BS/SBS Series) (CMOS): 6.3 mW (max) (L-version) (HB56A432BR/SBR Series) * Fast page mode capability * Refresh period 2048 refresh cycles: 32 ms 128 ms (L-version)
HB56A832BS/SBS Series, HB56A432BR/SBR Series
* 3 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh * TTL compatible
Ordering Information
Type No. HB56A832BS-5 HB56A832BS-6 HB56A832BS-7 HB56A832BS-5L HB56A832BS-6L HB56A832BS-7L HB56A432BR-5 HB56A432BR-6 HB56A432BR-7 HB56A432BR-5L HB56A432BR-6L HB56A432BR-7L HB56A832SBS-5 HB56A832SBS-6 HB56A832SBS-7 HB56A832SBS-5L HB56A832SBS-6L HB56A832SBS-7L HB56A432SBR-5 HB56A432SBR-6 HB56A432SBR-7 HB56A432SBR-5L HB56A432SBR-6L HB56A432SBR-7L Access time 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 72-pin SIP socket type Solder Package 72-pin SIP socket type Contact pad Gold
2
HB56A832BS/SBS Series, HB56A432BR/SBR Series
Pin Arrangement
1Pin
36Pin
37Pin
72Pin
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Pin name VSS DQ0 DQ16 DQ1 DQ17 DQ2 DQ18 DQ3 DQ19 VCC NC A0 A1 A2 A3 A4 A5 A6
Pin No. 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Pin name A10 DQ4 DQ20 DQ5 DQ21 DQ6 DQ22 DQ7 DQ23 A7 NC VCC A8 A9 RAS3 (NC)* RAS2 NC NC
1
Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54
Pin name NC NC VSS CAS0 CAS2 CAS3 CAS1 RAS0 RAS1 (NC)* NC WE NC DQ8 DQ24 DQ9 DQ25 DQ10 DQ26
2
Pin No. 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Pin name DQ11 DQ27 DQ12 DQ28 VCC DQ29 DQ13 DQ30 DQ14 DQ31 DQ15 NC PD1 PD2 PD3 PD4 NC VSS
Notes: 1. RAS3: HB56A832BS/SBS, NC: HB56A432BR/SBR 2. RAS1: HB56A832BS/SBS, NC: HB56A432BR/SBR
3
HB56A832BS/SBS Series, HB56A432BR/SBR Series
Pin Description
Pin name A0 to A10 Function Address inputs: Row address: Column address: Refresh address: DQ0 to DQ31 CAS0 to CAS3 RAS0 to RAS3 WE VCC VSS PD1 to PD4 NC Data-in/Data-out Column address strobe Row address strobe Read/Write enable Power supply Ground Presence detect pin No connection A0 to A10 A0 to A10 A0 to A10
Presence Detect Pin Arrangement (HB56A832BS/SBS)
Function Pin No. 67 68 69 70 Pin name PD1 PD2 PD3 PD4 50 ns NC VSS VSS VSS 60 ns NC VSS NC NC 70 ns NC VSS VSS NC
Presence Detect Pin Arrangement (HB56A432BR/SBR)
Function Pin No. 67 68 69 70 Pin name PD1 PD2 PD3 PD4 50 ns VSS NC VSS VSS 60 ns VSS NC NC NC 70 ns VSS NC VSS NC
4
HB56A832BS/SBS Series, HB56A432BR/SBR Series
Block Diagram (HB56A832BS/SBS)
RAS0 CAS0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O I/O I/O I/O OE I/O I/O I/O I/O OE CAS RAS D0 I/O I/O I/O I/O OE I/O I/O I/O I/O OE RAS CAS D1 RAS1
CAS RAS D3
RAS CAS D2
CAS1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O I/O I/O I/O OE I/O I/O I/O I/O OE CAS RAS D4 I/O I/O I/O I/O OE I/O I/O I/O I/O OE RAS CAS D5
CAS RAS D7
RAS CAS D6
RAS2 CAS2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 I/O I/O I/O I/O OE I/O I/O I/O I/O OE CAS RAS D8 I/O I/O I/O I/O OE I/O I/O I/O I/O OE RAS CAS D9
RAS3
CAS RAS D11
RAS CAS D10
CAS3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O I/O I/O I/O OE I/O I/O I/O I/O OE CAS RAS D12 I/O I/O I/O I/O OE I/O I/O I/O I/O OE RAS CAS D13
CAS RAS D15
RAS CAS D14
A0 - A10 Note: D0 - D15 : HM5117400 WE VCC VSS
D0 - D15 D0 - D15 D0 - D15 0.22 F x 8 pcs D0 - D15
5
HB56A832BS/SBS Series, HB56A432BR/SBR Series
Block Diagram (HB56A432BR/SBR)
RAS0 CAS0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O I/O I/O I/O OE I/O I/O I/O I/O OE CAS RAS D0
CAS RAS D2
CAS1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O I/O I/O I/O OE I/O I/O I/O I/O OE CAS RAS D4
CAS RAS D6
RAS2 CAS2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 I/O I/O I/O I/O OE I/O I/O I/O I/O OE CAS RAS D1
CAS RAS D3
CAS3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O I/O I/O I/O OE I/O I/O I/O I/O OE CAS RAS D5
CAS RAS D7
A0 - A10 Note: D0 - D7 : HM5117400 WE VCC VSS
D0 - D7 D0 - D7 D0 - D7 0.22 F x 8 pcs D0 - D7
6
HB56A832BS/SBS Series, HB56A432BR/SBR Series
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout Pt Topr Tstg Value -1.0 to +7.0 -1.0 to +7.0 50 8 0 to +70 -55 to +125 Unit V V mA W C C
Recommended DC Operating Conditions (Ta = 0 to 70C)
Parameter Supply voltage Symbol VSS VCC Input high voltage Input low voltage Note: 1. All voltage referred to VSS . VIH VIL Min 0 4.75 2.4 -1.0 Typ 0 5.0 -- -- Max 0 5.25 5.5 0.8 Unit V V V V 1 1 1 Note
7
HB56A832BS/SBS Series, HB56A432BR/SBR Series
DC Characteristics (Ta = 0 to 70C, VCC = 5 V 5%, VSS = 0 V) (HB56A832BS/SBS)
50 ns Parameter Operating current Standby current 60 ns 70 ns Test conditions t RC = min TTL interface, RAS, CAS = VIH, Dout = High-Z CMOS interface, RAS, CAS VC C - 0. 2 V, Dout = High-Z CMOS interface, RAS, CAS VC C - 0. 2 V, Dout = High-Z t RC = min RAS = VIH, CAS = VIL, Dout = enable t RC = min t PC = min CMOS interface, Dout = High-Z, CBR refresh: t RC = 62.5 s, t RAS 0.3 s 0 V Vin 5.5 V 0 V Vout 5.5 V, Dout = disable High Iout = -5 mA Low Iout = 4.2 mA 1, 3 2 1 Notes 1, 2 Symbol Min Max Min Max Min Max Unit I CC1 I CC2 -- -- 840 -- 32 -- 760 -- 32 -- 680 mA 32 mA
--
16
--
16
--
16
mA
Standby current (L-version) RAS-only refresh current Standby current CAS-before-RAS refresh current Fast page mode current
I CC2
--
2.4
--
2.4
--
2.4
mA
I CC3 I CC5 I CC6 I CC7
-- -- -- -- --
840 -- 80 --
760 -- 80 --
680 mA 80 mA
840 -- 760 -- 5.6 --
760 -- 680 -- 5.6 --
680 mA 600 mA 5.6 mA
Battery backup current I CC10 (Standby with CBR refresh) (L-version)
Input leakage current
I LI
-10 10 -10 10 2.4 0 VCC 0.4
-10 10 -10 10 2.4 0 VCC 0.4
-10 10 -10 10 2.4 0 VCC 0.4
A A V V
Output leakage current I LO Output high voltage Output low voltage VOH VOL
Notes: 1. I CC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH.
8
HB56A832BS/SBS Series, HB56A432BR/SBR Series
DC Characteristics (Ta = 0 to 70C, VCC = 5 V 5%, VSS = 0 V) (HB56A432BR/SBR)
50 ns Parameter Operating current Standby current 60 ns 70 ns Test conditions t RC = min TTL interface, RAS, CAS = VIH, Dout = High-Z CMOS interface, RAS, CAS VCC - 0.2 V, Dout = High-Z CMOS interface, RAS, CAS VCC - 0.2 V, Dout = High-Z t RC = min RAS = VIH, CAS = VIL, Dout = enable t RC = min t PC = min CMOS interface, Dout = High-Z, CBR refresh: t RC = 62.5 s, t RAS 0.3 s 0 V Vin 5.5 V 0 V Vout 5.5 V, Dout = disable High Iout = -5 mA Low Iout = 4.2 mA 1, 3 2 1 Notes 1, 2 Symbol Min Max Min Max Min Max Unit I CC1 I CC2 -- -- 800 -- 16 -- 720 -- 16 -- 640 mA 16 mA
--
8
--
8
--
8
mA
Standby current (L-version)
I CC2
--
1.2
--
1.2
--
1.2
mA
RAS-only refresh current Standby current CAS-before-RAS refresh current Fast page mode current
I CC3 I CC5 I CC6 I CC7
-- -- -- -- --
800 -- 40 --
720 -- 40 --
640 mA 40 mA
800 -- 720 -- 2.8 --
720 -- 640 -- 2.8 --
640 mA 560 mA 2.8 mA
Battery backup current I CC10 (Standby with CBR refresh) (L-version)
Input leakage current
I LI
-10 10 -10 10 2.4 0 VCC 0.4
-10 10 -10 10 2.4 0 VCC 0.4
-10 10 -10 10 2.4 0 VCC 0.4
A A V V
Output leakage current I LO Output high voltage Output low voltage VOH VOL
Notes: 1. I CC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH.
9
HB56A832BS/SBS Series, HB56A432BR/SBR Series
Capacitance (Ta = 25C, VCC = 5 V 5%) (HB56A832BS/SBS)
Parameter Input capacitance (Address) Input capacitance (WE) Input capacitance (RAS) Input capacitance (CAS) I/O capacitance (DQ) Symbol CI1 CI2 CI3 CI4 CI/O Typ -- -- -- -- -- Max 121 137 48 48 29 Unit pF pF pF pF pF Notes 1 1 1 1 1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout.
Capacitance (Ta = 25C, VCC = 5 V 5%) (HB56A432BR/SBR)
Parameter Input capacitance (Address) Input capacitance (WE) Input capacitance (RAS) Input capacitance (CAS) I/O capacitance (DQ) Symbol CI1 CI2 CI3 CI4 CI/O Typ -- -- -- -- -- Max 68 76 43 29 17 Unit pF pF pF pF pF Notes 1 1 1 1 1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout.
10
HB56A832BS/SBS Series, HB56A432BR/SBR Series
AC Characteristics (Ta = 0 to 70C, VCC = 5 V 5%, VSS = 0 V) *1, *2, *17
Test Conditions * * * * Input rise and fall times: 5 ns Input timing reference levels: 0.8 V, 2.4 V Output timing reference levels: 0.4 V, 2.4 V Output load: 2 TTL gate + C L (100 pF) (Including scope and jig)
Read, Write, and Refresh Cycles (Common parameters)
50 ns Parameter Random read or write cycle time RAS precharge time CAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS delay time from Din Symbol Min t RC t RP t CP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH 90 30 7 50 13 0 7 0 7 17 12 13 50 5 0 3 -- -- Max -- -- -- 60 ns Min 110 40 10 Max -- -- -- 70 ns Min 130 50 10 Max -- -- -- Unit ns ns ns Notes
10000 60 10000 15 -- -- -- -- 37 25 -- -- -- -- 50 32 128 0 10 0 10 20 15 15 60 5 0 3 -- --
10000 70 10000 18 -- -- -- -- 45 30 -- -- -- -- 50 32 128 0 10 0 15 20 15 18 70 5 0 3 -- --
10000 ns 10000 ns -- -- -- -- 52 35 -- -- -- -- 50 32 128 ns ns ns ns ns ns ns ns ns ns ns ms ms 5 3 4
CAS to RAS precharge time t CRP t DZC
Transition time (rise and fall) t T Refresh period (2,048 cycles) Refresh period (2,048 cycles) (L-version) t REF t REF
11
HB56A832BS/SBS Series, HB56A432BR/SBR Series
Read Cycle
50 ns Parameter Access time from RAS Access time from CAS Access time from address Read command setup time Symbol Min t RAC t CAC t AA t RCS -- -- -- 0 0 5 25 25 0 3 -- 13 Max 50 13 25 -- -- -- -- -- -- -- 13 -- 60 ns Min -- -- -- 0 0 5 30 30 0 3 -- 15 Max 60 15 30 -- -- -- -- -- -- -- 15 -- 70 ns Min -- -- -- 0 0 5 35 35 0 3 -- 18 Max 70 18 35 -- -- -- -- -- -- -- 15 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns 11 10 10 Notes 6, 7 7, 8, 15 7, 9, 15
Read command hold time to t RCH CAS Read command hold time to t RRH RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time Output buffer turn-off time CAS to Din delay time t RAL t CAL t CLZ t OH t OFF t CDD
Write Cycle
50 ns Parameter Write command setup time Write command hold time Write command pulse width Data-in setup time Data-in hold time Symbol Min t WCS t WCH t WP t DS t DH 0 7 7 0 7 Max -- -- -- -- -- 60 ns Min 0 10 10 0 10 Max -- -- -- -- -- 70 ns Min 0 15 10 0 15 Max -- -- -- -- -- Unit ns ns ns ns ns 13 13 Notes 12
12
HB56A832BS/SBS Series, HB56A432BR/SBR Series
Refresh Cycle
50 ns Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) WE setup time (CBR refresh cycle) WE hold time (CBR refresh cycle) Symbol Min t CSR t CHR t WRP t WRH 5 7 0 7 5 Max -- -- -- -- -- 60 ns Min 5 10 0 10 5 Max -- -- -- -- -- 70 ns Min 5 10 0 10 5 Max -- -- -- -- -- Unit ns ns ns ns ns Notes
RAS precharge to CAS hold t RPC time
Fast Page Mode Cycle
50 ns Parameter Fast page mode cycle time Symbol Min t PC 35 -- -- 30 Max -- 60 ns Min 40 Max -- 70 ns Min 45 Max -- Unit ns 14 7, 15 Notes
Fast page mode RAS pulse t RASP width Access time from CAS precharge RAS hold time from CAS precharge t CPA t CPRH
100000 -- 30 -- -- 35
100000 -- 35 -- -- 40
100000 ns 40 -- ns ns
13
HB56A832BS/SBS Series, HB56A432BR/SBR Series
Notes: 1. AC measurements assume t T = 5 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh cycle or CAS-before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 6. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 7. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 8. Assumes that t RCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max). 9. Assumes that t RAD tRAD (max) and tRCD + tCAC (max) tRAD + tAA (max). 10. Either t RCH or tRRH must be satisfied for a read cycles. 11. t OFF (max) defines the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 12. Early write cycle only (tWCS tWCS (min)). 13. These parameters are referred to CAS leading edge in early write cycles. 14. t RASP defines RAS pulse width in Fast page mode cycles. 15. Access time is determined by the longest among t AA , t CAC and t CPA. 16. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large V CC / VSS line noise, which causes to degrade V IH min./ V IL max level. 17. All the V CC and VSS pins shall be supplied with the same voltages. 18. XXX: H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL.
14
HB56A832BS/SBS Series, HB56A432BR/SBR Series
Timing Waveforms*18
Read Cycle
t RC t RAS t RP
RAS t CSH t RCD tT t RSH t CAS t CRP
CAS
t RAD t ASR t ASC t RAL t CAL t CAH
t RAH
Address
Row
Column t RRH t RCS t RCH
WE
t DZC t CDD Din High-Z t CAC t AA t RAC t OFF t CLZ t OH Dout Dout
15
HB56A832BS/SBS Series, HB56A432BR/SBR Series
Early Write Cycle
t RC t RAS t RP
RAS t CSH t RCD tT CAS t RSH t CAS t CRP
t ASR
t RAH
t ASC
t CAH
Address
Row
Column t WP t WCS t WCH
WE
t DS
t DH
Din
Din
Dout
High-Z* * t WCS t WCS (min)
16
HB56A832BS/SBS Series, HB56A432BR/SBR Series
RAS-Only Refresh Cycle
t RC t RAS t RP
RAS tT t CRP CAS t RPC t CRP
t ASR t RAH Address Row t OFF Dout High-Z 17
HB56A832BS/SBS Series, HB56A432BR/SBR Series
CAS-Before-RAS Refresh Cycle
t RC t RP RAS t RPC CAS t CSR tT t CHR t RPC t CRP t RAS t RP
,
t CP t WRP t WRH t CP WE Address t OFF Dout High-Z 18
HB56A832BS/SBS Series, HB56A432BR/SBR Series
Hidden Refresh Cycle
t RC t RAS t RC t RAS t RC t RP t RAS t RP
t RP
RAS tT t RSH t RCD CAS t RAD t ASR t RAH Address Row t ASC t RAL t CAH t CHR t CRP
Column t WRP t RCS t RRH t WRH

WE t DZC High-Z Din t CAC t AA t RAC t CLZ Dout Dout
t WRP
t WRH
t CDD
t OFF t OH
19
HB56A832BS/SBS Series, HB56A432BR/SBR Series
Fast Page Mode Read Cycle
t RASP t CPRH t RP
RAS tT t CSH t RCD CAS t RAL t RAD t ASR t RAH Address Row t CAL t ASC t CAH Column 1 t CAL t ASC t CAH Column 2 t CAL t ASC t CAH Column N t CAS t CP t PC t CAS t CP t RSH t CAS t CRP
,
$ *
t RCS t RCS t RRH t RCS t RCH t RCH t RCH WE t DZC t DZC t DZC t CDD t CDD t CDD Din High-Z High-Z High-Z t RAC t AA t OH t CPA t AA t OH t CPA t AA t OH t CAC t CLZ t OFF t CAC t CLZ t OFF t CAC t CLZ t OFF Dout Dout 1 Dout 2 Dout N 20
HB56A832BS/SBS Series, HB56A432BR/SBR Series
Fast Page Mode Early Write Cycle
t RASP t RP
RAS tT t CSH t RCD t CAS CAS t PC t CP t CAS t CP t RSH t CAS t CRP
t ASR t RAH
t ASC t CAH
t ASC t CAH
t ASC t CAH
Address
Row
Column 1 t WP t WCS t WCH
Column 2 t WP t WCS t WCH
Column N t WP t WCS t WCH
WE
t DS
t DH
t DS
t DH
t DS
t DH
Din
Din 1
Din 2
Din N
Dout
High-Z* * t WCS t WCS (min)
21
HB56A832BS/SBS Series, HB56A432BR/SBR Series
Physical Outline
HB56A832BS/SBS Series
Unit: mm inch Front side 107.95 4.25 101.19 3.98 2-O 3.175 0.125 R1.57 R0.062 6.35 0.25 2.03 0.08 6.35 0.25 9.14 max 0.36
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (Front) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
1 72 A 1.27 typ. 0.05 44.45 1.75 R1.57 R0.062 6.35 0.25 44.45 1.75
,,,, ,,,, ,,,, ,,,, ,,,, ,,,, ,,,, ,,
10.16 0.40 25.40 1.00
2.54 min. 0.10
+ 0.10 1.27 - 0.08 + 0.004 0.05 - 0.003
Back side 1
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (Back) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Detail A
2.54 min 0.10 1.04 0.03 0.041 0.001
0.25 max 0.01
22
3.17 min 0.125
5.72 min 0.225
72
HB56A832BS/SBS Series, HB56A432BR/SBR Series
HB56A432SBR/SBR Series
Unit: mm inch Front side 107.95 4.25 101.19 3.98 2-O 3.175 0.125 R1.57 R0.062 6.35 0.25 2.03 0.08 6.35 0.25 5.28 max 0.208
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
1 72 A 1.27 typ. 0.05 44.45 1.75 R1.57 R0.062 72 1 6.35 0.25 44.45 1.75
2.54 min. 0.10
10.16 0.40 25.40 1.00
,, ,, ,, ,, ,, ,, ,,
+ 0.10 1.27 - 0.08 + 0.004 0.05 - 0.003
Back side
Detail A
2.54 min 0.10 1.04 0.03 0.041 0.001
0.25 max 0.01
3.17 min 0.125
23
HB56A832BS/SBS Series, HB56A432BR/SBR Series
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
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HB56A832BS/SBS Series, HB56A432BR/SBR Series
Revision Record
Rev. 1.0 Date Feb. 20, 1997 Contents of Modification Initial issue Drawn by Approved by
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