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HB56A472E-5/6/7
4,194,304-word x 72-bit High Density Dynamic RAM Module
ADE-203-744A (Z) Rev. 1.0 Feb. 20, 1997 Description
The HB56A472E belongs to 8 Byte DIMM (Dual In-line Memory Module) family, and has been developed as an optimized main memory solution for 4 and 8 Byte processor applications. The HB56A472E is a 4M x 72 dynamic RAM module, mounted 18 pieces of 16-Mbit DRAM (HM5116400) sealed in TSOP package and 2 piece of 16-bit BiCMOS line driver (74ABT16244) sealed in TSSOP package. An outline of the HB56A472E is 168-pin socket type package (dual lead out). Therefore, the HB56A472E makes high density mounting possible without surface mount technology. The HB56A472E provides common data inputs and outputs. Decoupling capacitors are mounted on the module board.
Features
* 168-pin socket type package (Dual lead out) Outline: 133.35 mm (Length) x 25.40 mm (Height) x 4.00 mm (Thickness) Lead pitch: 1.27 mm * Single 5 V (5%) supply * High speed Access time: tRAC = 50/60/70 ns (max) tCAC = 18/20/23 ns (max) * Low power dissipation Active mode: 8.84/7.90/6.95 W (max) Standby mode (TTL): 525 mW (max) (CMOS): 431 mW (max) * Buffered input except RAS and DQ * 4 byte interleave enabled, dual address input (A0/B0) * JEDEC standard outline buffered 8-byte DIMM * Fast page mode capability * 4,096 refresh cycles: 64 ms * 2 variations of refresh RAS-only refresh CAS-before-RAS refresh * TTL compatible
HB56A472E-5/6/7
Ordering Information
Type No. HB56A472E-5 HB56A472E-6 HB56A472E-7 Access time 50 ns 60 ns 70 ns Package 168-pin dual lead out socket type Contact pad Gold
Pin Arrangement
Front side Back side
1 pin 10 pin 11 pin 85 pin 94 pin 95 pin
40 pin 41 pin 124 pin 125 pin
84 pin 168 pin
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HB56A472E-5/6/7
Pin Arrangement
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Pin name VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 DQ16 DQ17 VSS NC NC VCC WE0 CE0 NC RE0 OE0 VSS A0 A2 Pin No. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 Pin name VSS OE2 RE2 CE4 NC WE2 VCC NC NC DQ18 DQ19 VSS DQ20 DQ21 DQ22 DQ23 VCC DQ24 NC NC NC NC DQ25 DQ26 DQ27 VSS DQ28 DQ29 DQ30 DQ31 VCC DQ32 DQ33 DQ34 Pin No. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 Pin name VSS DQ36 DQ37 DQ38 DQ39 VCC DQ40 DQ41 DQ42 DQ43 DQ44 VSS DQ45 DQ46 DQ47 DQ48 DQ49 VCC DQ50 DQ51 DQ52 DQ53 VSS NC NC VCC NC NC NC NC NC VSS A1 A3 Pin No. 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Pin name VSS NC NC NC NC PDE VCC NC NC DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 NC NC NC NC DQ61 DQ62 DQ63 VSS DQ64 DQ65 DQ66 DQ67 VCC DQ68 DQ69 DQ70
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HB56A472E-5/6/7
Pin No. 35 36 37 38 39 40 41 42 Pin name A4 A6 A8 A10 NC VCC NC NC Pin No. 77 78 79 80 81 82 83 84 Pin name DQ35 VSS PD1 PD3 PD5 PD7 ID0 (VSS) VCC Pin No. 119 120 121 122 123 124 125 126 Pin name A5 A7 A9 A11 NC VCC NC B0 Pin No. 161 162 163 164 165 166 167 168 Pin name DQ71 VSS PD2 PD4 PD6 PD8 ID1 (VSS) VCC
Pin Description
Pin name A0 to A11, B0 Function Address input Row address Column address Refresh address DQ0 to DQ71 RE0, RE2 CE0, CE4 WE0, WE2 OE0, OE2 VCC VSS PD1 to PD8 ID0, ID1 PDE NC Data-in/data-out Row address strobe (RAS) Column address strobe (CAS) Read/Write enable Output enable Power supply Ground Presence detect ID bit Presence detect enable No connection : A0 to A11, B0 : A0 to A9, B0 : A0 to A11, B0
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HB56A472E-5/6/7
Presence Detect Pin Assignment
PDE = Low Pin name PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 Note: Pin No. 79 163 80 164 81 165 82 166 1: High level (driver output) 0: Low level (driver output) 50 ns 1 1 0 1 0 0 0 0 60 ns 1 1 0 1 0 1 1 0 70 ns 1 1 0 1 0 0 1 0 PDE = High All High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z
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HB56A472E-5/6/7
Block Diagram
RE0 OE0 WE0 CE0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O RAS WE OE D0 RE2 OE2 WE2 CE4 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ64 DQ65 DQ66 DQ67 DQ68 DQ69 DQ70 DQ71 I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O RAS WE OE D9
RAS WE OE D1
RAS WE OE D10
RAS WE OE D2
RAS WE OE D11
RAS WE OE D3
RAS WE OE D12
RAS WE OE D4
RAS WE OE D13
RAS WE OE D5
RAS WE OE D14
RAS WE OE D6
RAS WE OE D15
RAS WE OE D7
RAS WE OE D16
RAS WE OE D8
RAS WE OE D17
PD1 to PD8 A0 B0 A1 to A11 VCC VSS 0.1 F 20PCS 0.68 F 4PCS D0 to D8 D9 to D17 D0 to D17 D0 to D17, 74ABT16244 D0 to D17, 74ABT16244 VCC VCC VSS VCC VSS VCC VSS VCC VSS VSS PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8
Note : D0 to D17 : HM5116400 : 74ABT16244
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HB56A472E-5/6/7
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout Pt Topr Tstg Value -0.5 to +7.0 -0.5 to +7.0 50 19 0 to +70 -55 to +125 Unit V V mA W C C
Recommended DC Operating Conditions (Ta = 0 to 70C)
Parameter Supply voltage Symbol VSS VCC Input high voltage Input low voltage Note: 1. All voltage referred to VSS . VIH VIL Min 0 4.75 2.4 -0.5 Typ 0 5.0 -- -- Max 0 5.25 5.5 0.8 Unit V V V V 1 1 1 Note
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HB56A472E-5/6/7
DC Characteristics (Ta = 0 to 70C, VCC = 5 V 5%, VSS = 0 V)
50 ns Parameter Operating current Standby current 60 ns 70 ns Notes 1, 2 Symbol Min Max Min Max Min Max Unit Test conditions I CC1 I CC2 -- -- 1684 -- 100 -- 1504 -- 100 -- 1324 mA 100 mA t RC = min TTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z t RC = min RAS = VIH, CAS = VIL Dout = enable t RC = min t PC = min 0 V Vin 5.5 V 0 V Vout 5.5 V Dout = disable High Iout = -5 mA Low Iout = 4.2 mA 1, 3 2 1
--
82
--
82
--
82
mA
RAS-only refresh current Standby current CAS-before-RAS refresh current Fast page mode current Input leakage current
I CC3 I CC5 I CC6 I CC7 I LI
-- -- -- --
1684 -- 154 -- 1684 -- 1504 --
1504 -- 154 -- 1504 -- 1324 --
1324 mA 154 mA 1324 mA 1144 mA A A V V
-10 10 -10 10 2.4 0 VCC 0.4
-10 10 -10 10 2.4 0 VCC 0.4
-10 10 -10 10 2.4 0 VCC 0.4
Output leakage current I LO Output high voltage Output low voltage VOH VOL
Notes: 1. I CC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH.
Capacitance (Ta = 25C, VCC = 5 V 5%)
Parameter Input capacitance (Address) Input capacitance (CAS, WE, OE) Input capacitance (RAS) I/O capacitance (DQ) Symbol CI1 CI2 CI3 CI/O Typ -- -- -- -- Max 20 20 78 20 Unit pF pF pF pF Notes 1 1 1 1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout.
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HB56A472E-5/6/7
AC Characteristics (Ta = 0 to 70C, VCC = 5 V 5%, VSS = 0 V)*1, *2, *18, *19
Test Conditions * * * * Input rise and fall times: 5 ns Input timing reference levels: 0.8 V, 2.4 V Output timing reference levels: 0.4 V, 2.4 V Output load: 2 TTL gate + C L (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
50 ns Parameter Random read or write cycle time RAS precharge time CAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time OE to Din delay time OE delay time from Din CAS delay time from Din Symbol Min t RC t RP t CP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH 90 30 7 50 13 5 7 0 7 17 12 18 50 10 18 0 0 3 -- Max -- -- -- 60 ns Min 110 40 10 Max -- -- -- 70 ns Min 130 50 10 Max -- -- -- Unit ns ns ns Notes
10000 60 10000 15 -- -- -- -- 32 20 -- -- -- -- -- -- 50 64 5 10 0 10 20 15 20 60 10 20 0 0 3 --
10000 70 10000 18 -- -- -- -- 40 25 -- -- -- -- -- -- 50 64 5 10 0 15 20 15 23 70 10 23 0 0 3 --
10000 ns 10000 ns -- -- -- -- 47 30 -- -- -- -- -- -- 50 64 ns ns ns ns ns ns ns ns ns ns ns ns ns ms 5 6 6 7 3 4
CAS to RAS precharge time t CRP t OED t DZO t DZC
Transition time (rise and fall) t T Refresh period (4,096 cycles) t REF
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HB56A472E-5/6/7
Read Cycle
50 ns Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Symbol Min t RAC t CAC t AA t OEA t RCS -- -- -- -- 0 0 5 30 25 2 3 3 -- -- 18 Max 50 18 30 18 -- -- -- -- -- -- -- -- 18 18 -- 60 ns Min -- -- -- -- 0 0 5 35 30 2 3 3 -- -- 20 Max 60 20 35 20 -- -- -- -- -- -- -- -- 20 20 -- 70 ns Min -- -- -- -- 0 0 5 40 35 2 3 3 -- -- 23 Max 70 23 40 23 -- -- -- -- -- -- -- -- 20 20 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13 13 5 12 12 Notes 8, 9 9, 10, 17 9, 11, 17 9, 20
Read command hold time to t RCH CAS Read command hold time to t RRH RAS Column address to RAS lead t RAL time Column address to CAS lead t CAL time CAS to output in low-Z Output data hold time Output data hold time from OE Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time t CLZ t OH t OHO t OFF t OEZ t CDD
Write Cycle
50 ns Parameter Write command setup time Write command hold time Write command pulse width Symbol Min t WCS t WCH t WP 0 7 7 18 13 0 12 Max -- -- -- -- -- -- -- 60 ns Min 0 10 10 20 15 0 15 Max -- -- -- -- -- -- -- 70 ns Min 0 15 10 23 18 0 20 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns 15 15 Notes 14
Write command to RAS lead t RWL time Write command to CAS lead t CWL time Data-in setup time Data-in hold time t DS t DH
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HB56A472E-5/6/7
Read-Modify-Write Cycle
50 ns Parameter Symbol Min 131 73 36 48 13 Max -- -- -- -- -- 60 ns Min 155 85 40 55 15 Max -- -- -- -- -- 70 ns Min 181 98 46 63 18 Max -- -- -- -- -- Unit ns ns ns ns ns 14 14 14 Notes
Read-modify-write cycle time t RWC RAS to WE delay time CAS to WE delay time t RWD t CWD
Column address to WE delay t AWD time OE hold time from WE t OEH
Refresh Cycle
50 ns Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) WE setup time (CBR refresh cycle) WE hold time (CBR refresh cycle) Symbol Min t CSR t CHR t WRP t WRH 10 7 5 7 5 Max -- -- -- -- -- 60 ns Min 10 10 5 10 5 Max -- -- -- -- -- 70 ns Min 10 10 5 10 5 Max -- -- -- -- -- Unit ns ns ns ns ns Notes
RAS precharge to CAS hold t RPC time
Fast Page Mode Cycle
50 ns Parameter Fast page mode cycle time Symbol Min t PC 35 -- -- 35 Max -- 60 ns Min 40 Max -- 70 ns Min 45 Max -- Unit ns 16 9, 17 Notes
Fast page mode RAS pulse t RASP width Access time from CAS precharge RAS hold time from CAS precharge t CPA t CPRH
100000 -- 35 -- -- 40
100000 -- 40 -- -- 45
100000 ns 45 -- ns ns
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HB56A472E-5/6/7
Fast Page Mode Read-Modify-Write Cycle
50 ns Parameter Fast page mode readmodify-write cycle time WE delay time from CAS precharge Symbol Min t PRWC t CPW 76 53 Max -- -- 60 ns Min 85 60 Max -- -- 70 ns Min 96 68 Max -- -- Unit ns ns 14 Notes
Notes: 1. AC measurements assume t T = 5 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh cycle or CAS-before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 2TTL loads and 100 pF. 10. Assumes that t RCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max). 11. Assumes that t RAD tRAD (max) and tRCD + tCAC (max) tRAD + tAA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max) and tOEZ (max) is define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t CPW and t AWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD tRWD (min), tCWD tCWD (min), and tAWD tAWD (min) or tCWD tCWD (min), tAWD tAWD (min) and tCPW t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referred to CAS leading edge in early write cycle and to WE leading edge in delayed write or read-modify-write cycles. 16. t RASP defines RAS pulse width in fast page mode cycles. 17. Access time is determined by the longest among t AA , t CAC or tCPA. 18. In delayed write or read-modify-write cycle, OE must disable output buffer prior to applying data to the device. After RAS is reset, if tOEH tCWL, the DQ pin will remain open circuit (high impedance); if t OEH tCWL, invalid data will be out at each DQ. 19. All the V CC and VSS pins shall be supplied with the same voltages. 20. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally causes large V CC / VSS line noise, which causes to degrade V IH min / V IL max level.
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HB56A472E-5/6/7
21. XXX: H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL.
13
HB56A472E-5/6/7
Timing Waveforms*21
Read Cycle
t RC t RAS t RP
RAS t CSH t RCD tT t RSH t CAS t CRP
CAS
t RAD t ASR t ASC t RAL t CAL t CAH
t RAH
Address
Row
Column t RRH t RCS t RCH
WE
t DZC
t CDD
Din
High-Z
t DZO
t OEA
t OED
OE t OEZ t CAC t AA t RAC t CLZ Dout t OFF t OH Dout t OHO
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HB56A472E-5/6/7
Early Write Cycle
t RC t RAS t RP
RAS t CSH t RCD tT CAS t RSH t CAS t CRP
t ASR
t RAH
t ASC
t CAH
Address
Row
Column
t WCS
t WCH
WE
t DS
t DH
Din
Din
Dout
High-Z* * t WCS t WCS (min)
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HB56A472E-5/6/7
18 Delayed Write Cycle*
t RC t RAS
t RP
RAS t CSH t RCD tT CAS t ASR t RAH t ASC t CAH t RSH t CAS t CRP
Address
Row
Column t CWL t RCS t RWL t WP
WE
t DZC
t DS
t DH
Din
High-Z
Din t OEH t OED
t DZO
OE t OEZ t CLZ High-Z*
Invalid Dout
Dout
* t OEH
t CWL
16
HB56A472E-5/6/7
Read-Modify-Write Cycle*18
t RWC t RAS
t RP
RAS tT t RCD t CAS t CRP
CAS t RAD t ASR t RAH t ASC t CAH
Address
Row t RCS
Column t CWD t AWD t RWD tCWL t RWL t WP
WE t DZC t DS Din
High-Z Din
t DH
t DZO
t OED t OEA
t OEH
OE t CAC t AA t RAC t OEZ t OHO
High-Z*
Dout t CLZ
Dout
* t OEH
t CWL
17
HB56A472E-5/6/7
RAS-Only Refresh Cycle
t RC t RAS t RP
RAS tT t CRP CAS t RPC t CRP
t ASR t RAH Address Row t OFF Dout High-Z 18
HB56A472E-5/6/7
CAS-Before-RAS Refresh Cycle
t RC t RP t RAS t RP t RAS t RC t RP
RAS tT t RPC t CP t CSR t CHR t RPC t CP t CRP t CSR t CHR
CAS t WRP t WRH t WRP t WRH
WE
Address
t OFF High-Z
Dout
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HB56A472E-5/6/7
Fast Page Mode Read Cycle
t RASP t CPRH t RP
RAS tT t CSH t RCD CAS t RAL t RAD t ASR t RAH Address Row t CAL t ASC t CAH Column 1 t CAL t ASC t CAH Column 2 t CAL t ASC t CAH Column N t CAS t CP t PC t CAS t CP t RSH t CAS t CRP
t RCS t RCS WE t DZC t CDD Din t DZO High-Z t OED t DZC t CDD High-Z t DZO t OED t RCH t RCH
t RCS
t RRH t RCH
t DZC t CDD High-Z t DZO t OED
,
OE t RAC t AA t OH t CPA t AA t OH t CPA t AA t OH t OEA t OHO t OEA t OHO t OFF t OEZ t OHO t OEA t CAC t CLZ t OFF t CAC t OEZ t CLZ t CAC t CLZ t OFF t OEZ Dout Dout 1 Dout 2 Dout N 20
HB56A472E-5/6/7
Fast Page Mode Eary Write Cycle
t RASP t RP
RAS tT t CSH t RCD t CAS CAS t PC t CP t CAS t CP t RSH t CAS t CRP
t ASR t RAH
t ASC t CAH
t ASC t CAH
t ASC t CAH
Address
Row
Column 1
Column 2
Column N
t WCS
t WCH
t WCS
t WCH
t WCS
t WCH
WE
t DS
t DH
t DS
t DH
t DS
t DH
Din
Din 1
Din 2
Din N
Dout
High-Z* * t WCS t WCS (min)
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HB56A472E-5/6/7
Fast Page Mode Delayed Write Cycle*18
t RASP t RP RAS tT t CSH t RCD
CAS
t CP t PC t CAS t CAS
t CP t RSH t CAS
t CRP
t RAD t ASR t RAH Address Row t ASC t CAH Column 1 t CWL t RCS WE t WP t DZC t DS t DH Din t DZO t OED Din 1 t DZO t OED t WP t DZC t DS t DH Din 2 t DZO t OED t WP t DZC t DS t DH Din N t RCS t ASC t CAH Column 2 t CWL t RCS t ASC t CAH Column N t CWL t RWL

t OEH t OEH t OEH OE t CLZ t CLZ t CLZ t OEZ t OEZ t OEZ Dout High-Z*
Invalid Dout Invalid Dout Invalid Dout
* t OEH
t CWL
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HB56A472E-5/6/7
Fast Page Mode Read-Modify-Write Cycle*18
t RASP t RP RAS tT t CP t RCD
CAS
t PRWC t CP t CAS t CAS
t RSH t CAS
t CRP
t RAD t ASR t ASC t RAH Row t CAH Column 1 t RWD t AWD t CWD WE t RCS t WP t DZC t DS t DH Din t DZO t OED t OEH OE Din 1 t DZO t OED t OEH t WP t DZC t DS t DH Din 2 t DZO t OED t OEH t WP t DZC t DS t DH Din N t RCS t CWL t ASC t CAH Column 2 t CPW t AWD t CWD t CWL t RCS t ASC t CAH Column N t CPW t AWD t CWD t RWL t CWL
Address
*
t OHO t OHO t OHO t AA t OEA t CAC t RAC t AA t CPA t OEA t CAC t AA t CPA t OEA t CAC t CLZ t OEZ t CLZ t OEZ t CLZ t OEZ
High-Z*
Dout
Dout 1
Dout 2
Dout N
* t OEH
t CWL
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HB56A472E-5/6/7
Physical Outline
Unit: mm/inch
Front side 133.35 5.250 3.00 0.118 127.35 5.014 4.00 max 0.157 max
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (Front) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 1 84 ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
C B 36.83 1.450 54.61 2.150 A 11.43 0.450
,, , ,, , ,, , ,, , ,, , ,, , ,, , ,, , ,, ,
3.00 0.118
8.89 0.350
1.27 0.10 0.050 0.004
Back side 2 - 3.00 2 - 0.118
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (Back) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
168 85
4.00 0.157
17.78 0.700
Detail A
Detail B 1.27 0.050 1.00 0.039
Detail C 3.175 0.125 6.35 0.250 2.00 0.10 0.079 0.004
2.54 min 0.100 min
0.25 max 0.010 max
1.00 0.05 0.039 0.002
24
3.125 0.125 0.123 0.005
3.125 0.125 0.123 0.005
6.35 0.250 3.175 0.125 2.00 0.10 0.079 0.004
25.40 1.000
4.00 min 0.157 min
HB56A472E-5/6/7
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Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207
Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00
Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322
Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071
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HB56A472E-5/6/7
Revision Record
Rev. Date 1.0 Feb. 20, 1997 Contents of Modification Initial issue Drawn by Approved by
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