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HB56A172E Series
1,048,576-word x 72-bit High Density Dynamic RAM Module
Description
The HB56A172E belongs to 8 Byte DIMM (Dual In-line Memory Module) family, and has been developed as an optimized main memory solution for 4 and 8 Byte processor applications. The HB56A172E is a 1 M x 72 ECC mode dynamic RAM module, mounted 18 pieces of 4 Mbit DRAM(HM514400CTT) sealed in TSOP package and 2 pieces of 16 bit BiCMOS line driver (74ABT16244) sealed in TSSOP package. An outline of the HB56A172E is 168-pin socket type package (dual lead out). Therefore, the HB56A172E makes high density mounting possible without surface mount technology. The HB56A172E provides common data inputs and outputs. Decoupling capacitors are mounted beside the each TSOP on the module board.
Features
* 168-pin socket type package (Dual lead out) Lead pitch: 1.27 mm * Single 5 V ( 5%) supply * High speed Access time: tRAC = 60/70/80 ns (max) tCAC = 20/25/25 ns (max) * Low power dissipation Active mode: 10.73/9.79/8.84 W (max) Standby mode: 525 mW (max) * Buffered inputs except RAS and DQ * 4 Byte interleave enabled, Dual Address inputs (A0/B0) * Fast page mode capability * 1,024 refresh cycle : 16 ms * 2 variations of refresh RAS-only refresh CAS-before-RAS refresh * TTL compatible
HB56A172E Series
Ordering Information
Type No. HB56A172E-6C HB56A172E-7C HB56A172E-8C Access time 60 ns 70 ns 80 ns Package 168-pin dual lead out socket type Contact pad Gold
Pin Arrangement
1 pin 10 pin 11 pin
40 pin 41 pin
84 pin
85 pin 94 pin 95 pin 124 pin 125 pin
168 pin
2
HB56A172E Series
Pin Assignment
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Pin name VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 DQ16 DQ17 VSS NC NC VCC Pin No. 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Pin name WE0 CE0 NC RE0 OE0 VSS A0 A2 A4 A6 A8 NC NC VCC NC NC VSS OE2 RE2 CE4 NC WE2 VCC NC NC DQ18 Pin No. 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 Pin name DQ19 VSS DQ20 DQ21 DQ22 DQ23 VCC DQ24 NC NC NC NC DQ25 DQ26 DQ27 VSS DQ28 DQ29 DQ30 DQ31 VCC DQ32 DQ33 DQ34 DQ35 VSS Pin No. 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 Pin name PD1 PD3 PD5 PD7 ID0 (VSS) VCC VSS DQ36 DQ37 DQ38 DQ39 VCC DQ40 DQ41 DQ42 DQ43 DQ44 VSS DQ45 DQ46 DQ47 DQ48 DQ49 VCC DQ50 DQ51
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HB56A172E Series
Pin Assignment (cont)
Pin No. 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 Pin name DQ52 DQ53 VSS NC NC VCC NC NC NC NC NC VSS A1 A3 A5 A7 A9 Pin No. 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 Pin name NC NC VCC NC B0 VSS NC NC NC NC PDE VCC NC NC DQ54 DQ55 VSS Pin No. 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 Pin name DQ56 DQ57 DQ58 DQ59 VCC DQ60 NC NC NC NC DQ61 DQ62 DQ63 VSS DQ64 DQ65 DQ66 Pin No. 156 157 158 159 160D 161 162 163 164 165 166 167 168 Pin name DQ67 VCC DQ68 DQ69 DQ70 DQ71 VSS PD2 PD4 PD6 PD8 ID1 (VSS) VCC
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HB56A172E Series
Pin Description
Pin name A0 - A9, B0 Function Address input: A0 - A9, B0 Row address: A0 - A9, B0 Column address: A0 - A9, B0 Refresh Address: A0 - A9, B0 Data-in/Data-out Row address strobe (RAS) Column address strobe (CAS) Read/write enable Output enable Power supply (+5 V) Ground Presence detect ID bit Presence detect enable No connection
DQ0 - DQ71 RE0, RE2 CE0, CE4 WE0, WE2 OE0, OE2 VCC VSS PD1 - PD8 ID0, ID1 PDE NC
Presence Detect Pin Assignment
PDE = Low Pin name PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 Note: Pin No. 79 163 80 164 81 165 82 166 1: High level (Driver output) 0: Low level (Driver output) 60 ns 0 0 1 0 0 1 1 0 70 ns 0 0 1 0 0 0 1 0 80 ns 0 0 1 0 0 1 0 0 PDE = High All High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z
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HB56A172E Series
Block Diagram
RE0 OE0 WE0 CE0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O RAS WE OE D0 RE2 OE2 WE2 CE4 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ64 DQ65 DQ66 DQ67 DQ68 DQ69 DQ70 DQ71 I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O RAS WE OE D9
RAS WE OE D1
RAS WE OE D10
RAS WE OE D2
RAS WE OE D11
RAS WE OE D3
RAS WE OE D12
RAS WE OE D4
RAS WE OE D13
RAS WE OE D5
RAS WE OE D14
RAS WE OE D6
RAS WE OE D15
RAS WE OE D7
RAS WE OE D16
RAS WE OE D8
RAS WE OE D17
PD1 to PD8 A0 B0 A1 to A9 VCC VSS 0.1 F 20 0.68 F 4 D0 to D8 D9 to D17 D0 to D17 D0 to D17, 74ABT16244 D0 to D17, 74ABT16244 Note : D0 to D17 : HM514400 : 74ABT16244 VCC or VSS PD1 to PD8
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HB56A172E Series
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS . Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout PT Topr Tstg Value -0.5 to +7.0 -0.5 to +7.0 50 19 0 to +70 -55 to +125 Unit V V mA W C C
Recommended DC Operating Conditions (Ta = 0 to +70C)
Parameter Supply voltatge Symbol VSS VCC Input high voltage Input low voltage Note: 1. All voltage referred to VSS VIH VIL Min 0 4.75 2.4 -0.5 Typ 0 5.0 -- -- Max 0 5.25 5.5 0.8 Unit V V V V 1 1 1 Note
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HB56A172E Series
DC Characteristics (Ta = 0 to +70C, VCC = 5 V 5%, VSS = 0 V)
HB56A172E 60 ns Parameter Operating current Standby current Symbol Min I CC1 I CC2 -- -- 70 ns Max Min 2044 -- 100 -- 80 ns Max Min 1864 -- 100 -- Max Unit Test conditions 1684 mA 100 mA t RC = min TTL interface RAS, CAS = VIH, Dout = High-Z CMOS interface RAS, CAS V CC-0.2 V Dout = High-Z t RC = min RAS = VIH CAS = VIL Dout = enable t RC = min t PC = min 0 V Vin 5.5 V 0 V Vout 5.5 V Dout = disable High Iout = -5.0 mA Low Iout = 4.2 mA 1, 3 2 1 Notes 1, 2
--
82
--
82
--
82
mA
RAS-only refresh current Standby current CAS-before-RAS refresh current
I CC3 I CC5 I CC6
-- -- -- --
2044 -- 154 --
1864 -- 154 --
1684 mA 154 mA
2044 -- 2044 --
1864 -- 1864 -- -1.0 -10 VCC 0
1684 mA 1684 mA 1.0 10 2.4 0.4 A A V V
Fast page mode current I CC7 Input leakage current I LI
-1.0 1.0 -10 2.4 0 10 VCC 0.4
-1.0 1.0 -10 2.4 0 10 VCC 0.4
Output leakage current I LO Output high voltage Output low voltage VOH VOL
Notes: 1. I CC depends on output load condition when the device is selected ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH.
Capacitance (Ta = 25C, VCC = 5 V 5%)
Parameter Input capacitance (Address) Input capacitance (Clock) Input capacitance (RAS) I/O capacitance (DQ) Symbol CI1 CI2 CI3 CI/0 Typ -- -- -- -- Max 20 20 78 20 Unit pF pF pF pF Notes 1 1 1 1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout.
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HB56A172E Series
AC Characteristics (Ta = 0 to 70C, VCC = 5 V 5%, VSS = 0 V)*1, *14, *15
Read, Write, Read-Modity-Write and Refresh Cycles (Common parameters)
HB56A172E 60 ns Parameter Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS delay time from Din Transition time (rise and fall) Refresh period Symbol Min t RC t RP t RAS t CAS t ASR t RAH t ASC t CAH t RCD 110 40 60 15 5 10 0 15 20 15 20 60 15 20 0 0 3 -- Max -- -- 70 ns Min 130 50 Max -- -- 80 ns Min 150 60 Max -- -- Unit ns ns Notes
10000 70 10000 20 -- -- -- -- 40 25 -- -- -- -- -- -- 50 16 5 10 0 15 20 15 25 70 15 25 0 0 3 --
10000 80 10000 20 -- -- -- -- 45 30 -- -- -- -- -- -- 50 16 5 10 0 15 20 15 25 80 15 25 0 0 3 --
10000 ns 10000 ns -- -- -- -- 55 35 -- -- -- -- -- -- 50 16 ns ns ns ns ns ns ns ns ns ns ns ns ns ms 7 8 9
RAS to column address delay time t RAD t RSH t CSH t CRP t ODD t DZO t DZC tT t REF
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HB56A172E Series
Read Cycle
HB56A172E 60 ns Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Read command hold time to CAS Read command hold time to RAS Column address to RAS lead time Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time OE pulse width Symbol Min t RAC t CAC t AA t OAC t RCS t RCH t RRH t RAL t OFF1 t OFF2 t CDD t OEP -- -- -- -- 0 0 0 35 0 0 20 15 Max 60 20 35 20 -- -- -- -- 20 20 -- -- 70 ns Min -- -- -- -- 0 0 0 40 0 0 25 20 Max 70 25 40 25 -- -- -- -- 25 25 -- -- 80 ns Min -- -- -- -- 0 0 0 45 0 0 25 20 Max 80 25 45 25 -- -- -- -- 25 25 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns 6 6 Notes 2, 3 3, 4, 13 3, 5, 13 3 16 16
Write Cycle
HB56A172E 60 ns Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Symbol Min t WCS t WCH t WP t RWL t CWL t DS t DH 0 15 10 20 15 0 20 Max -- -- -- -- -- -- -- 70 ns Min 0 15 10 25 20 0 20 Max -- -- -- -- -- -- -- 80 ns Min 0 15 10 25 20 0 20 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns 11 11 Notes 10
10
HB56A172E Series
Read-Modify-Write Cycle
HB56A172E 60 ns Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE Symbol Min t RWC t RWD t CWD t AWD t OEH 150 85 35 50 15 Max -- -- -- -- -- 70 ns Min 180 100 45 60 20 Max -- -- -- -- -- 80 ns Min 200 110 45 65 20 Max -- -- -- -- -- Unit ns ns ns ns ns 10 10 10 Notes
Refresh Cycle
HB56A172E 60 ns Parameter Symbol Min 15 10 5 10 10 10 Max -- -- -- -- -- -- 70 ns Min 15 10 5 10 10 10 Max -- -- -- -- -- -- 80 ns Min 15 10 5 10 10 10 Max -- -- -- -- -- -- Unit ns ns ns ns ns ns Notes
CAS setup time (CBR refresh cycle) t CSR CAS hold time (CBR refresh cycle) t CHR WE setup time WE hold time RAS precharge to CAS hold time CAS precharge time in normal mode t WS t WH t RPC t CPN
Fast Page Mode Cycle
HB56A172E 60 ns Parameter Fast page mode cycle time CAS precharge time Fast page mode RAS pulse width Access time from CAS precharge Symbol Min t PC t CP t RASC t ACP 40 10 -- -- 40 Max -- -- 70 ns Min 45 10 Max -- -- 80 ns Min 50 10 Max -- -- Unit ns ns 12 3, 13 Notes
100000 -- 40 -- -- 45
100000 -- 45 -- -- 50
100000 ns 50 -- ns ns
RAS hold time from CAS precharge t RHCP
11
HB56A172E Series
Fast Page Mode Read-Modify-Write Cycle
HB56A172E 60 ns Parameter Fast page mode read-modify-write cycle time Symbol Min t PCM 80 55 Max -- -- 70 ns Min 95 65 Max -- -- 80 ns Min 100 70 Max -- -- Unit ns ns 10 Notes
WE delay time from CAS precharge t CPW
Notes: 1. AC measurements assume t T = 5 ns. 2. Assumes that t RCD < tRCD (max) and tRAD < tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2TTL loads and 100 pF. 4. Assumes that t RCD tRCD (max) and tRAD tRAD (max). 5. Assumes that t RCD tRCD (max) and tRAD tRAD (max). 6. t OFF (max) and tOEZ (max) is define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 10. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD tRWD (min), tCWD tCWD (min), tCPW tCPW (min) and tAWD tAWD (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. These parameters are referred to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 12. t RASP defines RAS pulse width in fast page mode cycles. 13. Access time is determined by the longer of t AA or tCAC or tCPA. 14. An initial pause of 100 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 16. Either t RCH or tRRH must be satisfied for a read cycles.
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HB56A172E Series
Timing Waveforms
Refer to the HB56G236B/SB Series.
Physical Outline
133.35 5.250 3.00 0.118 127.35 5.014 2 - R2.000 2 - R0.079 4.00 Min 0.157 Min
Unit: mm/inch
4.00 Max 0.157 Max
3.00 0.118
8.89 11.43 C 0.350 0.450 2 - 3.00 2 - 0.118
B
54.61 2.150
Detail A
2.54 Min 0.100 Min
Detail B
1.00 0.039 3.125 0.125 0.123 0.005
Detail C
0.25 Max 0.010 Max
2.540
A
1.270 0.050 36.83 1.450
4.00 0.154 17.78 0.700 25.40 1.000
1.27 0.10 0.050 0.004
3.125 0.125 0.123 0.005
6.35 0.250 2.00 0.10 0.079 0.004
6.35 0.250 2.00 0.10 0.079 0.004
1.00 0.05 0.039 0.002
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