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HB526A164DB Series
524,288-word x 64-bit x 2-bank Synchronous Dynamic RAM Module
ADE-203-606 (Z) Preliminary Rev. 0.0 Jun. 18, 1996 Description
The HB526A164DB is a 512k x 64 x 2 banks Synchronous Dynamic RAM Small Outline Dual In-line Memory Module (S.O.DIMM), mounted 4 pieces of 16-Mbit SDRAM (HM5216165TT) sealed in TSOP package and 1 piece of serial EEPROM (24C02) for Presence Detect (PD). An outline of the HB526A164DB is 144-pin Zig Zag Dual tabs socket type compact and thin package. Therefore, the HB526A164DB makes high density mounting possible without surface mount technology. The HB526A164DB provides common data inputs and outputs. Decoupling capacitors are mounted beside TSOP on the module board.
Features
* 144-pin Zig Zag Dual tabs socket type Outline: 67.60 mm (Length) x 25.40 mm (Height) x 3.80 mm (Thickness) Lead pitch : 0.80 mm * 3.3V power supply * Clock frequency : 100 MHz / 83 MHz / 66 MHz * LVTTL interface * 2 Banks can operates simultaneously and independently * Burst read/write operation and burst read/single write operation capability * Programmable burst length : 1/2/4/8/full page * Programmable burst sequence Sequential/interleave * Full page burst length capability Sequential burst Burst stop capability * Programmable CAS latency : 2/3 Preliminary:The specification of this device are subject to change without notice. Please contact your nearest Hitachi's Sales Dept. regrding specification.
HB526A164DB Series
* Byte control by DQMB * 4096 refresh cycles: 64 ms * 2 variations of refresh Auto refresh Self refresh
Ordering Information
Type No. HB526A164DB-10 HB526A164DB-12 HB526A164DB-15 Frequency 100 MHz 83 MHz 66 MHz Package Small outline DIMM (144-pin) Contact pad Gold
Pin Arrangement
Front Side
1pin 2pin
59pin 60pin
61pin 62pin
143pin 144pin
Back Side
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HB526A164DB Series
Pin Arrangement (cont.)
Front side Pin No. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 Signal name Pin No. VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 VSS DQMB0 DQMB1 VDD A0 A1 A2 VSS DQ8 DQ9 DQ10 DQ11 VDD DQ12 DQ13 DQ14 DQ15 VSS NC NC CK0 VDD RAS 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 Back side Signal name Pin No. NC VSS NC NC VDD DQ16 DQ17 DQ18 DQ19 VSS DQ20 DQ21 DQ22 DQ23 VDD A6 A8 VSS A9 A10 (AP) VDD DQMB2 DQMB3 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 Signal name Pin No. VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 VSS DQMB4 DQMB5 VDD A3 A4 A5 VSS DQ40 DQ41 DQ42 DQ43 VDD DQ44 DQ45 DQ46 DQ47 VSS NC NC CKE0 VDD CAS 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 Signal name NC VSS NC NC VDD DQ48 DQ49 DQ50 DQ51 VSS DQ52 DQ53 DQ54 DQ55 VDD A7 A11 (BS) VSS NC NC VDD DQMB6 DQMB7 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63
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HB526A164DB Series
Pin Arrangement (cont.)
Front side Pin No. 67 69 71 Signal name Pin No. WE S0 NC 139 141 143 Back side Signal name Pin No. VSS SDA VDD 68 70 72 Signal name Pin No. NC NC NC 140 142 144 Signal name VSS SCL VDD
Pin Description
Pin name A0 to A11 Function Address input Row address Column address DQ0 to DQ63 S0 RAS CAS WE DQMB0 to DQMB7 CK0 CKE0 SDA SCL VDD VSS NC Data-input/output Chip select Row address asserted bank enable Column address asserted Write enable Byte input/output mask Clock input Clock enable Data-input/output for serial PD Clock input for serial PD Power supply Ground No connection A0 to A10 A0 to A7 A11
Bank select address
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HB526A164DB Series
Serial PD Matrix
Byte No. Function described 0 1 2 3 4 5 6 7 8 9 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Notes 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 1 0 0 1 21 256byte SDRAM 11 8 1 64 0 (+) 3.3 V Number of bytes utilized by module 0 manufacturer Total number bytes in serial PD device Memory type Number of row addresses Number of column addresses Number of DIMM banks Module data width Module data width(continued Module supply voltage/interface levels System clock cycle time 10 ns 12 ns 15 ns 10 Access time from clock 8 ns 9.5 ns 12 ns 11 12 SDRAM DIMM configuration type Refresh rate/type 0 0 0 0 0 0 0 0
1 1 1 1 1 1 0 1
0 1 1 0 0 1 0 0
1 0 1 0 1 0 0 0
0 0 1 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0
CL = 3
CL = 3
None Normal (15.625 s) Self refresh
13 14 15
SDRAM module attributes SDRAM device attributes: General
0 0
0 0 0
0 0 0
0 0 0
0 1 0
0 1 0
0 1 0
0 0 1 1
SDRAM device attributes: 0 minimum clock delay, back-to-back random column addresses SDRAM device attributes: Burst lengths supported SDRAM device attributes: number of banks on SDRAM device SDRAM device attributes: CAS latency SDRAM device attributes: S0 latency SDRAM device attributes: WE latency 1 0 0 0 0
16 17 18 19 20
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
1 0 0 0 0
1 0 1 0 0
1 1 1 0 0
1 0 0 1 1
1, 2, 4, 8, full page 2 2, 3 0 0
Note: 0: Serial data, "driven Low", 1: Serial data, "driven High"
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HB526A164DB Series
Block Diagram
WE S0
WE DQMB0 DQ0 to DQ7 UDQM 8 N0, N1 I/O8 to I/O15 LDQM 8 N2, N3 I/O0 to I/O7
CS DQMB4 DQ32 to DQ39
WE LDQM 8 N4, N5 I/O0 to I/O7 UDQM 8 N6, N7 I/O8 to I/O15
CS
D0
DQMB5 DQ40 to DQ47
D2
DQMB1 DQ8 to DQ15
WE DQMB2 DQ16 to DQ23 UDQM 8 N8, N9 I/O8 to I/O15 LDQM 8 N10, N11 I/O0 to I/O7
CS DQMB6 DQ48 to DQ55
WE LDQM 8 N12, N13 I/O0 to I/O7 UDQM 8 N14, N15 I/O8 to I/O15
CS
D1
DQMB7 DQ56 to DQ63
D3
DQMB3 DQ24 to DQ31
RAS CAS A0 to A11 CKE0 R0 CK0 R1
RAS (D0 to D3) CAS (D0 to D3) A0 to A11(D0 to D3) CKE (D0 to D3) CLK (D0,D2) CLK (D1,D3) VSS VSS A0 A1 A2 SCL
Serial PD SCL SDA SDA
U0
VDD
C0-C15 C100-C107
VDD (D0 to D3, U0) VSS (D0 to D3, U0) * D0 to D3 : HM5216165TT U0 : 24C02 C0 to C7 : 0.33 F C100 to C107 : 0.1 F N0 to N15 : Network Resistors R0, R1 : Chip Resistors
Notes : 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state.
VSS
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HB526A164DB Series
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Note: Symbol VT VDD Iout PT Topr Tstg Value -1.0 to +4.6 -1.0 to +4.6 50 4 0 to +65 -55 to +125 Unit V V mA W C C Note 1 1
1. VIH (max) = 5.75 V for pulse width 5 ns.
Recommended DC Operating Conditions (Ta = 0 to +65C)
Parameter Supply voltage Symbol VDD VSS Input high voltage Input low voltage VIH VIL Min 3.0 0 2.0 -0.3 Typ 3.3 0 -- -- Max 3.6 0 4.6 0.8 Unit V V V V 1, 2 1, 3 Notes 1
Notes: 1. All voltage referred to VSS 2. VIH (max) = 5.5 V for pulse width 5 ns 3. VIL (min) = -1.0 V for pulse width 5 ns
7
HB526A164DB Series
DC Characteristics (Ta = 0 to 65C, VDD = 3.3 V 0.3 V, V SS = 0 V)
HB526A164DB -10 Parameter Operating current Standby current (Bank Disable) Symbol I CC1 I CC2 -12 -15 Notes 1, 2, 4 5 6
Min Max Min Max Min Max Unit Test conditions -- -- -- 520 -- 12 8 -- -- 420 -- 12 8 -- -- 340 mA Burst length = 1 t RC = min 12 8 mA CKE0 = VIL, t CK = min mA CKE0 = VIL CK0 = VIL or VIH Fixed
--
200 --
164 --
132 mA CKE0 = VIH, NOP command t CK = min 28 mA CKE0 = VIL, t CK = min, DQ = High-Z
3
Active standby current (Bank active)
I CC3
--
28
--
28
--
1, 2
--
204 --
172 --
136 mA CKE0 = VIH, NOP command t CK = min, DQ = High-Z 260 mA t CK = min, BL = 4 400 mA 240 mA t RC = min 8 mA VIH VDD - 0.2 VIL 0.2 V A A V V 0 Vin VDD 0 Vout VDD DQ = disable I OH = -2 mA I OL = 2 mA
1, 2, 3
Burst operating current (CAS Latency = 2) (CAS Latency = 3) Refresh current Self refresh current Input leakage current Output leakage current Output high voltage Output low voltage
I CC4 I CC4 I CC5 I CC6 I LI I LO VOH VOL
-- -- -- --
400 -- 600 -- 340 -- 8 --
340 -- 500 -- 280 -- 8 --
1, 2, 4
7
-10 10 -10 10 2.4 -- -- 0.4
-10 10 -10 10 2.4 -- -- 0.4
-10 10 -10 10 2.4 -- -- 0.4
Notes: 1. I CC depends on output load condition when the device is selected. ICC (max) is specified at the output open condition. 2. One bank operation. 3. Input signal transition is once per two CK0 cycles. 4. Input signal transition is once per one CK0 cycle. 5. After power down mode, CK0 operating current. 6. After power down mode, no CK0 operating current. 7. After self refresh mode set, self refresh current.
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HB526A164DB Series
Capacitance (Ta = 25C, VDD = 3.3 V 0.3 V)
Parameter Input capacitance (Address) Symbol CIN Max 40 40 40 25 20 Unit pF pF pF pF pF Notes 1, 3 1, 3 1, 3 1, 2, 3 1, 3
Input capacitance (RAS, CAS, WE, CK0, CKE0) CIN Input capacitance (S0) Input capacitance (DQMB0 to DQMB7) Input/Output capacitance (DQ0 to DQ63) CIN CIN CI/O
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. DQMB = VIH to disable Dout. 3. This parameter is sampled and not 100% tested.
AC Characteristics (Ta = 0 to 65C, VDD = 3.3 V 0.3 V, V SS = 0 V)
HB526A164DB -10 Parameter System clock cycle time (CAS Latency = 2) (CAS Latency = 3) CK0 high pulse width CK0 low pulse width Access time from CK0 (CAS Latency = 2) (CAS Latency = 3) Data-out hold time CK0 to Data-out low impedance CK0 to Data-out high impedance Data-in setup time Data in hold time Address setup time Address hold time CKE0 setup time CKE0 setup time for power down exit CKE0 hold time Symbol Min Max t CK t CK t CKH t CKL t AC t AC t OH t LZ t HZ t DS t DH t AS t AH t CES t CESP t CEH 15 10 3 3 -- -- 3 0 -- 2 1 2 1 2 2 1 -- -- -- -- 9.5 8 -- -- 7 -- -- -- -- -- -- -- -12 Min Max 18 12 4 4 -- -- 3 0 -- 3 1 3 1 3 3 1 -- -- -- -- 12 9.5 -- -- 9 -- -- -- -- -- -- -- -15 Min Max 22.5 -- 15 5 5 -- -- 3 0 -- 3 1 3 1 3 3 1 -- -- -- 17 12 -- -- 11 -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns 1, 2 1, 2, 3 1, 4 1 1 1 1 1, 5 1 1 ns ns ns 1 1 1, 2 Unit Notes ns 1
9
HB526A164DB Series
AC Characteristics (Ta = 0 to 65C, VDD = 3.3 V 0.3 V, V SS = 0 V) (cont)
HB526A164DB -10 Parameter Command (S0, RAS, CAS, WE, DQMB) setup time Command (S0, RAS, CAS, WE, DQMB) hold time Ref/Active to Ref/Active command period Active to precharge command period Active to precharge on full page mode Active command to column command (same bank) Precharge to active command period Symbol Min Max t CS t CH t RC t RAS t RASC t RCD t RP 2 1 90 60 -- 30 30 15 20 1 -- -- -- -- -12 Min Max 3 1 -- -- -15 Min Max 3 1 -- -- Unit Notes ns ns ns 1 1 1 1 1 1 1 1 1
108 --
135 --
120000 72 120000 -- -- -- -- -- 5 64 36 36 18 24 1 --
120000 90 120000 -- -- -- -- -- 5 64 45 45
120000 ns 120000 ns -- -- ns ns ns ns ns ms
The last data-in the precharge lead t RWL time Active (a) to Active (b) command period Transition time (rise to fall) Refresh period Notes: 1. 2. 3. 4. 5. t RRD tT t REF
22.5 -- 30 1 -- -- 5 64
AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.40 V. Access time is measured at 1.40 V. Load condition is C L = 50 pF with current source. t LZ (max) defines the time at which the outputs achieves the low impedance state. t HZ (max) defines the time at which the outputs achieves the high impedance state. t CES defines CKE0 setup time to CKE0 rising edge except power down exit command.
10
HB526A164DB Series
Test Conditions * Input and output timing reference levels: 1.4 V * Input waveform and output load: See following figures
2.8 V
input
V SS
80% 20%
I/O
50 +1.4 V CL
t
T
tT
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HB526A164DB Series
Relationship Between Frequency and Minimum Latency
HB526A164DB Parameter Frequency (MHz) tCK (ns) Active command to column command (same bank) Active command to active command (same bank) Active command to precharge command (same bank) Precharge command to active command (same bank) Last data input to precharge command (same bank) Active command to active command (different bank) Self refresh exit time Last data in to active command (Auto precharge, same bank) Self refresh exit to command input Precharge command to high impedance (CAS latency = 3) (CAS latency = 2) -10 100 66 Symbol 10 15 t RCD t RC t RAS t RP t RWL t RRD I SREX I APW I SEC 3 9 6 3 2 2 2 5 9 2 6 4 2 1 2 2 3 6 33 30 1 3 2 1 1 1 2 2 3 -12 83 12 3 9 6 3 2 2 2 5 9 55 18 2 6 4 2 1 2 2 3 6 28 36 1 3 2 1 1 1 2 2 3 -15 66 15 3 9 6 3 2 2 2 5 9 44 22 22.5 45 2 6 4 2 1 2 2 3 6 1 3 2 1 1 1 2 2 3 Notes 1 = [tRAS + tRP] 1 1 1 1 1 2 = [tRWL + t RP] = [tRC]
I HZP I HZP
3 -- 1
3 2 1
3 2 1
3 -- 1
3 2 1
3 2 1
3 -- 1
3 2 1
3 2 1
Last data out to active command I APR (auto precharge) (same bank) Last data out to precharge (early precharge) (CAS latency = 3) I EP (CAS latency = 2) Column command to column command I EP I CCD
-2 -- 1 0 0 2 1
-2 -1 1 0 0 2 1
-2 -1 1 0 0 2 1
-2 -- 1 0 0 2 1
-2 -1 1 0 0 2 1
-2 -1 1 0 0 2 1
-2 -- 1 0 0 2 1
-2 -1 1 0 0 2 1
-2 -1 1 0 0 2 1
Write command to data in latency I WCD DQMB to data in DQMB to data out CKE0 to CK0 disable I DID I DOD I CLE
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HB526A164DB Series
Relationship Between Frequency and Minimum Latency (cont)
HB526A164DB Parameter Frequency (MHz) tCK (ns) Register set to active command S0 to command disable Power down exit to command input Burst stop to output valid data hold (CAS latency = 3) (CAS latency = 2) Burst stop to output high impedance (CAS latency = 3) (CAS latency = 2) Burst stop to write data ignore -10 100 66 Symbol 10 15 t RSA I CDD I PEC 1 0 1 1 0 1 33 30 1 0 1 -12 83 12 1 0 1 55 18 1 0 1 28 36 1 0 1 -15 66 15 1 0 1 44 22 22.5 45 1 0 1 1 0 1 Notes
I BSR I BSR I BSH I BSH I BSW
2 -- 3 -- 0
2 1 3 2 0
2 1 3 2 0
2 -- 3 -- 0
2 1 3 2 0
2 1 3 2 0
2 -- 3 -- 0
2 1 3 2 0
2 1 3 2 0
Notes: 1. t RCD to tRRD are recommended value. 2. When self refresh exit is executed, CKE0 should be kept "H" longer than l SREX from exit cycle.
Refer to the HB526C264EN/HB526C464EN Series for the details.
13
HB526A164DB Series
Physical Outline
Unit: mm / inch
67.60 2.661 24.50 0.965
,,,,,,,,,,,,,,,,,,,,,,,,, 2R0.118Min. ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,, (front) ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,
23.20 0.913 2.50 0.098 B 4.60 0.181 32.80 1.291 A
143 1
63.60 2.504 (Datum -A-)
3.80Max. 0.150Max. 2R3.00Min
,, , ,, , ,, , ,, , ,, , ,, , ,, , ,, , ,, ,
3.20Min. 0.126Min.
20.00 0.787
3.30 0.130
2- o1.80 2- o0.071 2-R2.00 2-R0.079
,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,, (back) ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,
(Datum -A-)
144 2
2.00Min. 0.079Min.
Detail A
Detail B
(DATUM -A-) 0.60 0.05 0.024 0.002 2.5 0.098 R0.75 R0.030
0.25 Max. 0.010 Max.
0.80 0.031
4.00 0.10 0.157 0.004
2.55 Min. 0.100 Min.
4.00 0.10 0.157 0.004
3.70 0.146
2.10 0.083 23.20 0.913
4.60 0.181 32.80 1.291
1.50 0.10 0.059 0.004
14
4.00Min. 0.157Min.
1.00 0.10 0.039 0.004
25.40 1.000 6.00 0.236
HB526A164DB Series
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207
Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00
Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322
Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071
15
HB526A164DB Series
Revision Record
Rev. 0.0 Date Contents of Modification Drawn by Approved by Jun. 18, 1996 Initial issue
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