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HM51W17400B Series
4,194,304-word x 4-bit Dynamic Random Access Memory
ADE-203-370A (Z) Rev. 1.0 Nov. 17, 1995 Description
The Hitachi HM51W17400B is a CMOS dynamic RAM organized 4,194,304-word x 4-bit. It employs the most advanced CMOS technology for high performance and low power. The HM51W17400B offers Fast Page Mode as a high speed access mode.
Features
* Single 3.3 V (0.3 V) * High speed Access time : 60 ns/ 70 ns/ 80 ns (max) * Low power dissipation Active mode : 396 mW/360 mW/324 mW(max) Standby mode : 7.2 mW (max) : 0.36 mW (max) (L-version) * Fast page mode capability * Long refresh period 2048 refresh cycles : 32 ms : 128 ms (L-version) * 4 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh Self refresh (L-version) * Battery backup operation (L-version) * Test function 16-bit parallel test mode
This specification is fully compatible with the 16-Mbit DRAM specifications from TEXAS INSTRUMENTS.
HM51W17400B Series
Ordering Information
Type No. HM51W17400BS-6 HM51W17400BS-7 HM51W17400BS-8 HM51W17400BLS-6 HM51W17400BLS-7 HM51W17400BLS-8 HM51W17400BTS-6 HM51W17400BTS-7 HM51W17400BTS-8 HM51W17400BLTS-6 HM51W17400BLTS-7 HM51W17400BLTS-8 Access Time 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 300-mil 26-pin plastic TSOP II (TTP-26/24DA) Package 300-mil 26-pin plastic SOJ (CP-26/24DB)
Pin Arrangement
HM51W17400BS/BLS Series HM51W17400BTS/BLTS Series
VCC I/O1 I/O2 WE RAS NC
1 2 3 4 5 6
26 25 24 23 22 21
VSS I/O4 I/O3 CAS OE A9
VCC I/O1 I/O2 WE RAS NC
1 2 3 4 5 6
26 25 24 23 22 21
VSS I/O4 I/O3 CAS OE A9
A10 A0 A1 A2 A3 V
CC
8 9 10 11 12 13
19 18 17 16 15 14
A8 A7 A6 A5 A4 VSS
A10 A0 A1 A2 A3 V
CC
8 9 10 11 12 13
19 18 17 16 15 14
A8 A7 A6 A5 A4 VSS
(Top view)
(Top view)
2
HM51W17400B Series
Pin Description
Pin Name A0 to A10 A0 to A10 I/O1 to I/O4 RAS CAS WE OE VCC VSS NC Function Address input Refresh address input Data input/data output Row address strobe Column address strobe Write enable Output enable Power supply (+3.3 V) Ground No connection
3
HM51W17400B Series
Block Diagram
RAS I/O 4 I/O Buffer 4 CAS WE OE I/O 3 I/O Buffer 3
Column decoder & driver
Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus
Peripheral Circuit
Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. &
I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O
bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus
Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. &
I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O
bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus
Selector
Selector Selector Row decoder & driver
Row decoder & driver
Selector
Column decoder & driver
Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus
Selector
Selector
Row decoder & driver
I/O Buffer 2 I/O 2
Selector
I/O Buffer 1 I/O 1
Address A0 to A10
4
Selector
Row decoder & driver
HM51W17400B Series
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout PT Topr Tstg Value -0.5 to VCC + 0.5 ( 4.6 V (max)) -0.5 to +4.6 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C
Recommended DC Operating Conditions (Ta = 0 to +70C)
Parameter Supply voltage Input high voltage Input low voltage Note: 1. All voltage referred to VSS . Symbol VCC VIH VIL Min 3.0 2.0 -0.3 Typ 3.3 -- -- Max 3.6 VCC + 0.3 0.8 Unit V V V Note 1 1 1
DC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, VSS = 0 V)
HM51W17400B -6 Parameter Operating current Standby current
*1, *2
-7 Max Min 110 2 -- --
-8 Max Min 100 2 -- -- Max Unit Test Conditions 90 2 mA mA t RC = min TTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS V CC - 0.2 V Dout = High-Z CMOS interface RAS, CAS V CC - 0.2 V Dout = High-Z
Symbol Min I CC1 I CC2 -- --
--
1
--
1
--
1
mA
Standby current (L-version)
I CC2
--
100
--
100
--
100
A
5
HM51W17400B Series
DC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, VSS = 0 V) (cont)
HM51W17400B -6 Parameter RAS-only refresh current Standby current
*1 *2
-7 Max Min 110 5 110 80 300 -- -- -- -- --
-8 Max Min 100 5 100 70 300 -- -- -- -- -- Max Unit Test Conditions 90 5 90 65 300 mA mA mA mA A t RC = min RAS = VIH, CAS = VIL Dout = enable t RC = min t PC = min CMOS interface Dout = High-Z CBR refresh: tRC = 62.5 s t RAS 0.3 s CMOS interface RAS, CAS 0.2 V Dout = High-Z 0 V Vin 4.6 V 0 V Vout 4.6 V Dout = disable High Iout = -2 mA Low Iout = 2 mA
Symbol Min I CC3 I CC5 I CC6 -- -- -- -- --
CAS-before-RAS refresh current
Fast page mode current *1, *3 I CC7 Battery backup current I CC10 (Standby with CBR refresh) (L-version) Self refresh mode current (L-version) Input leakage current Output leakage current Output high voltage Output low voltage I CC11
--
200
--
200
--
200
A
I LI I LO VOH VOL
-10 -10 2.4 0
10 10 VCC 0.4
-10 -10 2.4 0
10 10 VCC 0.4
-10 -10 2.4 0
10 10 VCC 0.4
A A V V
Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH.
Capacitance (Ta = 25C, VCC = 3.3 V 0.3 V)
Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI1 CI2 CI/O Typ -- -- -- Max 5 7 7 Unit pF pF pF Notes 1 1 1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout.
6
HM51W17400B Series
AC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, VSS = 0 V) *1, *2, *18, *19
Test Conditions * * * * Input rise and fall time : 5 ns Input timing reference levels : 0.8 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V Output load : 1 TTL gate + C L (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM51W17400B -6 Parameter Random read or write cycle time RAS precharge time CAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS delay time from Din Transition time (rise and fall) Symbol Min t RC t RP t CP t RAS t CAS t ASR t RAH t ASC t CAH t RCD 110 40 10 60 15 0 10 0 10 20 15 15 60 5 15 0 0 3 Max -- -- -- -7 Min 130 50 10 Max -- -- -- -8 Min 150 60 10 Max -- -- -- Unit Notes ns ns ns
10000 70 10000 18 -- -- -- -- 45 30 -- -- -- -- -- -- 50 0 10 0 15 20 15 18 70 5 18 0 0 3
10000 80 10000 20 -- -- -- -- 52 35 -- -- -- -- -- -- 50 0 10 0 15 20 15 20 80 5 20 0 0 3
10000 ns 10000 ns -- -- -- -- 60 40 -- -- -- -- -- -- 50 ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 6 7 3 4
RAS to column address delay time t RAD t RSH t CSH t CRP t OED t DZO t DZC tT
7
HM51W17400B Series
Read Cycle
HM51W17400B -6 Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Read command hold time to CAS Read command hold time to RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time Output data hold time from OE Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time Symbol Min t RAC t CAC t AA t OEA t RCS t RCH t RRH t RAL t CAL t CLZ t OH t OHO t OFF t OEZ t CDD -- -- -- -- 0 0 0 30 30 0 3 3 -- -- 15 Max 60 15 30 15 -- -- -- -- -- -- -- -- 15 15 -- -7 Min -- -- -- -- 0 0 0 35 35 0 3 3 -- -- 18 Max 70 18 35 18 -- -- -- -- -- -- -- -- 15 15 -- -8 Min -- -- -- -- 0 0 0 40 40 0 3 3 -- -- 20 Max 80 20 40 20 -- -- -- -- -- -- -- -- 15 15 -- Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13 13 5 12 12 8, 9, 20 9, 10, 17, 20 9, 11, 17, 20 9, 20
Write Cycle
HM51W17400B -6 Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Symbol Min t WCS t WCH t WP t RWL t CWL t DS t DH 0 10 10 15 15 0 10 Max -- -- -- -- -- -- -- -7 Min 0 15 10 18 18 0 15 Max -- -- -- -- -- -- -- -8 Min 0 15 10 20 20 0 15 Max -- -- -- -- -- -- -- Unit Notes ns ns ns ns ns ns ns 15 15 14
8
HM51W17400B Series
Read-Modify-Write Cycle
HM51W17400B -6 Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE Symbol Min t RWC t RWD t CWD t AWD t OEH 155 85 40 55 15 Max -- -- -- -- -- -7 Min 181 98 46 63 18 Max -- -- -- -- -- -8 Min 205 110 50 70 20 Max -- -- -- -- -- Unit Notes ns ns ns ns ns 14 14 14
Refresh Cycle
HM51W17400B -6 Parameter Symbol Min 5 10 0 10 0 Max -- -- -- -- -- -7 Min 5 10 0 10 0 Max -- -- -- -- -- -8 Min 5 10 0 10 0 Max -- -- -- -- -- Unit Notes ns ns ns ns ns
CAS setup time (CBR refresh cycle) t CSR CAS hold time (CBR refresh cycle) t CHR WE setup time (CBR refresh cycle) t WRP WE hold time (CBR refresh cycle) RAS precharge to CAS hold time t WRH t RPC
Fast Page Mode Cycle
HM51W17400B -6 Parameter Fast page mode cycle time Fast page mode RAS pulse width Access time from CAS precharge Symbol Min t PC t RASP t CPA 40 -- -- 35 Max -- -7 Min 45 Max -- -8 Min 50 Max -- Unit Notes ns 16 9, 17, 20
100000 -- 35 -- -- 40
100000 -- 40 -- -- 45
100000 ns 45 -- ns ns
RAS hold time from CAS precharge t CPRH
9
HM51W17400B Series
Fast Page Mode Read-Modify-Write Cycle
HM51W17400B -6 Parameter Fast page mode read-modify-write cycle time Symbol Min t PRWC 85 60 Max -- -- -7 Min 96 68 Max -- -- -8 Min 105 75 Max -- -- Unit Notes ns ns 14
WE delay time from CAS precharge t CPW
Test Mode Cycle *19
HM51W17400B -6 Parameter Test mode WE setup time Test mode WE hold time Symbol Min t WTS t WTH 0 10 Max -- -- -7 Min 0 10 Max -- -- -8 Min 0 10 Max -- -- Unit Notes ns ns
Refresh
Parameter Refresh period Refresh period (L-version) Symbol t REF t REF Max 32 128 Unit ms ms Note 2048 cycles 2048 cycles
Self Refresh Mode (L-version)
HM51W17400BL -6 Parameter RAS pulse width (Self refresh) RAS precharge time (Self refresh) CAS hold time (Self refresh) Symbol Min t RASS t RPS t CHS 100 110 -50 Max -- -- -- -7 Min 100 130 -50 Max -- -- -- -8 Min 100 150 -50 Max -- -- -- Unit Notes s ns ns
Notes: 1. AC measurements assume t T = 5 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC .
10
HM51W17400B Series
4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. (V OH = 2.0 V, VOL = 0.8 V) 10. Assumes that t RCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max). 11. Assumes that t RAD tRAD (max) and tRCD + tCAC (max) tRAD + tAA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operationg parameters. They are included in the data sheet as electrical characteristics only; if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD tRWD (min), tCWD tCWD (min), and tAWD tAWD (min), or tCWD tCWD (min), tAWD tAWD (min) and tCPW tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referred to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. t RASP defines RAS pulse width in fast page mode cycles. 17. Access time is determined by the longest among t AA , t CAC and t CPA. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. After RAS is reset, if tOEH tCWL, the I/O pin will remain open circuit (high impedance); if tOEH < tCWL, invalid data will be out at each I/O. 19. The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0 and CA1 for the 4M x 4 are don't care during test mode. Test mode is set by performing WE-and-CAS-before-RAS (WCBR) cycle. In 16-bit parallel test mode, data is written into 4 bits in parallel at each I/O (I/O1 to I/O4) and read out from each I/O. If 4 bits of each I/O are equal (all 1s or 0s), data output pin is a high state during test mode read cycle, then the device has passed. If they are not equal, data output pin is a low state, then the device has failed. Refresh during test mode operation can be performed by normal read cycles or by WCBR refresh cycles. To get out of test mode and enter a normal operation mode, perform either a regular CAS-beforeRAS refresh cycle or RAS-only refresh cycle. 20. In a test mode read cycle, the value of tRAC , t AA , t CAC and t CPA is delayed by 2 ns to 5 ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 21. XXX: H or L (H: V IH (min) V IN V IH (max), L: VIL (min) V IN V IL (max)) ///////: Invalid Dout
11
HM51W17400B Series
Timing Waveforms*21
Read Cycle
t RC t RAS t RP
RAS t CSH t RCD tT t RSH t CAS t CRP
CAS t RAD t ASR t ASC t RAL t CAL t CAH
t RAH
Address
Row
Column t RRH t RCS t RCH
WE
t DZC
t CDD
Din
High-Z
t DZO
t OEA
t OED
OE t OEZ t CAC t AA t RAC t CLZ Dout t OFF t OH Dout t OHO
12
HM51W17400B Series
Early Write Cycle
t RC t RAS t RP
RAS t CSH t RCD tT t RSH t CAS t CRP
CAS
t ASR
t RAH
t ASC
t CAH
Address
Row
Column
t WCS
t WCH
WE
t DS
t DH
Din
Din
Dout
High-Z** * OE : H or L ** t WCS t WCS (min)
13
HM51W17400B Series
Delayed Write Cycle*18
t RC t RAS
t RP
RAS t CSH t RCD tT CAS t ASR t RAH t ASC t CAH t RSH t CAS t CRP
Address
Row
Column t CWL t RCS t RWL t WP
WE
t DZC
t DS
t DH
Din
High-Z
Din t OEH t OED
t DZO

OE t OEZ t CLZ Dout High-Z Invalid Dout 14
HM51W17400B Series
Read-Modify-Write Cycle*18
t RWC t RAS
t RP
RAS tT t RCD t CAS t CRP
CAS t RAD t ASR tRAH t ASC t CAH
Address
Row t RCS
Column t CWD t AWD t RWD tCWL t RWL t WP
WE t DZC t DS Din
High-Z Din
t DH
t DZO
t OED t OEA
t OEH
OE t CAC t AA t RAC t OEZ t OHO
High-Z
Dout t CLZ
Dout
15
HM51W17400B Series
RAS-Only Refresh Cycle
t RC t RAS RAS t RP
tT t CRP t RPC t CRP CAS t ASR t RAH Address Row t OFF Dout High-Z ** OE, WE: H or L
* Refresh Address A0 - A10 (RA0 - RA10)
16
HM51W17400B Series
CAS-Before-RAS Refresh Cycle
t RC t RP RAS t RPC CAS t CSR tT t CHR t RPC t CRP t RAS t RP
, + * $
t CP t WRP t WRH t CP WE Address t OFF Dout High-Z
* OE: H or L
17
HM51W17400B Series
Hidden Refresh Cycle
t RC t RAS t RC t RAS t RC t RP t RAS t RP
t RP
RAS tT t RSH t RCD CAS t RAD t ASR t RAH Address Row t ASC t RAL t CAH t CHR t CRP
Column t WRP t RCS t RRH t WRH

WE t DZC High-Z Din t DZO t OEA OE t CAC t AA t RAC t CLZ Dout Dout
t WRP
t WRH
t CDD
t OED
t OEZ t OHO
t OFF t OH
18
HM51W17400B Series
Fast Page Mode Read Cycle
t RASP t CPRH t RP
RAS tT t CSH t RCD CAS t RAL t RAD t ASR t RAH Address Row t CAL t ASC t CAH Column 1 t CAL t ASC t CAH Column 2 t CAL t ASC t CAH Column N t CAS t CP t PC t CAS t CP t RSH t CAS t CRP
t RCS tRCS WE t DZC t CDD Din t DZO High-Z t OED t DZC t CDD High-Z t DZO t OED tRCH tRCH
t RCS
t RRH t RCH
t DZC t CDD High-Z t DZO t OED
,
OE t RAC t AA t OH t CPA t AA t OH t CPA t AA t OH t OEA t OHO t OEA t OHO t OFF t OEZ t OHO t OEA t CAC t CLZ t OFF t CAC t OEZ t CLZ t CAC t CLZ t OFF t OEZ Dout Dout 1 Dout 2 Dout N 19
HM51W17400B Series
Fast Page Mode Early Write Cycle
t RASP t RP
RAS tT t CSH t RCD t CAS t PC t CP t CAS t CP t RSH t CAS t CRP
CAS
t ASR t RAH
t ASC t CAH
t ASC t CAH
t ASC t CAH
Address
Row
Column 1
Column 2
Column N
t WCS
t WCH
t WCS
t WCH
t WCS
t WCH
WE
t DS
t DH
t DS
t DH
t DS
t DH
Din
Din 1
Din 2
Din N
Dout
High-Z** * OE : H or L ** t WCS t WCS (min)
20
HM51W17400B Series
Fast Page Mode Delayed Write Cycle*18
t RASP t RP RAS tT t CSH t RCD
CAS
t CP t PC t CAS t CAS
t CP t RSH t CAS
t CRP
t RAD t ASR t RAH Address Row t ASC t CAH Column 1 t CWL t RCS WE t WP t DZC t DS t DH Din t DZO t OED Din 1 t DZO t OED t WP t DZC t DS t DH Din 2 t DZO t OED t WP t DZC t DS t DH Din N t RCS t ASC t CAH Column 2 t CWL t RCS t ASC t CAH Column N t CWL t RWL

t OEH t OEH t OEH OE t CLZ t CLZ t CLZ t OEZ t OEZ t OEZ Dout High-Z
Invalid Dout Invalid Dout Invalid Dout
21
HM51W17400B Series
Fast Page Mode Read-Modify-Write Cycle*18
t RASP t RP RAS tT t CP t RCD
CAS
t PRWC t CP t CAS t CAS
t RSH t CAS
t CRP
t RAD t ASR t ASC t RAH Row t CAH Column 1 t RWD t AWD t CWD WE t RCS t WP t DZC t DS t DH Din t DZO
t OED
t ASC t CAH Column 2 t CWL t RCS t CPW t AWD t CWD t CWL t RCS
t ASC t CAH Column N t CPW t AWD t CWD t RWL t CWL
Address
t WP t DZC t DS t DH Din 2 t OED t OEH t DZO t OED
t WP t DZC t DS t DH Din N
Din 1 t DZO t OEH
t OEH
*
OE t OHO t OHO t OHO t AA t OEA t CAC t RAC t AA t CPA t OEA t CAC t AA t CPA t OEA t CAC t CLZ t OEZ t CLZ t OEZ t CLZ t OEZ
High-Z
Dout
Dout 1
Dout 2
Dout N
22
HM51W17400B Series
Test Mode Cycle *19
*,** Reset Cycle
Set Cycle**
Test Mode Cycle
Normal Mode
RAS
CAS
WE
* CBR or RAS-only refresh ** Address, Din, OE: H or L
23
HM51W17400B Series
Test Mode Set Cycle
t RC t RP t RAS t RP
RAS
tT CAS t CP t WTS
t WTH
WE
Address t OFF High-Z
Dout
24
SP C@ ,, S R P C B @
t CP
t RPC
t CSR
t CHR
t RPC
t CRP
HM51W17400B Series
Self Refresh Cycle (L-version)
t RASS
t RP
t RPS
RAS tT t CRP
+ * $
t RPC t CP t CSR t CHS CAS t WRP t WRH WE t OFF Dout High-Z

* Address, OE : H or L
The low self refresh current is achieved by introducing extremely long internal refresh cycle. Therefore some care needs to be taken on the refresh. 1. Please do not use tRASS timing, 10 s t RASS 100 s. During this period, the device is in transition state from normal operation mode to self refresh mode. If tRASS 100 s, then RAS precharge time should use tRPS instead of t RP . 2. If you use distributed CBR refresh mode with 15.6 s interval in normal read/write cycle, CBR refresh should be executed within 15.6 s immediately after exiting from and before entering into self refresh mode. 3. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 2048 cycles of distributed CBR refresh with 15.6 s interval should be executed within 32 ms immediately after exiting from and before entering into the self refresh mode. 4. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again.
25
HM51W17400B Series
Package Dimensions
HM51W17400BS/BLS Series (CP-26/24DB)
16.90 17.27 Max 21 19
Unit: mm
26
14
1
3.50 0.26
68 0.74
13
8.51 0.13
7.62 0.13
1.30 Max
0.43 0.10 0.10
2.54 1.27
0.80
6.71 0.25
HM51W17400BTS/BLTS Series (TTP-26/24DA)
17.14 17.54 Max 21 19
2.65 0.12
+0.25 -0.17
Unit: mm
26
14 7.62
1 0.40 0.10
68 1.27 0.21 M 1.15 Max
13
9.22 0.20 0 - 5 0.68 0.80
0.145
0.10
0.13 0.05
1.20 Max
+0.075 -0.025
2.54
0.50 0.10
26

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