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ST14C02C
Memory Card IC 2 Kbit (256 x 8) Serial I Bus EEPROM
2C
DATA BRIEFING
s s s s s
Single Supply Voltage (3 V to 5.5 V) Two Wire I2C Serial Interface BYTE and MULTBYTE WRITE (up to 4 Bytes) PAGE WRITE (up to 8 Bytes) BYTE, RANDOM and SEQUENTIAL READ Modes Self-Timed Programming Cycle
2 2 2 2
s s s s s
Automatic Address Incrementing Enhanced ESD/Latch-Up Behaviour 1 Million Erase/Write Cycles (minimum) 10 Year Data Retention (minimum)
Micromodule (D15) Micromodule (D20)
DESCRIPTION This device is an electrically erasable programmable memory (EEPROM) fabricated with STMicroelectronics's High Endurance, Advanced Polysilicon, CMOS technology. This guarantees an endurance typically well above one million Erase/Write cycles, with a data retention of 10 years. The memory operates with a power supply as low as 3 V. The device is available in wafer form (either sawn or unsawn) and in micromodule form (on film). Each memory is compatible with the I2C standard. This is a two wire serial interface that uses a bi-directional data bus and serial clock. The memory carries a built-in 7-bit unique Device Type Identifier code (1010000) in accordance with the I 2C bus
Wafer
Figure 1. Logic Diagram
VCC
Table 1. Signal Names
SDA Serial Data/Address Input/ Output Serial Clock Write Mode Supply Voltage Ground
SCL ST14C02C MODE SDA
SCL MODE VCC GND
GND
AI01162
September 1998
Complete data available on Data-on-Disc CD-ROM or at www.st.com
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ST14C02C
Figure 2. D15 Contact Connections Figure 3. D20 Contact Connections
VCC VCC GND
GND
SCL SCL SDA
SDA MODE
AI02492
AI02491
definition. Only one memory can be attached to each I2C bus. The memory behaves as a slave device in the I2C protocol, with all memory operations synchronized by the serial clock. Read and write operations are initiated by a START condition, generated by the bus master. The START condition is followed by the Device Select Code which is composed of a stream of 7 bits (1010000), plus one read/write bit (R/W) and is terminated by an acknowledge bit. When writing data to the memory, the memory inserts an acknowledge bit during the 9th bit time, following the bus master's 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a STOP condition after an Ack for WRITE, and after a NoAck for READ.
ORDERING INFORMATION Devices are shipped from the factory with the memory content set at all `1's (FFh). The notation used for the device number is as shown in Table 2. For a list of available options (speed, package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. Sawn wafers are scribed and mounted in a frame on adhesive tape. The orientation is defined by the position of the GND pad on the die, viewed with active area of product visible, relative to the notches of the frame (as shown in Figure 4). The orientation of the die with respect to the plastic frame notches is specified by the Customer. One further concern, when specifying devices to be delivered in this form, is that wafers mounted on adhesive tape must be used within a limited period from the mounting date: - two months, if wafers are stored at 25C, 55% relative humidity - six months, if wafers are stored at 4C, 55% relative humidity
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ST14C02C
Table 2. Ordering Information Scheme
Example: ST14C02C D20
Delivery Form D15 D20 W2 W4 Module on Super 35 mm film Module on Super 35 mm film Unsawn wafer (275 m 25 m thickness) Unsawn wafer (180 m 15 m thickness) Sawn wafer (275 m 25 m thickness) Sawn wafer (180 m 15 m thickness) GND at top right GND at bottom right GND at bottom left GND at top left
S2x S4x
where "x" indicates the sawing orientation, as follows (and as shown in Figure 4) 1 2 3 4
Figure 4. Sawing Orientation
VIEW: WAFER FRONT SIDE
GND
GND
GND
GND
ORIENTATION
1
2
3
4
AI02171
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