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| ST7 FAMILY PROGRAMMING MANUAL INTRODUCTION The ST7 family of HCMOS Microcontrollers has been designed and built around an industry standard 8-bit core and a library of peripheral blocks, which include ROM, EPROM, RAM, EEPROM, I/ O, Serial Interfaces (SPI, SCI, I2C,...), 16-bit Timers, etc. These blocks may be assembled in various combinations in order to provide cost-effective solutions for application dedicated products. The ST7 family forms part of the STMicroelectronics 8-bit MCU product line, and finds place in a wide variety of applications such as automotive systems, remote controls, video monitors, car radio and numerous other consumer, industrial, telecom, multimedia and automotive products. ST7 ARCHITECTURE The 8-bit ST7 Core is designed for high code efficiency. It contains 6 internal registers, 17 main addressing modes and 63 instructions. The 6 internal registers include 2 Index registers, an Accumulator, a 16-bit Program Counter, a Stack Pointer and a Condition Code register. The two Index registers X and Y enable Indexed Addressing modes with or without offset, along with read-modify-write type data manipulations. These registers simplify branching routines and data modifications. The 16-bit Program Counter is able to address up to 64K of ROM/EPROM memory. The 6-bit Stack Pointer provides access to a 64-level Stack and an upgrade to an 8-bit Stack Pointer is foreseen in order to be able to manage a 256-level Stack. The Core also includes a Condition Code Register providing 5 Condition Flags that indicate the result of the last instruction executed. The 17 main Addressing modes, including Indirect Relative and Indexed addressing, allow sophisticated branching routines or CASE-type functions. The Indexed Indirect Addressing mode, for instance, permits look-up tables to be located anywhere in the address space, thus enabling very flexible programming and compact C-based code. The 63-instruction Instruction Set is 8-bit oriented with a 2-byte average instruction size. This Instruction Set offers, in addition to standard data movement and logic/arithmetic functions, byte multiplication, bit manipulation, data transfer between Stack and Accumulator (Push/Pop) with direct stack access, as well as data transfer using the X and Y registers. Depending of the target device, different methods of Interrupt priority management may be selected: the number of Interrupt vectors can vary from 6 to 16, and the priority level may be managed by software on some versions. Some peripherals include Direct Memory Access (DMA) between serial interfaces and memory. Power-saving may be managed under program control by placing the device in WAIT or HALT mode. A high test coverage is achieved for ST7 family devices thanks to the use of an autotest method based on "Cyclic Redundancy Checking" (CRC). This approach is based on the analysis of a data flow comprising not only input and output, but also internal data, which affords a detailed inside view of the behaviour of the core and of the peripherals. Rev. 1.1 March 1999 This is advanced information from STMicroelectronics. Details are subject to change without notice. 1/96 1 Table of Contents INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . 1 1 GLOSSARY . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 ST7 CORE DESCRIPTION . . . . . . . . . . . . . 6 2.1 INTRODUCTION . . . . . . . . . . . . . . . . 6 2.2 CPU REGISTERS . . . . . . . . . . . . . . . 6 3 ST7 ADDRESSING MODES . . . . . . . . . . . . 8 Inherent: . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Immediate: . . . . . . . . . . . . . . . . . . . . . . . 10 Direct (short, long): . . . . . . . . . . . . . . . . . 11 Short direct: . . . . . . . . . . . . . . . . . . . . . . . 12 Long direct: . . . . . . . . . . . . . . . . . . . . . . . 13 Indexed (no offset, short, long) . . . . . . . . 14 (no offset) Indexed: . . . . . . . . . . . . . . . . . 15 Short Indexed: . . . . . . . . . . . . . . . . . . . . . 16 Long Indexed: . . . . . . . . . . . . . . . . . . . . . 17 Indirect (short, long): . . . . . . . . . . . . . . . . 18 Short Indirect: . . . . . . . . . . . . . . . . . . . . . 19 Long Indirect: . . . . . . . . . . . . . . . . . . . . . 20 Indirect indexed (short, long): . . . . . . . . . 21 Short indirect indexed: . . . . . . . . . . . . . . 22 Long indirect indexed: . . . . . . . . . . . . . . . 24 Relative mode (direct, indirect): . . . . . . . . 26 Relative (Direct): . . . . . . . . . . . . . . . . . . . 26 Relative Indirect: . . . . . . . . . . . . . . . . . . . 28 4 ST7 INSTRUCTION SET . . . . . . . . . . . . . . 30 4.1 INTRODUCTION . . . . . . . . . . . . . . . 30 4.2 INSTRUCTION SET SUMMARY . . . 31 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 ADD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 BCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 BRES . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 BSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 BTJF . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 BTJT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 CALL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 CALLR . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 CLR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 CP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 CPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 DEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 HALT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 INC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 IRET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 JP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 JRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 JRxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 LD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 MUL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 NEG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 NOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 POP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 PUSH . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 RCF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 RET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 RIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 RLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 RRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 RSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 SBC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 SCF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 SIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 SLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 SLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 SRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 SRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 SUB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 SWAP . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 TNZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 TRAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 WFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 XOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5 SOFTWARE Library . . . . . . . . . . . . . . . . . 82 5.1 TIPS GENERAL TRICKS . . . . . . . . . 83 5.2 DBSET/DBRES, DYNAMIC BIT SET/RESET . . . . . . . . . . . . . . . . . . . 84 5.3 JMPCALLTBL, IMPLEMENTATION OF JUMP/CALL VECTOR TABLES 85 5.4 UNSIGNED WORD MULTIPLICATION . . . . . . . . . . . . . . 86 5.5 UNSIGNED LONG WORD BY WORD DIVISION . . . . . . . . . . . . . . . 88 5.6 MIN./MAX. CHECK . . . . . . . . . . . . . 91 5.7 RANGE CHECK . . . . . . . . . . . . . . . . 93 2/96 2 INTRODUCTION ADDITIONAL BLOCKS The additional blocks take the form of integrated hardware peripherals arranged around the central processor core. The following list details the features of some of the currently available blocks: ROM User ROM, in sizes up to 64K EPROM EPROM based devices, same sizes as ROM RAM Sizes up to several K byte EEPROM Sizes up to several K byte. Erase/programming operations do not require additional external power sources. Up to 32 bytes can be programmed or erased simultaneously. TIMER Different versions based on a 16-bit free running timer/counter are available. They can be coupled with either input captures, output compares or PWM facilities. PWM Software programmable duty cycle between 0% to 100% in up to 1024 steps. The outputs can be filtered to provide D/A conversion. A/D CONVERTER The Analog to Digital Converter uses a sample and hold technique. It has an 8-bit range. I2C Multi/master, single master, single slave modes, DMA or 1byte transfer, standard and fast I2C modes, 7 and 10-bit addressing. SPI The Serial peripheral Interface is a fully synchronous 4 wire interface ideal for Master and Slave applications such as driving devices with input shift register (LCD driver, external memory,...). The Serial Communication Interface is a fast asynchronous interface which features both duplex transmission, NRZ format, programmable baud rates and standard error detection. The SCI can also emulate RS232 protocol. WATCHDOG It has the ability to induce a full reset of the MCU if its counter counts down to zero prior to being reset by the software. This feature is especially useful in noisy applications. I/O PORTS They are programmable from software to act in several input or output configurations on an individual line basis including high current and interrupt generation. The basic block has eight CMOS/TTL compatible lines. LCD Liquid Crystal Display drive with simple addressing in RAM and drive capability from 1 to 16 multiplexing rates. Static DAC True Digital to Analog Converter with up to 12-bit resolution. DDC Complete DDC interface for "plug and play" multimedia applications SYNC PROC. East/West deflection and synchronization processor for digital monitors. RDS Complete RDS decoder embedded in the device for radio applications. New blocks are continuously being added to the peripheral block library to meet customers' specific needs with regard to the optimal integration level in high volume projects. SCI 3/96 3 INTRODUCTION ST7 DEVELOPMENT SUPPORT The ST7 family of MCUs is supported by a comprehensive range of development tools. This family presently comprises hardware tools (emulators, programmers), a software package (assemblerlinker, debugger, archiver) and a C-compiler development tool. The PC-compatible host system forms the platform for the assembler/linker and for the symbolic debugger; it also controls the emulator and enables object code to be downloaded through the RS232 serial link. The real-time emulator is connected through the probe to the target application. It provides the proper electrical connections, thus allowing duplication of the MCU's functions in the target system. The user program can be executed in real time, in step-by-step mode, or by stepping over call modes. Breakpoints can be included on instructions, on memory addresses, on address ranges, on the state of one of two output triggers, as well as in trap mode (automatic reset). A logical analyser mode can record four input signals as external events, using a 1K x 32-bit trace and six recording modes, with or without breakpoints. In addition, two output signals are available for synchronisation and for timing measurement. Each member of the ST7 family has an exclusive probe, dedicated to the device and package. A remote programming tool is available to program EPROM and OTP devices independently (Epromer) or by batches of 10 parts (Gang programmer). The ST7 assembler is used to translate the source code into relocatable machine code. It accepts a source file written in ST7 assembly language and transforms it into a linkable object file. The assembler recognizes the use of symbols, macros and conditional assembly directives. The ST7 linker/ loader combines a number of object files into a single program, associating an absolute address to each section of code. It generates a binary file, containing the image of the ST7 EPROM or ROM memory content. The ST7 library archiver maintains libraries of software object files. Libraries may be used as entry for the linker/loader, together with object files. This allows the user to develop standard modules for repetitive use. The ST7 executable file formatter is responsible for generating an executable file. This file can be downloaded to the emulator or, via the debugger, to the Eprom or OTP device for evaluation and small volume production with the programmer or sent to STMicroelectronics for production of ROM parts. A C-compiler development environment is also available. It includes an editor, a compiler, a linker, a debugger and a simulator which are WindowsTM compatible, and take full advantage of the ST7 architecture to generate excellent quality code. 4/96 4 GLOSSARY 1 GLOSSARY mnem src dst cy lgth op-code mnemonic source destination duration of the instruction in CPU clock cycles (internal clock) length of the instruction in byte(s) instruction byte(s) implementation (1..4 bytes) memory location a byte represent a short 8-bit addressing mode represent a long 16-bit addressing mode LS Least Significant Byte of a 16-bit value (LSB) AAccumulator Register X Index Register Y Index Register A, X or Y register index register, either X or Y 16-bit Program Counter Register 16-bit Stack Pointer Stack Pointer LSB Condition Code Register: 1 1 H I N Z C X Y reg ndx PC SP S CC 1 mem byte short long Effective Address: The final computed data byte address Page Zero all data located at [00..FF] addressing space (single byte address) (XX) XX MS content of a memory location XX a byte value Most Significant Byte of a 16-bit value (MSB) EA For each instruction, we show how it affects the CC flags: Nothing Flag not affected Flag NameFlag affected 0Flag cleared 1Flag set Example: H I 0 N N Z Z C 1 See the Core Description for further details on the CC Register content 5/96 5 ST7 CORE DESCRIPTION 2 ST7 CORE DESCRIPTION 2.1 INTRODUCTION The CPU has a full 8-bit architecture. Six internal registers allow efficient 8-bit data manipulations. The CPU is able to execute 63 basic instructions. It features 17 main addressing modes and can address 6 internal registers. 2.2 CPU Registers The 6 CPU registers are shown in the programming model in Figure 1.. Following an interrupt, the registers are pushed onto the stack in the order shown in Figure 2.. They are popped from stack in the reverse order. The Y register is not affected by these automatic procedures. The interrupt routine must therefore handle it, if needed, through the POP and PUSH instructions. Figure 1. Programming Mode 7 ACCUMULATOR: 0 Accumulator (A). The accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations as well as data manipulations. Index Registers (X and Y). These 8-bit registers are used to create effective addresses or as temporary storage area for data manipulations. The cross assembler generates a PRECEDE instruction (PRE) to indicate that the following instruction refers to the Y register. The Y register is never automatically stacked. Interrupt routines must push or pop it by using the POP and PUSH instructions. Program Counter (PC). The program counter is a 16-bit register used to store the address of the next instruction to be executed by the CPU. It is automatically refreshed after each processed instruction. As a result, the ST7 core can access up to 64 kb of memory. 7 X INDEX REGISTER: 0 7 Y INDEX REGISTER: 0 15 PROGRAM COUNTER: 7 0 15 STACK POINTER: 7 0 CONDITION CODE REGISTER: X = Undefined 76543210 111HI NZC VR01767D 6/96 6 ST7 CORE DESCRIPTION Stack Pointer (SP): The stack pointer is a 16-bit register. The 6 least significant bits contain the address of the next free location of the stack. The 10 most significant bits are forced to a preset value. They are reserved for future extension of ST72 family. The stack is used to save the CPU context on subroutines calls or interrupts. The user can also directly use it through the POP and PUSH instructions. After an MCU reset, or after the Reset Stack Pointer instruction (RSP), the Stack Pointer is set to its upper value. It is then decremented after data has been pushed onto the stack and incremented after data is popped from the stack. When the lower limit is exceeded, the stack pointer wraps around to the stack upper limit. The previously stored information is then overwritten, and therefore lost. A subroutine call occupies two locations and an interrupt five locations. Condition Code Register (CC): The Condition Code register is a 5-bit register which indicates the result of the instruction just executed as well as the state of the processor. These bits can be individually tested by a program and specified action taken as a result of their state. The following paragraphs describe each bit. Half carry bit (H): The H bit is set to 1 when a carry occurs between the bits 3 and 4 of the ALU during an ADD or ADC instruction. The H bit is useful in BCD arithmetic subroutines. Interrupt mask (I): When the I bit is set to 1, all interrupts are disabled. Clearing this bit enables them. Interrupts requested while I is set, are latched and can be processed when I is cleared (only one interrupt request Figure 2. Stacking Order 7 1 INCREASING RETURN MEMORY ADDRESSES 1 1 H I per interrupt enable flag can be latched). This bit can be set/reset by software and is automatically set after reset or at the beginning of an interrupt routine. Negative (N): When set to 1, this bit indicates that the result of the last arithmetic, logical or data manipulation is negative (i.e. the most significant bit is a logic 1). Zero (Z): When set to 1, this bit indicates that the result of the last arithmetic, logical or data manipulation is zero. Carry/Borrow (C): When set, C indicates that a carry or borrow out of the ALU occurred during the last arithmetic operation on the MSB operation result bit. This bit is also affected during bit test, branch, shift, rotate and load instructions. See ADD, ADC, SUB, SBC instructions. In bit test operations, C is the copy of the tested bit. See BTJF, BTJT instructions. In shift and rotates operations, the carry is updated. See RRC, RLC, SRL, SLL, SRA instructions This bit can be set/reset by S/W Example: Addition:$B5 + $94 = "C" + $49 = $149 C 0 7 1 0 1 1 0 1 0 0 1 C + 0 7 1 0 0 1 0 1 0 0 0 C = 1 7 0 1 0 0 1 0 0 0 1 0 N Z C INTERRUPT STACK (PUSH) DECREASING MEMORY ADDRESSES ACCUMULATOR X INDEX REGISTER PCH UNSTACK (POP) PCL 7/96 7 ST7 ADDRESSING MODES 3 ST7 ADDRESSING MODES The ST7 core features 17 different addressing modes which can be classified in 7 main groups: Addressing Mode Inherent Immediate Direct Indexed Indirect Relative Bit operation Example nop ld A,#$55 ld A,$55 ld A,($55,X) ld A,([$55],X) jrne loop bset byte,#5 The ST7 Instruction set is designed to minimize the number of required bytes per instruction: To do Table 1. ST7 Addressing Mode Overview: Mode Inherent Immediate Short Long No Offset Short Long Short Long Short Long Relative Relative Bit Bit Bit Bit Direct Direct Direct Direct Direct Indirect Indirect Indirect Indirect Direct Indirect Direct Indirect Direct Indirect Relative Relative Indexed Indexed Indexed Indexed Indexed nop ld A,#$55 ld A,$10 ld A,$1000 ld A,(X) ld A,($10,X) so, most of the addressing modes can be split in two sub-modes called long and short: - The long addressing mode is the most powerful because it can reach any byte in the 64kb addressing space, but the instruction is bigger and slower than the short addressing mode. - The short addressing mode is less powerful because it can generally only access the page zero (00..FF range), but the instruction size is more compact, and faster. All memory to memory instructions are only working with short addressing modes (CLR, CPL, NEG, BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP) Both modes have pros and cons, but the programmer doesn't need to choose which one is the best: the ST7 Assembler will always choose the best one. Destination Ptr adr Ptr size Lgth +0 +1 00..FF 0000..FFFF 00..FF 00..1FE 0000..FFFF 00..FF 0000..FFFF 00..1FE 0000..FFFF PC+/-127 PC+/-127 00..FF 00..FF 00..FF 00..FF 00..FF byte 00..FF byte 00..FF byte 00..FF 00..FF 00..FF 00..FF byte word byte word +1 +2 +0 +1 +2 +2 +2 +2 +2 +1 +2 +1 +2 +2 +3 Syntax ld A,($1000,X) ld A,[$10] ld A,[$10.w] ld A,([$10],X) ld A,([$10.w],X) jrne loop jrne [$10] bset $10,#7 bset [$10],#7 btjt $10,#7,skip btjt [$10],#7,skip 8/96 8 ST7 ADDRESSING MODES Inherent: All related instructions are single byte ones. The op-code fully specify all required information for the CPU to process the operation. These instructions are single byte ones. Example: 1000 98 rcf 1001 9D nop Action: Do the operation: Inherent Instruction NOP TRAP WFI HALT RET IRET SIM RIM SCF RCF RSP LD CLR PUSH/POP INC/DEC TNZ CPL, NEG MUL SLL, SRL, SRA, RLC, RRC SWAP No operation S/W Interrupt Wait For Interrupt (Low Power Mode) Halt Oscillator (Lowest Power Mode) Sub-routine Return Interrupt Sub-routine Return Set Interrupt Mask Reset Interrupt Mask Set Carry Flag Reset Carry Flag Reset Stack Pointer Load Clear Push/Pop to/from the stack Increment/Decrement Test Negative or Zero 1 or 2 Complement Byte Multiplication Shift and Rotate Operations Swap Nibbles Function 9/96 9 ST7 ADDRESSING MODES Immediate: The required data byte to do the operation is following the op-code. Immediate Instruction LD CP BCP AND, OR, XOR ADC, ADD, SUB, SBC Load Compare Bit Compare Logical Operations Arithmetic Operations Function These are two byte instructions, one for the opcode and the other one for the immediate data byte. Example: 1000 AEFF ld X,#$FF 1002 A355 cp X,#$55 1004 A6F8 ld A,#$F8 Action: X = $FF Compare (X, $55) A = $F8 Figure 3. Immediate Addressing Mode Example Before Completion A Previous Value PC LD A, #0F8h A6 F8 05BE 05BF 05C0 05BE PC = 05BE PC = PC + 1 = 05BF EA = PC New PC = PC + 1 = 05C0 Steps to Determine Effective Address After Completion Instruction Complete A F8 A6 F8 05BE 05BF 05C0 New PC 05C0 VR02059A A = (EA) = F8 New PC = 05C0 10/96 10 ST7 ADDRESSING MODES Direct (short, long): Addressing mode Short Long Direct Direct Syntax (ptr) (ptr) EA formula (ptr) (ptr.w) Ptr Adr op + 1 op + 1..2 Ptr Size Byte Word Dest adr 00..FF 0000..FFF F The required data byte to do the operation is found by its memory address, which follows the op-code. The direct addressing mode is made of two sub-modes: Available Long and Short Direct Instructions LD CP AND, OR, XOR ADC, ADD, SUB, SBC BCP Load Compare Logical Operations Arithmetic Additions/Substractions operations Bit Compare Function Short Direct Instructions Only CLR INC, DEC TNZ CPL, NEG BSET, BRES BTJT, BTJF SLL, SRL, SRA, RLC, RRC SWAP CALL, JP Clear Increment/Decrement Test Negative or Zero 1 or 2 Complement Bit Operations Function Bit Test and Jump Operations Shift and Rotate Operations Swap Nibbles Call or Jump subroutine 11/96 11 ST7 ADDRESSING MODES Short direct: The address is a byte, thus require only one byte after the op-code, but only allow 00..FF addressing space. Example: 004B 052D Action: 20 B64B coeff dc.b$20 ld A,coeff A = (coeff) = ($4B) = $20 Figure 4. Short Direct Addressing Mode Example Before Completion Steps to Determine Effective Address A Coeff .byte 20h 20 004B Previous Value PC B6 LD A,Coeff 4B 052D 052E 052F 052D PC = 052D PC = PC + 1 = 052E EA = (PC) = (4B + 0000) = 004B New PC = PC + 1 = 052F EA 004B After Completion A Coeff .byte 20h 20 004B 20 Instruction Complete B6 LD A,Coeff 4B 052D 052E 052F New PC 052F A = (EA) = 20 New PC = 052F VR02059L 12/96 12 ST7 ADDRESSING MODES Long direct: The address is a word, thus allowing 64 kb addressing space, but requires 2 bytes after the op-code. Example: 0409 06E5 Action: C606E5 40 coeff ld A,coeff dc.b$ 40 A = (coeff) = ($06E5) = $40 Figure 5. Long Direct Addressing Mode Example Before Completion A Previous Value PC LD A,Coeff C6 06 E5 0409 040A 040B 040C 06E5 0409 PC = 0409 PC = PC + 1 = 040A EA = (PC) : (PC+1) = 06E5 New PC = PC + 2 = 040C Steps to Determine Effective Address Coeff .byte 040h 40 06E5 EA 06E5 After Completion Instruction Complete LD A,Coeff C6 06 E5 0409 040A 040B 040C New PC 040C A Coeff .byte 040h 40 06E5 40 VR02059B A = (EA) = 40 New PC = 040C 13/96 13 ST7 ADDRESSING MODES Indexed (no offset, short, long) Addressing mode No offset Short Long Direct Direct Direct Indexed Indexed Indexed Syntax (ndx) (ptr,ndx) (ptr.w,ndx) EA formula (ndx) (ptr + ndx) (ptr.w + ndx) Ptr Adr --op + 1 op + 1..2 Ptr Size --Byte Word Dest adr 00..FF 00..1FE 0000..FFFF The required data byte to do the operation is found by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset which follows the op-code. The indexed addressing mode is made of three sub-modes: No Offset, Long and Short Indexed Instructions LD CP AND, OR, XOR ADC, ADD, SUB, SBC BCP Load Compare Logical Operations Arithmetic Additions/Substractions operations Bit Compare Function No Offset and Short Indexed Instructions Only CLR INC, DEC TNZ CPL, NEG BSET, BRES BTJT, BTJF SLL, SRL, SRA, RLC, RRC SWAP CALL, JP Clear Increment/Decrement Test Negative or Zero 1 or 2 Complement Bit Operations Function Bit Test and Jump Operations Shift and Rotate Operations Swap Nibbles Call or Jump subroutine 14/96 14 ST7 ADDRESSING MODES (no offset) Indexed: There is no offset, (no extra byte after the op-code), but only allows 00..FF addressing space. Example: 00B8 11223344 table dc.w$1122, $3344 05F2 AEB8 ld X,#table 05F4 F6 ld A,(X) Action: X = table A = (X) = (table) = ($B8) = $11 Figure 6. No offset Indexed Addressing Mode Example Before Completion A Previous Value Table .word 1122 11 22 33 44 PC LD A,(X) F6 05F4 05F4 EA B8 00B8 X B8 Steps to Determine Effective Address PC = 05F4 EA = X + 0000 = 00B8 New PC = PC + 1 = 05F5 After Completion A Table .word 1122 11 22 33 44 00B8 11 X B8 Instruction Complete A = (EA) = 11 New PC = 05F5 LD A,(X) F6 05F4 05F5 New PC 05F5 VR02059C 15/96 15 ST7 ADDRESSING MODES Short Indexed: The offset is a byte, thus require only one byte after the op-code, but only allow 00..1FE addressing space. Example: 0089 0759 075B Action: 11223344 table dc.l $11223344 AE03 ld X,#3 E689 ld A,(table,X) X =3 A = (table, X) = ($89, X) = ($89, 3) = ($8C) = $44 Figure 7. Short Indexed - 8-bit offset - Addressing Mode Example Before Completion A Table .long 1122334 4 11 22 33 44 0089 008A 008B 008C Steps to Determine Effective Address PC = 075B PC = PC + 1 = 075C EA = (PC) + X = 89 + 03 = 008C New PC = PC + 1 = 075D Previous Value X 03 PC LD A, (table,X) E6 89 075B 075C 075D 075B Adder EA 008C After Completion Table .long 11223344 11 22 33 44 0089 008A 008B 008C Instruction Complete A 44 X 03 A = (EA) = 44 New PC = 075D LD A, (table,X) E6 89 075B 075C 075D New PC 075D VR02059D 16/96 16 ST7 ADDRESSING MODES Long Indexed: The offset is a word, thus allowing 64 kb addressing space, but requires 2 bytes after the op-code. Example: 0690 AE02 ld X,#2 0692 D6077E ld A,(table,X) 077E Action: BF table dc.b$BF 86 dc.b$86 DBCF dc.w$DBCF X =2 A = (table, X) = ($077E, X) = ($077E, 2) = ($0780) = $DB Figure 8. Long Indexed - 16-bit offset - Addressing Mode Example Before Completion PC LD A, (table, X) D6 07 7E 0692 0693 0694 X 02 table . byte BF BF 86 DB CF 077E 077F 0780 0781 Adder A Previous Value 0692 Steps to Determine Effective Address PC = 0692 PC = PC + 1 = 0693 EA = (PC):(PC+1) + (X) = 077E + 02 = 0780 New PC = PC + 2 = 0695 EA 0780 After Completion X LD A, (table, X) D6 07 7E 0692 0693 0694 0695 New PC 0695 02 A = (EA) = DB New PC = 0695 Instruction Complete table . byte BF BF 86 DB CF 077E 077F 0780 0781 A DB VR02059E 17/96 17 ST7 ADDRESSING MODES Indirect (short, long): Addressing mode Short Long Indirect Indirect Syntax ((ptr)) ((ptr.w)) EA formula ((ptr)) ((ptr.w)) Ptr Adr 00..FF 00..FF Ptr Size Byte Word Dest adr 00..FF 0000..FFFF The required data byte to do the operation is found by its memory address, located in memory (pointer). The pointer address follows the op-code. The indirect addressing mode is made of two sub-modes: Available Long and Short Indirect Instructions LD CP AND, OR, XOR ADC, ADD, SUB, SBC BCP Load Compare Logical Operations Arithmetic Additions/Substractions operations Bit Compare Function Short Indirect Instructions Only CLR INC, DEC TNZ CPL, NEG BSET, BRES BTJT, BTJF SLL, SRL, SRA, RLC, RRC SWAP CALL, JP Clear Increment/Decrement Test Negative or Zero 1 or 2 Complement Bit Operations Function Bit Test and Jump Operations Shift and Rotate Operations Swap Nibbles Call or Jump subroutine 18/96 18 ST7 ADDRESSING MODES Short Indirect: The pointer address is a byte, the pointer size is a byte, thus allowing 00..FF addressing space, and requires 1 byte after the op-code. Example: 0020 42 var dc.b$42 004B 20 ptr dc.bvar 052D 92B64B ld A,[ptr] Action: A = [ptr] = ((ptr)) = (($4B)) = ($20) = $42 Figure 9. Short Indirect Addressing Mode Example Before Completion Steps to Determine Effective Address A ptr .byte var 20 004B Previous Value PC LD A,[ptr] 92 B6 4B 052D 052E 052F 052D PC = 052D PC = PC + 2 = 052F EA = (PC) = (4B + 0000) = 0020 New PC = PC + 1 = 0530 var .byte 42h 42 0020 EA 0020 After Completion A var .byte 42h 42 0020 42 Instruction Complete LD A, [ptr] 92 B6 4B 052D 052E 052F New PC 0530 A = (EA) = 42 New PC = 0530 VR02059F 19/96 19 ST7 ADDRESSING MODES Long Indirect: The pointer address is a byte, the pointer size is a word, thus allowing 64 kb addressing space, and requires 1 byte after the op-code. Example: 0040 42E5 ptr dc.wvar 0409 92C640 ld A,[ptr.w] 42E5 11 var dc.b$11 Action: A = [ptr.w] = ((ptr.w)) = (($40.w)) = ($42E5) = $11 Figure 10. Long Indirect Addressing Mode Example Before Completion Steps to Determine Effective Address ptr .word var 42 E5 0040 0041 A Previous Value PC LD A, [ptr.w] 92 C6 40 0409 040A 040B 040C 0409 PC = 0409 PC = PC + 2 = 40B EA = ((PC)) :((PC)+1) = 42E5 var.byte 011h 11 42E5 EA 42E5 After Completion Instruction Complete ptr .word var 42 E5 0040 0041 A = (EA) = 011h New PC = 040C LD A, [ptr.w] 92 C6 40 0409 040A 040B 040C New PC 040C A var .byte 011h 11 42E5 011h VR02059G 20/96 20 ST7 ADDRESSING MODES Indirect indexed (short, long): Addressing mode Short Long Indirect Indirect Indexed Indexed Syntax ([ptr],ndx) ([ptr.w],ndx) EA formula ((ptr) + ndx) ( (ptr.w) + ndx ) Ptr Adr 00..FF 00..FF Ptr Size Byte Word Dest adr 00..1FE 0000..FFFF This is a combination of indirect and short indexed addressing mode. The required data byte to do the operation is found by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the op-code. The indirect indexed addressing mode is made of two sub-modes: Long and Short Indi rect Indexed Instructions LD CP AND, OR, XOR ADC, ADD, SUB, SBC BCP Load Compare Logical Operations Arithmetic Additions/Substractions operations Bit Compare Function Short Indirect Indexed Instructions Only CLR INC, DEC TNZ CPL, NEG BSET, BRES BTJT, BTJF SLL, SRL, SRA, RLC, RRC SWAP CALL, JP Clear Increment/Decrement Test Negative or Zero 1 or 2 Complement Bit Operations Function Bit Test and Jump Operations Shift and Rotate Operations Swap Nibbles Call or Jump subroutine 21/96 21 ST7 ADDRESSING MODES Short indirect indexed: The pointer address is a byte, the pointer size is a byte, thus allowing 00..1FE addressing space, and requires 1 byte after the op-code. Example: 0040 0041 0042 0043 0089 0759 075B 00 01 02 03 40 AE03 92E689 table dc.b0,1,2,3 ptr dc.btable ld X,#3 ld A,([ptr],X) Action: X =3 A = ([ptr],X) = ((ptr) , X) = (($89), 3) = ($40, 3) = ($43) = 3 22/96 22 ST7 ADDRESSING MODES Figure 11. Short Indirect Indexed Addressing Mode Example Before Completion table .byte 0,1,2,3 00 01 02 03 0040 0041 0042 0043 A ptr .byte table 40 0089 Previous value X 03 PC 075B LD A, ([ptr.B],X) 92 E6 89 075B 075C 075D 40 Adder 03 Steps to Determine Effective Address PC = 075B PC = PC + 2 = 075D EA = ((PC)) + X + 0000 EA = 40 + 3 = 0043 EA 0043 After Completion table .byte 0,1,2,3 00 01 02 03 0040 0041 0042 0043 A = (EA) = 03 New PC = 075E Instruction Complete ptr .byte table 40 0089 A 03 X 03 LD A, ([ptr.B],X) 92 E6 89 075B 075C 075D New PC 075E VR02059H 23/96 23 ST7 ADDRESSING MODES Long indirect indexed: The pointer address is a byte, the pointer size is a word, thus allowing 64 kb addressing space, and requires 1 byte after the op-code. Example: 0089 0800 0690 0692 0800 10203040 AE03 92D689 ptr table dc.wtable dc.b$10,$20,$30,$40 ld X,#3 ld A,([ptr.w],X) X=3 A = ([ptr.w],X) = ((ptr.w), X) = (($89.w), 3) = ($0800,3) = ($0803) = $40 24/96 24 ST7 ADDRESSING MODES Figure 12. Long Indirect Indexed Addressing Mode Example Before Completion ptr .word table 08 00 0089 008A PC LD A,([ptr.w],X) 92 D6 89 0692 0693 0694 X 03 table .byte 10h,20h,30h,40h 10 20 30 40 800 801 802 803 800 Adder 03 A Previous value 0692 PC = 0692 PC = PC + 2 = 0694 EA = ((PC)) : ((PC)+1) + X EA = 0803 Steps to Determine Effective Address EA 0803 After Completion ptr .word table 08 00 0089 008A X LD A,([ptr.w],X) 92 D6 89 0692 0693 0694 0695 New PC 0695 03 A = (EA) = 40 New PC = 0695 Instruction Complete table .byte 10h,20h,30h ,40h 10 20 30 40 0800 0801 0802 0803 A 40 VR02059I 25/96 25 ST7 ADDRESSING MODES Relative mode (direct, indirect): Addressing mode Direct Indirect Relative Relative Syntax oft [oft] EA formula PC = PC + oft PC = PC + (oft) Ptr Adr op + 1 00..FF Ptr Size --Byte Dest adr PC +/- 127 PC +/- 127 This addressing mode is used to modify the PC register value, by adding an 8-bit signed offset to it. The relative addressing mode is made of two sub-modes: Available Relative Direct/Indirect Instructions JRxx CALLR Conditional Jump Call Relative Function Relative (Direct): The offset is following the op-code. Example: 04A7 2717 jreqskip 04A9 9D nop 04AA 9D nop 04C0 Action: 20FE if (Z == 1) skip jra * ; Infinite loop = $04C0 thenPC = PC + $17 = $04A9 + $17 elsePC = PC = $04A9 26/96 26 ST7 ADDRESSING MODES Figure 13. Relative Direct Indexed Addressing Mode Example Before Completion CC Z JREQ SKIP 27 17 04A7 04A8 04A9 02 PC 04A7 Steps to Determine Effective Address PC = 04A7 PC = PC + 1 = 04A8 TEMP = (PC) = 17 Adder 04A7 PC = PC +1 = 04A9 Stop here if there is no Branch; i.e., Z = 0 04A9 EA EA = PC + TEMP = 04A9 + 17 = 04C0 New PC = EA if Branch is taken After Completion (Branch taken) CC Z=1 PC JREQ SKIP 27 17 04A7 04A8 04A9 17 Adder SKIP : 04C0 04C0 New PC 04C0 E.A 04A9 New PC = EA = 04C0 04A9 Instruction Complete After Completion (No Branch taken) CC Z=0 InstructionComplete New PC = EA = 04A9 New PC 04A9 JREQ SKIP 27 17 04A7 04A8 04A9 VR02059J 27/96 27 ST7 ADDRESSING MODES Relative Indirect: The offset is defined in memory, which address follows the op-code. Example: 0089 50 offset dc.b$50 0800 922789 jreg[offset] 0803 9D nop 0853 9D nop Relative Indirect Indexed Addressing Mode Example 28/96 28 ST7 ADDRESSING MODES Before Completion CC offset .byte 050h 50 0089 Z PC JREQ [offset] 92 27 89 9D 0800 0801 0802 0803 0800 Steps to Determine Effective Address PC = PC +2 = 0802 Temp = ((PC)) = 50 PC = PC+1 = 803 if branch taken EA = PC = 853 EA 9D 0853 0803 After Completion (Branch taken) CC offset .byte 050h 50 0089 Z =1 PC JREQ [offset] 92 27 89 9D 0800 0801 0802 50 0803 adder 0803 0803 EA 0853 New PC 9D 0853 0853 After Completion (Branch not taken) CC offset .byte 050h 50 0089 Z=0 JREQ [offset] 92 27 89 9D 0800 0801 0802 0803 New PC 0803 9D 0853 VR02059K 29/96 29 ST7 INSTRUCTION SET 4 ST7 INSTRUCTION SET 4.1 INTRODUCTION This chapter describes all the ST7 instructions. They are 63 and are described in alphabetical order. However, they can be classified in 13 main groups as follows: Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic operations Shift and Rotates Unconditional Jump or Call Conditional Branch Interruption management Code Condition Flag modification LD PUSH INC CP AND BSET BTJT ADC SLL JRA JRxx TRAP SIM WFI RIM HALT SCF IRET RCF CLR POP DEC TNZ OR BRES BTJF ADD SRL JRT SUB SRA JRF SBC RLC JP MUL RRC CALL SWAP CALLR SLA NOP RET BCP XOR CPL NEG RSP Using a pre-byte The instructions are described with one to four bytes. In order to extend the number of available opcodes for an 8-bit CPU (256 op-codes), three different prebyte opcodes are defined. These prebytes modify the meaning of the instruction they precede. The whole instruction becomes: PC-2 End of previous instruction PC-1 Prebyte PC Op-code PC+1 Additional word (0 to 2) according to the number of bytes required to compute the effective address These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are: PDY 90 Replace an X based instruction using immediate, direct, indexed or inherent addressing mode by a Y one. PIX 92 Replace an instruction using direct, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode. PIY 91 Replace an instruction using indirect X indexed addressing mode by a Y one. 30/96 30 ST7 INSTRUCTION SET 4.2 INSTRUCTION SET SUMMARY Mnemo ADC ADD AND BCP BRES BSET BTJF BTJT CALL CALLR CLR CP CPL DEC HALT IRET INC JP JRA JRT JRF JRIH JRIL JRH JRNH JRM JRNM JRMI JRPL JREQ JRNE JRC JRNC JRULT JRUGE JRUGT JRULE Description Add with Carry Addition Logical And Bit compare A, Memory Bit Reset Bit Set Jump if bit is false (0) Jump if bit is true (1) Call subroutine Call subroutine relative Clear Arithmetic Compare One Complement Decrement Halt Interrupt routine return Increment Absolute Jump Jump relative always Jump relative Never jump Jump if Port INT pin = 1 Jum if Port INT pin = 0 Jump if H = 1 Jump if H = 0 Jump if I = 1 Jump if I = 0 Jump if N = 1 (minus) Jump if N = 0 (plus) Jump if Z = 1 (equal) Jump if Z = 0 (not equal) Jump if C = 1 Jump if C = 0 Jump if C = 1 Jump if C = 0 Jump if (C + Z = 0) Jump if (C + Z = 1) jrf * (no Port Interrupts) (Port interrupt) H=1? H=0? I=1? I=0? N=1? N=0? Z=1? Z=0? C=1? C=0? Unsigned < Jmp if unsigned >= Unsigned > Unsigned <= Pop CC, A, X, PC inc X jp [TBL.w] reg, Mem H tst(Reg - Mem) A = FFH-A dec Y reg, Mem reg reg, Mem reg, Mem 0 I N N Z Z C Mem 0 N N N 1 Z Z Z C 1 Function/Example A = A + Mem + C A = A + Mem A = A . Mem tst (A . Mem) bres Byte, #3 bset Byte, #3 btjf Byte, #3, Jmp1 btjt Byte, #3, Jmp1 A A A A Mem Mem Mem Mem C C Dst Src Mem Mem Mem Mem H H H I N N N N N Z Z Z Z Z C C C 31/96 31 ST7 INSTRUCTION SET Mnemo LD MUL NEG NOP OR POP Load Description Function/Example dst <= src X,A = X * A neg $10 Dst reg, Mem A, X, Y reg, Mem Src Mem, reg X, Y, A H I N N Z Z C Multiply Negate (2's compl) No Operation OR operation Pop from the Stack 0 N Z 0 C A = A + Mem pop reg pop CC A reg CC Mem Mem Mem Mem reg, CC H I N N Z Z C PUSH RCF RET RIM RLC RRC RSP SBC SCF SIM SLA SLL SRL SRA SUB SWAP TNZ TRAP WFI XOR Push onto the Stack Reset carry flag Subroutine Return Enable Interrupts Rotate left true C Rotate right true C Reset Stack Pointer Subtract with Carry Set carry flag Disable Interrupts Shift left Arithmetic Shift left Logic Shift right Logic Shift right Arithmetic Substraction SWAP nibbles Test for Neg & Zero S/W trap Wait for Interrupt Exclusive OR push Y C=0 0 I=0 C <= A <= C C => A => C S = Max allowed A = A - Mem - C C=1 I=1 C <= A <= 0 C <= A <= 0 0 => A => C A7 => A => C A = A - Mem A7-A4 <=> A3-A0 tnz lbl1 S/W interrupt reg, Mem reg, Mem reg, Mem reg, Mem A reg, Mem Mem A Mem reg, Mem reg, Mem 0 N N Z Z C C N Z C 1 1 N N 0 N N N N 1 0 Z Z Z Z Z Z Z C C C C C A = A XOR Mem A M N Z 32/96 32 ST7 INSTRUCTION SET ADC Syntax Operation Description adc Addition with Carry dst,src e.g.: adc A,#$15 ADC dst <= dst + src + C The source byte, along with the carry flag, is added to the destination byte and the result is stored in the destination byte. The source is a memory byte, and the destination is the A register. Instruction Overview: mnem ADC dst A src Mem Condition Flags H H I N N Z Z C C Detailed Description: dst A A A A A A A A A A A A A A A #byte short long (X) (short,X) (long,X) (Y) (short,Y) (long,Y) [short] [long.w] ([short],X) ([long.w],X) ([short],Y) ([long.w],Y) src cy 2 3 4 3 4 5 4 5 6 5 6 6 7 6 7 lgth 2 2 3 1 2 3 2 3 4 3 3 3 3 3 3 90 90 90 92 92 92 92 91 91 Op-Cod e(s) A9 B9 C9 F9 E9 D9 F9 E9 D9 B9 C9 E9 D9 E9 D9 XX MS XX XX XX XX XX XX LS XX MS LS XX XX MS LS See Also: ADD,SUB,SBC,MUL 33/96 33 ST7 INSTRUCTION SET ADD Syntax Operation Description add dst <= dst + src dst,src Addition e.g.: add A,#%11001010 ADD The source byte is added to the destination byte and the result is stored in the destination byte. The source is a memory byte, and the destination is the A register. Instruction Overview mnem ADD dst A src Mem Condition Flags H H I N N Z Z C C Detailed Description dst A A A A A A A A A A A A A A A #byte short long (X) (short,X) (long,X) (Y) (short,Y) (long,Y) [short] [long.w] ([short],X) ([long.w],X) ([short],Y) ([long.w],Y) src cy 2 3 4 3 4 5 4 5 6 5 6 6 7 6 7 lgth 2 2 3 1 2 3 2 3 4 3 3 3 3 3 3 90 90 90 92 92 92 92 91 91 Op-Code(s) AB BB CB FB EB DB FB EB DB BB CB EB DB EB DB XX MS XX XX XX XX XX XX LS XX MS LS XX XX MS LS See Also:ADC, SUB, SBC, MUL 34/96 34 ST7 INSTRUCTION SET AND Syntax Operation Description and dst,src dst <= dst AND src Logical e.g.: and A,#%00110101 AND The source byte, is ANDed with the destination byte and the result is stored in the destination byte. The source is a memory byte, and the destination is the A register. Truth Table: AND 0 1 0 0 0 1 0 1 Instruction Overview mnem AND dst A src Mem Condition Flags H I N N Z Z C Detailed Description dst A A A A A A A A A A A A A A A #byte short long (X) (short,X) (long,X) (Y) (short,Y) (long,Y) [short] [long.w] ([short],X) ([long.w],X) ([short],Y) ([long.w],Y) src cy 2 3 4 3 4 5 4 5 6 5 6 6 7 6 7 lgth 2 2 3 1 2 3 2 3 4 3 3 3 3 3 3 90 90 90 92 92 92 92 91 91 Op-Code(s) A4 B4 C4 F4 E4 D4 F4 E4 D4 B4 C4 E4 D4 E4 D4 XX MS XX XX XX XX XX XX LS XX MS LS XX XX MS LS See Also: OR, XOR, CPL, NEG 35/96 35 ST7 INSTRUCTION SET BCP Syntax Operation Description bcp Logical Bit Compare src,dst e.g.: bcp A,#%10100101 BCP {N, Z} <= src AND dst The source byte, is ANDed to the destination byte. The result is lost but condition flags N and Z are updated accordingly. The source is a memory byte, and the destination is A register. This instruction can be used to perform bit tests on A. Instruction Overview mnem BCP dst A src Mem Condition Flags H I N N Z Z C Detailed Description dst A A A A A A A A A A A A A A A #byte short long (X) (short,X) (long,X) (Y) (short,Y) (long,Y) [short] [long.w] ([short],X) ([long.w],X) ([short],Y) ([long.w],Y) src cy 2 3 4 3 4 5 4 5 6 5 6 6 7 6 7 lgth 2 2 3 1 2 3 2 3 4 3 3 3 3 3 3 90 90 90 92 92 92 92 91 91 Op-Code(s) A5 B5 C5 F5 E5 D5 F5 E5 D5 B5 C5 E5 D5 E5 D5 XX MS XX XX XX XX XX XX LS XX MS LS XX XX MS LS See Also: CP, TNZ 36/96 36 ST7 INSTRUCTION SET BRES Syntax Operation bres dst,#pos Bit Reset pos = [0..7] e.g.: bres BRES PADR,#6 dst <= dst AND (2**pos) Description Read the destination byte, reset the corresponding bit (bit position), and write the result in destination byte. The destination is a memory byte. The bit position is a constant. This instruction is fast, compact, and does not affect any register. Very useful for boolean variable manipulation. Instruction Overview mnem BRES dst Mem bit position #pos Condition Flags H I N Z C Detailed Description dst short [short] pos = 0..7 n = 11+2.pos n = 11+2.pos cy 5 7 lgth 2 3 92 Op-Code(s) 1n 1n XX XX See Also: BSET 37/96 37 ST7 INSTRUCTION SET BSET Syntax Operation Description bset dst,#pos dst <= dst OR (2**pos) Bit Set pos = [0..7] e.g.: bset BSET PADR,#0 Read the destination byte, set the corresponding bit (bit position), and write the result in destination byte. The destination is a memory byte. The bit position is a constant. This instruction is fast, compact, and does not affect any register. Very useful for boolean variable manipulation. Instruction Overview mnem BSET dst Mem bit position #pos Condition Flags H I N Z C Detailed Description dst short [short] pos = 0..7 n = 10+2.pos n = 10+2.pos cy 5 7 lgth 2 3 92 Op-Code(s) 1n 1n XX XX See Also: BRES 38/96 38 ST7 INSTRUCTION SET BTJF Syntax Operation Description btjf e.g.: Bit Test and Jump if False dst,#pos,rel btjf pos = [0..7], rel is relative jump label PADR,#3,skip BTJF PC = PC + 3 PC = PC + rel IF (dst AND (2**pos)) = 0 Read the destination byte, test the corresponding bit (bit position), and jump to 'rel' label if the bit is false (0), else continue the program to the next instruction. The tested bit is saved in the C flag. The destination is a memory byte. The bit position is a constant. The jump label points to an memory location around the instruction (relative jump). This instruction is used for boolean variable manipulation, H/W register flag tests, or I/O polling method. This instruction is fast, compact, and does not affect any register. Very useful for boolean variable manipulation. Instruction Overview mnem BTJF dst Mem bit position #pos jump label rel Condition Flags H I N Z C C Detailed Description dst short [short] pos = 0..7 n = 01+2.pos n = 01+2.pos cy 5 7 lgth 3 4 92 Op-Code(s) 0n 0n XX XX XX XX See also: BTJT 39/96 39 ST7 INSTRUCTION SET BTJT Syntax Operation Description btjt e.g.: Bit Test and Jump if True dst,#pos,rel btjt pos = [0..7], rel is relative jump label PADR,#7,skip BTJT PC = PC + 3 PC = PC + rel IF (dst AND (2**pos)) <> 0 Read the destination byte, test the corresponding bit (bit position), and jump to 'rel' label if the bit is true (1), else continue the program to the next instruction. The tested bit is saved in the C flag. The destination is a memory byte. The bit position is a constant. The jump label points to an memory location around the instruction (relative jump). This instruction is used for boolean variable manipulation, H/W register flag tests, or I/O polling method. Instruction Overview mnem BTJT dst Mem bit position #pos jump label rel Condition Flags H I N Z C C Detailed Description dst short [short] pos = 0..7 n = 00+2.pos n = 00+2.pos cy 5 7 lgth 3 4 92 Op-Code(s) 0n 0n XX XX XX XX See Also: BTJF 40/96 40 ST7 INSTRUCTION SET CALL Syntax Operation CALL CALL Subroutine (Absolute) dst e.g.: call divide32_16 CALL PC = PC+lgth (SP--) = LSB (PC) (SP--) = MSB (PC) PC = dst The current PC register value is pushed onto the stack, then PC is loaded with the destination address. This instruction should be used versus CALLR when developing a program. Description Instruction Overview mnem CALL dst Mem Condition Flags H I N Z C Detailed Description dst short long (X) (short,X) (long,X) (Y) (short,Y) (long,Y) [short] [long.w] ([short],X) ([long.w],X) ([short],Y) ([long.w],Y) cy 5 6 5 6 7 6 7 8 7 8 8 9 8 9 lgth 2 3 1 2 3 2 3 4 3 3 3 3 3 3 90 90 90 92 92 92 92 91 91 Op-Code(s) BD CD FD ED DD FD ED DD BD CD ED DD ED DD XX MS XX XX XX XX XX XX LS XX MS LS XX MS LS See Also: CALLR, RET 41/96 41 ST7 INSTRUCTION SET CALLR Syntax Operation CALLR CALL Subroutine Relative dst e.g.: callr chk_pol CALLR PC = PC+lgth (SP--) = LSB(PC) (SP--) = MSB(PC) PC = PC + dst The current PC register value is pushed onto the stack, then PC is loaded with the relative destination addresss.This instruction is used, once a program is debugged, to shrink the overall program size. Description Instruction Overview mnem CALLR dst Mem Condition Flags H I N Z C Detailed Description dst short [short] cy 6 8 lgth 2 3 92 Op-Code(s) AD AD XX XX See Also: CALL, RET 42/96 42 ST7 INSTRUCTION SET CLR Syntax Operation Description clr dst <= 00 dst CLEAR e.g.: clr X CLR The destination byte is forced to 00 value. The destination is either a memory byte location, or a register. This instruction is compact, and does not affect any register when used with RAM variables. Instruction Overview mnem CLR CLR dst Mem Reg Condition Flags H I N 0 0 Z 1 1 C Detailed Description dst A X Y short (X) (short,X) (Y) (short,Y) [short] ([short],X) ([short],Y) cy 3 3 4 5 5 6 6 7 7 8 8 lgth 1 1 2 2 1 2 2 3 3 3 3 90 90 92 92 91 90 Op-Code(s) 4F 5F 5F 3F 7F 6F 7F 6F 3F 6F 6F XX XX XX XX XX XX See Also: LD 43/96 43 ST7 INSTRUCTION SET CP Syntax Operation Description cp dst,src Compare e.g.: cp A,(tbl,X) CP {N, Z, C} = Test (dst - src) The source byte is subtracted from the destination byte and the result is lost. However, N, Z, C are updated according to the result. The destination is a register, and the source is a memory byte. This instruction generally is placed just before a conditional jump instruction. Instruction Overview mnem CP dst Reg src Mem Condition Flags H I N N Z Z C C Detailed Description dst A A A A A A A A A A A A A A A #byte short long (X) (short,X) (long,X) (Y) (short,Y) (long,Y) [short] [long.w] ([short],X) ([long.w],X) ([short],Y) ([long.w],Y) src cy 2 3 4 3 4 5 4 5 6 5 6 6 7 6 7 lgth 2 2 3 1 2 3 2 3 4 3 3 3 3 3 3 90 90 90 92 92 92 92 91 91 Op-Code(s) A1 B1 C1 F1 E1 D1 F1 E1 D1 B1 C1 E1 D1 E1 D1 XX MS XX XX XX XX XX XX LS XX MS LS XX XX MS LS (Continued on next page) 44/96 44 ST7 INSTRUCTION SET CP Detailed Description (Cont'd) dst X X X X X X X X X X #byte short long (X) (short,X) (long,X) [short] [long.w] ([short],X) ([long.w],X) src cy 2 3 4 3 4 5 5 6 6 7 lgth 2 2 3 1 2 3 3 3 3 3 92 92 92 92 Op-Code(s) A3 B3 C3 F3 E3 D3 B3 C3 E3 D3 XX MS XX XX XX XX LS XX XX MS LS dst Y Y Y Y Y Y Y Y Y Y #byte short long (Y) src cy 3 4 5 4 5 6 5 6 6 7 lgth 3 3 4 2 3 4 3 3 3 3 90 90 90 90 90 90 91 91 91 91 Op-Code(s) A3 B3 C3 F3 E3 D3 B3 C3 E3 D3 XX MS XX XX XX XX LS XX XX MS LS (short,Y) (long,Y) [short] [long.w] ([short],Y) ([long.w],Y) See Also: TNZ, BCP 45/96 45 ST7 INSTRUCTION SET CPL Syntax Operation Description cpl Logical 1-Complement dst e.g.: cpl (X) CPL dst <= dst XOR FF, or FF - dst The destination byte is read, then each bit is toggled (inverted) and the result is written at the destination byte. The destination is either a memory byte or a register. This instruction is compact, and does not affect any register when used with RAM variables. Instruction Overview mnem CPL CPL dst Mem Reg Condition Flags H I N N N Z Z Z C 1 1 Detailed Description dst A X Y short (X) (short,X) (Y) (short,Y) [short] ([short],X) ([short],Y) cy 3 3 4 5 5 6 6 7 7 8 8 lgth 1 1 2 2 1 2 2 3 3 3 3 90 90 92 92 91 90 Op-Code(s) 43 53 53 33 73 63 73 63 33 63 63 XX XX XX XX XX XX See Also: NEG, XOR, AND, OR 46/96 46 ST7 INSTRUCTION SET DEC Syntax Operation Description dec dst <= dst - 1 dst Decrement e.g.: dec Y DEC The destination byte is read, then decremented by one, and the result is written at the destination byte. The destination is either a memory byte or a register. This instruction is compact, and does not affect any register when used with RAM variables. Instruction Overview mnem DEC DEC dst Mem Reg Condition Flags H I N N N Z Z Z C Detailed description dst A X Y short (X) (short,X) (Y) (short,Y) [short] ([short],X) ([short],Y) cy 3 3 4 5 5 6 6 7 7 8 8 lgth 1 1 2 2 1 2 2 3 3 3 3 90 90 92 92 91 90 Op-Code(s) 4A 5A 5A 3A 7A 6A 7A 6A 3A 6A 6A XX XX XX XX XX XX See Also: INC 47/96 47 ST7 INSTRUCTION SET HALT Syntax Operation Description HALT HALT Oscillator (CPU + Peripherals) HALT I = 0, The Oscillator is stopped till an interrupt occur. The interrupt mask is reset, allowing interrupts to be fetched. Then the Oscillator is stopped thus stopping the CPU and all internal peripherals, reducing the microcontroller to its lowest possible power consumption. The micro will continue the program upon an external interrupt, by restarting the oscillator (with 4096 clock cycles delay), and then, fetching the corresponding external interrupt, which is generally either an I/O interrupt or an external Reset. Instruction Overview mnem HALT Condition Flags H I 0 N Z C Detailed Description cy 2 lgth 1 8E Op-Code(s) See Also: WFI 48/96 48 ST7 INSTRUCTION SET INC Syntax Operation Description inc dst <= dst + 1 dst Increment e.g.: inc counter INC The destination byte is read, then incremented by one, and the result is written at the destination byte. The destination is either a memory byte or a register.This instruction is compact, and does not affect any register when used with RAM variables. Instruction Overview mnem INC INC dst Mem Reg Condition Flags H I N N N Z Z Z C Detailed Description dst A X Y short (X) (short,X) (Y) (short,Y) [short] ([short],X) ([short],Y) cy 3 3 4 5 5 6 6 7 7 8 8 lgth 1 1 2 2 1 2 2 3 3 3 3 90 90 92 92 91 90 Op-Code(s) 4C 5C 5C 3C 7C 6C 7C 6C 3C 6C 6C XX XX XX XX XX XX See Also: DEC 49/96 49 ST7 INSTRUCTION SET IRET Syntax Operation IRET CC A X MSB (PC) LSB (PC) Interrupt Return IRET = = = = = (++SP) (++SP) (++SP) (++SP) (++SP) Description Placed at the end of an interrupt routine, return to the original program context before the interrupt occurred. All registers which have been saved/pushed onto the stack (Y excepted) are restored/popped. Instruction Overview mnem IRET Condition Flags H H I I N N Z Z C C X: Detailed Description cy 9 lgth 1 Condition Flags set or reset according to the first byte pulled from the stack Op-Code(s) 80 See Also: Interrupts, TRAP 50/96 50 ST7 INSTRUCTION SET JP Syntax Operation Description jp PC <= dst dst Jump (absolute) e.g.: jp test JP The unconditional jump simply replaces the content of PC by dst. Control then passes to the statement addressed by the program counter. This instruction should be used instead of JRA during S/W development. Instruction Overview mnem JP dst Mem Condition Flags H I N Z C Detailed Description dst short long (X) (short,X) (long,X) (Y) (short,Y) (long,Y) [short] [long.w] ([short],X) ([long.w],X) ([short],Y) ([long.w],Y) cy 2 3 2 3 4 3 4 5 4 5 5 6 5 6 lgth 2 3 1 2 3 2 3 4 3 3 3 3 3 3 90 90 90 92 92 92 92 91 91 Op-Code(s) BC CC FC EC DC FC EC DC BC CC EC DC EC DC XX MS XX XX XX XX XX XX LS XX MS LS XX MS LS See Also: JRA 51/96 51 ST7 INSTRUCTION SET JRA Syntax Operation Description jra PC <= PC + dst Jump Relative Always dst e.g.: jra loop JRA Unconditional relative jump. PC is updated by the signed addition of PC and dst. Control then passes to the statement addressed by the program counter. This instruction may be used, once the S/W debugged to fasten and shrink a program. Instruction Overview mnem JRA dst Mem Condition Flags H I N Z C Detailed Description dst rel [rel] cy 3 5 lgth 2 3 92 Op-Code(s) 20 20 XX XX See Also: JP 52/96 52 ST7 INSTRUCTION SET JRxx Syntax Operation Description jrxx Conditional Jump Relative Instruction dst e.g.: jrxx loop JRxx PC <= PC + dst if Condition is True Conditional relative jump. PC is updated by the signed addition of PC and dst if the condition is true. Control then passes to the statement addressed by the program counter. Else, the program continues normally. Instruction Overview mnem JRxx dst Mem Condition Flags H I N Z C Instruction List mnem JRC JREQ JRF JRH JRIH JRIL JRM JRMI JRNC JRNE JRNH JRNM JRPL JRT JRUGE JRUGT JRULE JRULT Carry Equal False Half-Carry Interrupt Line is High Interrupt Line is Low Interrupt Mask Minus Not Carry Not Equal Not Half-Carry Not Interrupt Mask Plus True Unsigned Greater or Equal Unsigned Greater Then Unsigned Lower or Equal Unsigned Lower Than >= > <= < >= 0 <> 0 <0 I=1 N=1 C=0 Z=0 H=0 I=0 N=0 True C=0 (C or Z) = 0 (C or Z) = 1 C=1 = meaning sym Conditio n C=1 Z=1 False H=1 Op-Code (OC) 25 27 21 29 2F 2E 2D 2B 24 26 28 2C 2A 20 24 22 23 25 Detailed Description dst rel [rel] cy 3 5 lgth 2 3 92 Op-Cod e(s) OC OC XX XX 53/96 53 ST7 INSTRUCTION SET LD Syntax Operation Description Instruction Overview mnem LD LD LD LD LD dst reg mem reg S reg Load ld dst <= src Load the destination byte with the source byte. dst,src e.g.: ld A,#$15 LD src mem reg reg reg S Condition Flags H I N N N Z Z Z C Detailed Description dst A A A A A A A A A A A A A A A #byte short long (X) (short,X) (long,X) (Y) (short,Y) (long,Y) [short] [long.w] ([short],X) ([long.w],X) ([short],Y) ([long.w],Y) src cy 2 3 4 3 4 5 4 5 6 5 6 6 7 6 7 lgth 2 2 3 1 2 3 2 3 4 3 3 3 3 3 3 90 90 90 92 92 92 92 91 91 Op-Cod e(s) A6 B6 C6 F6 E6 D6 F6 E6 D6 B6 C6 E6 D6 E6 D6 XX MS XX XX XX XX XX XX LS XX MS LS XX XX MS LS 54/96 54 ST7 INSTRUCTION SET LD Detailed Description (Cont'd) dst short long (X) (short,X) (long,X) (Y) (short,Y) (long,Y) [short] [long.w] ([short],X) ([long.w],X) ([short],Y) ([long.w],Y) src A A A A A A A A A A A A A A cy 4 5 4 5 6 5 6 7 6 7 7 8 7 8 lgth 2 3 1 2 3 2 3 4 3 3 3 3 3 3 90 90 90 92 92 92 92 91 91 Op-Code(s) B7 C7 F7 E7 D7 F7 E7 D7 B7 C7 E7 D7 E7 D7 XX MS XX XX XX XX XX XX LS XX MS LS XX MS LS dst X X X X X X X X X X #byte short long (X) src cy 2 3 4 3 4 5 5 6 6 7 lgth 2 2 3 1 2 3 3 3 3 3 92 92 92 92 Op-Code(s) AE BE CE FE EE DE BE CE EE DE XX MS XX XX XX XX LS XX XX MS LS (short,X) (long,X) [short] [long.w] ([short],X) ([long.w],X) dst short long (X) (short,X) (long,X) [short] [long.w] ([short],X) ([long.w],X) src X X X X X X X X X cy 4 5 4 5 6 6 7 7 8 lgth 2 3 1 2 3 3 3 3 3 92 92 92 92 Op-Cod e(s) BF CF FF EF DF BF CF EF DF XX MS XX XX XX XX LS XX MS LS 55/96 55 ST7 INSTRUCTION SET LD Detailed Description (Cont'd) dst Y Y Y Y Y Y Y Y Y Y #byte short long (Y) (short,Y) (long,Y) [short] [long.w] ([short],Y) ([long.w],Y) src cy 3 4 5 4 5 6 5 6 6 7 lgth 3 3 4 2 3 4 3 3 3 3 90 90 90 90 90 90 91 91 91 91 Op-Code(s) AE BE CE FE EE DE BE CE EE DE XX MS XX XX XX XX LS XX XX MS LS dst short long (Y) (short,Y) (long,Y) [short] [long.w] ([short],Y) ([long.w],Y) src Y Y Y Y Y Y Y Y Y cy 5 6 5 6 7 6 7 7 8 lgth 3 4 2 3 4 3 3 3 3 90 90 90 90 90 91 91 91 91 Op-Code(s) BF CF FF EF DF BF CF EF DF XX MS XX XX XX XX LS XX MS LS dst X A Y A Y X A S X S Y S src A X A Y X Y S A S X S Y cy 2 2 3 3 3 2 2 2 2 2 3 3 lgth 1 1 2 2 2 1 1 1 1 1 2 2 90 90 90 90 90 Op-Code(s) 97 9F 97 9F 93 93 9E 95 96 94 96 94 See Also: CLR 56/96 56 ST7 INSTRUCTION SET MUL Syntax Operation Description Instruction Overview mnem MUL MUL Multiply (unsigned) mul dst,src e.g.: mul X,A MUL dst:src <= dst x src The source byte, is multiplied (unsigned), with the destination byte. The 16 bit MSB word result is saved in dst location, and the LSB one in src location. dst X:A Y:A src X, A Y, A Condition Flags H 0 0 I N Z C 0 0 Detailed Description dst X Y src A A cy 11 12 lgth 1 2 90 Op-Code(s) 42 42 See Also: ADD, ADC, SUB, SBC 57/96 57 ST7 INSTRUCTION SET NEG Syntax Operation Description neg Negate (Logical 2-Complement) dst e.g.: neg (X) NEG dst <= (dst XOR FF) + 1, or 00 - dst The destination byte is read, then each bit is toggled (inverted), and the result is incremented before it is written at the destination byte. The destination is either a memory byte or a register. The Carry is cleared if the result is zero. This instruction is used to negate signed values. This instruction is compact, and does not affect any register when used with RAM variables. Instruction Overview mnem NEG NEG dst Mem Reg Condition Flags H I N N N Z Z Z C C C Detailed Description dst A X Y short (X) (short,X) (Y) (short,Y) [short] ([short],X) ([short],Y) cy 3 3 4 5 5 6 6 7 7 8 8 lgth 1 1 2 2 1 2 2 3 3 3 3 90 90 92 92 91 90 Op-Code(s) 40 50 50 30 70 60 70 60 30 60 60 XX XX XX XX XX XX See Also: CPL, AND, OR, XOR 58/96 58 ST7 INSTRUCTION SET NOP Syntax Operation Description Instruction Overview mnem NOP No operation nop NOP Does nothing. This instruction can be used either to disable an instruction, or to build a waiting delay. Condition Flag H I N Z C Detailed Description cy 2 lgth 1 Op-Code(s) 9D See Also: JRF 59/96 59 ST7 INSTRUCTION SET OR Syntax Operation Description or dst,src dst <= dst OR src Logical OR e.g.: or A,#%00110101 OR The source byte, is ORed with the destination byte and the result is stored in the destination byte. The source is a memory byte, and the destination is the Accumulator register. Truth Table OR 0 1 0 0 1 1 1 1 Instruction Overview mnem OR dst A src Mem Condition Flags H I N N Z Z C Detailed Description dst A A A A A A A A A A A A A A A #byte short long (X) (short,X) (long,X) (Y) (short,Y) (long,Y) [short] [long.w] ([short],X) ([long.w],X) ([short],Y) ([long.w],Y) src cy 2 3 4 3 4 5 4 5 6 5 6 6 7 6 7 lgth 2 2 3 1 2 3 2 3 4 3 3 3 3 3 3 90 90 90 92 92 92 92 91 91 Op-Code(s) AA BA CA FA EA DA FA EA DA BA CA EA DA EA DA XX MS XX XX XX XX XX XX LS XX MS LS XX XX MS LS See Also: AND, XOR, CPL, NEG 60/96 60 ST7 INSTRUCTION SET POP Syntax Operation Description Instruction Overview mnem POP POP POP POP Pop from Stack pop dst e.g.: pop CC POP dst <= (++SP) Restore from the stack a data byte which will be placed in dst location. The stack pointer is incremented by one. Use to restore a register value. dst A X Y CC Condition Flag H I N Z C H I N Z C X: Detailed Description dst A X Y CC Load Condition Flag from the stack cy 4 4 5 4 lgth 1 1 2 1 90 Op-Cod e(s) 84 85 85 86 See Also: PUSH, RSP 61/96 61 ST7 INSTRUCTION SET PUSH Syntax Operation Description Instruction Overview mnem PUSH PUSH PUSH PUSH Push into the Stack push (SP--) <= dst src e.g.: push A PUSH Save into the stack the dst byte location. The stack pointer is decremented by one. Used to save a register value. dst A X Y CC Condition Flag H I N Z C Detailed Description dst A X Y CC cy 3 3 4 3 lgth 1 1 2 1 90 Op-Code(s) 88 89 89 8A See Also: POP, RSP 62/96 62 ST7 INSTRUCTION SET RCF Syntax Operation Description Instruction Overview mnem RCF Reset Carry Flag rcf C=0 RCF Clear the carry flag of the CC register. May be used as a boolean used controlled flags. Condition Flags H I N Z C 0 Detailed Description cy 2 lgth 1 Op-Code(s) 98 See Also: SCF 63/96 63 ST7 INSTRUCTION SET RET Syntax Operation Description Instruction Overview mnem RET Return from subroutine ret MSB (PC) = (++SP) LSB (PC) = (++SP) RET Restore the PC from the stack. The stack pointer is incremented twice.This instruction is the last one of a subroutine. Condition Flags H I N Z C Detailed Description cy 6 lgth 1 Op-Code(s) 81 See Also: CALL, CALLR 64/96 64 ST7 INSTRUCTION SET RIM Syntax Operation Description rim I=0 Reset Interrupt Mask/Enable Interrupt RIM Clear the Interrupt mask of the CC register, which enable interrupts. This instruction is generally put in the main program, after the reset routine, once all desired interrupts have been properly configured. This instruction is not needed before both WFI and HALT instructions. Instruction Overview mnem RIM Condition Flags H I 0 N Z C Detailed Description cy 2 lgth 1 Op-Code(s) 9A See Also: SIM 65/96 65 ST7 INSTRUCTION SET RLC Syntax Operation Description Instruction Overview RLC RLC RLC Rotate Left Logical through Carry rlc dst e.g.: rlc (X) RLC The destination is either a memory byte or a register. This instruction is compact, and does not affect any register when used with RAM variables. Mem Reg Mem Condition Flag H I N N N Z Z Z C bit 7 bit 7 C 7 0 Detailed Description dst A X Y short (X) (short,X) (Y) (short,Y) [short] ([short],X) ([short],Y) cy 3 3 4 5 5 6 6 7 7 8 8 lgth 1 1 2 2 1 2 2 3 3 3 3 90 90 92 92 91 90 Op-Code(s) 49 59 59 39 79 69 79 69 39 69 69 XX XX XX XX XX XX See Also: RRC, SLL, SRL, SRA, ADC, SWAP, SLA 66/96 66 ST7 INSTRUCTION SET RRC Syntax Operation Description Instruction Overview rrc Rotate Right Logical through Carry dst e.g.: rrc (X) RRC The destination is either a memory byte location or a register. This instruction is compact, and does not affect any register when used with RAM variables. mnem RRC RRC dst Mem Reg Condition Flag H I N N N Z Z Z C bit 0 bit 0 C 7 0 Detailed Description dst A X Y short (X) (short,X) (Y) (short,Y) [short] ([short],X) ([short],Y) cy 3 3 4 5 5 6 6 7 7 8 8 lgth 1 1 2 2 1 2 2 3 3 3 3 90 90 92 92 91 90 Op-Code(s) 46 56 56 36 76 66 76 66 36 66 66 XX XX XX XX XX XX See Also: RLC, SRL, SLL, SRA, SWAP, ADC, SLA 67/96 67 ST7 INSTRUCTION SET RSP Syntax Operation Description Trick Instruction Overview mnem RSP Reset Stack Pointer rsp SP = Reset Value RSP Reset the stack pointer to its reset initial value.This instruction may be put as first executed instruction in the reset routine. It may be used to test current stack size used with an ST7 independent program. Condition Flags H I N Z C Detailed Description cy 2 lgth 1 Op-Cod e(s) 9C See Also: PUSH, POP 68/96 68 ST7 INSTRUCTION SET SBC Syntax Operation Description sbc Substraction with Carry dst,src e.g.: sbc A,#$15 SBC dst <= dst - src - C The source byte, along with the carry flag, is subtracted from the destination byte and the result is stored in the destination byte. The source is a memory byte, and the destination is the A register. Instruction Overview mnem SBC dst A src Mem Condition Flags H I N N Z Z C C Detailed Description dst A A A A A A A A A A A A A A A #byte short long (X) (short,X) (long,X) (Y) (short,Y) (long,Y) [short] [long.w] ([short],X) ([long.w],X) ([short],Y) ([long.w],Y) src cy 2 3 4 3 4 5 4 5 6 5 6 6 7 6 7 lgth 2 2 3 1 2 3 2 3 4 3 3 3 3 3 3 90 90 90 92 92 92 92 91 91 Op-Code(s) A2 B2 C2 F2 E2 D2 F2 E2 D2 B2 C2 E2 D2 E2 D2 XX MS XX XX XX XX XX XX LS XX MS LS XX XX MS LS See Also: ADD,SUB,SBC, MUL 69/96 69 ST7 INSTRUCTION SET SCF Syntax Operation Description Instruction Overview mnem SCF Set Carry Flag scf C=1 SCF Set the carry flag of the CC register. It may be used as user controlled flag. Condition Flags H I N Z C 1 Detailed Description cy 2 lgth 1 Op-Code(s) 99 See Also: RCF 70/96 70 ST7 INSTRUCTION SET SIM Syntax Operation Description Instruction Overview sim I=1 Set Interrupt Mask/Disable Interrupt SIM Set the Interrupt mask of the CC register, which disables interrupts. This instruction is useless at the beginning of an interrupt/reset routine mnem SIM Condition Flags H I 1 N Z C Detailed Description cy 2 lgth 1 Op-Code(s) 9B See Also: RIM 71/96 71 ST7 INSTRUCTION SET SLA Syntax Operation Description Instruction Overview mnem SLA SLA Shift Left Arithmetic sla dst e.g.: sla (X) SLA The destination is either a memory byte or a register.This instruction is equivalent to SLL one. dst Mem Reg Condition Flags H I N N N Z Z Z C bit 7 bit 7 C 7 0 0 Detailed Description dst A X Y short (X) (short,X) (Y) (short,Y) [short] ([short],X) ([short],Y) cy 3 3 4 5 5 6 6 7 7 8 8 lgth 1 1 2 2 1 2 2 3 3 3 3 90 90 92 92 91 90 Op-Code(s) 48 58 58 38 78 68 78 68 38 68 68 XX XX XX XX XX XX See Also: SRL, SRA, RRC, RLC, SWAP, SLL 72/96 72 ST7 INSTRUCTION SET SLL Syntax Operation Description sll Shift Left Logical dst e.g.: sll (X) SLL The destination is either a memory byte or a register.It double the affected value. This instruction is compact, and does not affect any register when used with RAM variables. Instruction Overview mnem SLL SLL dst Mem Reg Condition Flags H I N N N Z Z Z C bit 7 bit 7 C 7 0 0 Detailed Description dst A X Y short (X) (short,X) (Y) (short,Y) [short] ([short],X) ([short],Y) cy 3 3 4 5 5 6 6 7 7 8 8 lgth 1 1 2 2 1 2 2 3 3 3 3 90 90 92 92 91 90 Op-Code(s) 48 58 58 38 78 68 78 68 38 68 68 XX XX XX XX XX XX See Also: SLA, SRA, SRL, RRC, RLC, SWAP 73/96 73 ST7 INSTRUCTION SET SRA Syntax Operation Description sra Shift Right Arithmetic dst e.g.: sra (X) SRA The destination is either a memory byte or a register.It perform an signed division by 2: The sign bit 7 is not modified.This instruction is compact, and does not affect any register when used with RAM variables. Instruction Overview mnem SRA SRA dst Mem Reg Condition Flags H I N N N Z Z Z C bit 0 bit 0 7 0 C Detailed Description dst A X Y short (X) (short,X) (Y) (short,Y) [short] ([short],X) ([short],Y) cy 3 3 4 5 5 6 6 7 7 8 8 lgth 1 1 2 2 1 2 2 3 3 3 3 90 90 92 92 91 90 Op-Cod e(s) 47 57 57 37 77 67 77 67 37 67 67 XX XX XX XX XX XX See Also: SRL, SLL, RRC, RLC, SWAP 74/96 74 ST7 INSTRUCTION SET SRL Syntax Operation Description srl dst Shift Right Logical e.g.: srl (X) SRL The destination is either a memory byte or a register.It perform an unsigned division by 2.This instruction is compact, and does not affect any register when used with RAM variables. Instruction Overview mnem SRL SRL dst Mem Reg Condition Flags H I N 0 0 Z Z Z C bit 0 bit 0 0 7 0 C Detailed Description dst A X Y short (X) (short,X) (Y) (short,Y) [short] ([short],X) ([short],Y) cy 3 3 4 5 5 6 6 7 7 8 8 lgth 1 1 2 2 1 2 2 3 3 3 3 90 90 92 92 91 90 Op-Code(s) 44 54 54 34 74 64 74 64 34 64 64 XX XX XX XX XX XX See Also: RLC, RRC, SRL, SRA, SWAP, SLL 75/96 75 ST7 INSTRUCTION SET SUB Syntax Operation Description sub dst,src dst <= dst - src Substraction e.g.: sub A,#%11001010 SUB The source byte is subtracted from the destination byte and the result is stored in the destination byte. The source is a memory byte, and the destination is the A register. Instruction Overview mnem SUB dst A src Mem Condition Flags H I N N Z Z C C Detailed Description dst A A A A A A A A A A A A A A A #byte short long (X) (short,X) (long,X) (Y) (short,Y) (long,Y) [short] [long.w] ([short],X) ([long.w],X) ([short],Y) ([long.w],Y) src cy 2 3 4 3 4 5 4 5 6 5 6 6 7 6 7 lgth 2 2 3 1 2 3 2 3 4 3 3 3 3 3 3 90 90 90 92 92 92 92 91 91 Op-Code(s) A0 B0 C0 F0 E0 D0 F0 E0 D0 B0 C0 E0 D0 E0 D0 XX MS XX XX XX XX XX XX LS XX MS LS XX XX MS LS See Also: ADD, ADC, SBC, MUL 76/96 76 ST7 INSTRUCTION SET SWAP Syntax Operation Description swap dst Swap nibbles e.g.: swap counter SWAP The destination byte upper and low nibbles are swapped over. The destination is either a memory byte or a register.This instruction is compact, and does not affect any register when used with RAM variables. Instruction Overview mnem SWAP SWAP dst Mem Reg Condition Flags H I N N N Z Z Z C Detailed Description dst A X Y short (X) (short,X) (Y) (short,Y) [short] ([short],X) ([short],Y) cy 3 3 4 5 5 6 6 7 7 8 8 lgth 1 1 2 2 1 2 2 3 3 3 3 90 90 92 92 91 90 Op-Code(s) 4E 5E 5E 3E 7E 6E 7E 6E 3E 6E 6E XX XX XX XX XX XX See Also: RRC, RLC, SLL, SRL, SRA 77/96 77 ST7 INSTRUCTION SET TNZ Syntax Operation Description tnz Test for Negative or Zero dst e.g.: tnz A TNZ {N, Z} = Test(dst) The destination byte is tested and both N and Z flags are updated accordingly.This instruction is compact, and does not affect any register when used with RAM variables. Instruction Overview mnem TNZ TNZ dst Mem Reg Condition Flags H I N N N Z Z Z C Detailed Description dst A X Y short (X) (short,X) (Y) (short,Y) [short] ([short],X) ([short],Y) cy 3 3 4 4 4 5 5 6 6 7 7 lgth 1 1 2 2 1 2 2 3 3 3 3 90 90 92 92 91 90 Op-Cod e(s) 4D 5D 5D 3D 7D 6D 7D 6D 3D 6D 6D XX XX XX XX XX XX See Also: CP, BCP 78/96 78 ST7 INSTRUCTION SET TRAP Syntax Operation TRAP Software Interrupt TRAP PC = PC + 1 (SP--) = LSB (PC) (SP--) = MSB (PC) (SP--) = X (SP--) = A (SP--) = CC PC = Vector Contents Description When processed, this instruction force the trap interrupt to occur and to be processed. It cannot be masked by I flag. Instruction Overview mnem TRAP Condition Flags H I 1 N Z C Detailed Description cy 10 lgth 1 Op-Code(s) 83 See Also: IRET 79/96 79 ST7 INSTRUCTION SET WFI Syntax Operation Description Wait for Interrupt (CPU Stopped, Low Power Mode) WFI WFI I = 0, The CPU Clock is stopped till an interrupt occur. Internal Peripheral are still running. The interrupt flag is cleared, allowing interrupts to be fetched. Then the CPU clock is stopped, reducing the microcontroller to a lower power consumption. The micro will continue the program upon an internal or external interrupt. Instruction Overview mnem WFI Condition Flags H I 0 N Z C Detailed Description cy 2 lgth 1 Op-Code(s) 8F See Also: HALT 80/96 80 ST7 INSTRUCTION SET XOR Syntax Operation Description xor Logical Exclusive OR dst,src e.g.: xor A,#%00110101 XOR dst <= dst XOR src The source byte, is XORed with the destination byte and the result is stored in the destination byte. The source is a memory byte, and the destination is the A register. Truth Table XOR 0 1 0 0 1 1 1 0 Instruction Overview mnem XOR dst A src Mem Condition Flags H I N N Z Z C Detailed Description dst A A A A A A A A A A A A A A A #byte short long (X) (short,X) (long,X) (Y) (short,Y) (long,Y) [short] [long.w] ([short],X) ([long.w],X) ([short],Y) ([long.w],Y) src cy 2 3 4 3 4 5 4 5 6 5 6 6 7 6 7 lgth 2 2 3 1 2 3 2 3 4 3 3 3 3 3 3 90 90 90 92 92 92 92 91 91 Op-Code(s) A8 B8 C8 F8 E8 D8 F8 E8 D8 B8 C8 E8 D8 E8 D8 XX MS XX XX XX XX XX XX LS XX MS LS XX XX MS LS See Also: AND, OR, CPL, NEG 81/96 81 SOFTWARE Library 5 SOFTWARE Library In order to simplify and hasten the development of any ST7 application, many useful standard routines are shown in this chapter. They are general purpose ones, since they do not interact with any H/W cell. These routines are split in 8 main groups: Table of Contents: 5.1 Tips: How How How How 5.2 5.3 5.4 5.5 5.6 5.7 to increment A up to XX? to decrement A down to XX? to convert A, (hex. value between $00 (0) and $63 (99)) to decimal? to deduce a parity bit of X content value? (returned in C) Dynamic Bit Set/Reset Implementation of jump call vector tables Unsigned Word Multiplication Unsigned Long Word by Word Division Min./Max. Check Range Check 82/96 82 SOFTWARE Library 5.1 TIPS GENERAL TRICKS Trick 1:How to increment A up to XX? clr A ; A=00h. loop1 cp A,#18 ; 18 is our example, you can take #XX. jreq exit1 ; when A=#18, exit. adc A,#0 ; The advantage to use adc and not add (add A,#1) is jrnc loop1 ; that when A=#18, C=0 and A keeps the good value. ; The instruction jra is also possible. exit 1 Trick 2: How to decrement A down to XX? ld A,#$FF ; A is put at FF to be greater than #XX loop2 cp A,#$A5 ; A5 is here our example, you can take any value #XX. jreq exit2 ; When A=#$A5, exit. adc A,#$FF jrc loop2 ; The instruction jra is also possible. exit 2 Trick 3: How to convert A, hexa value between $00 (0) and $63 (99) in decimal? clr dec_nbr ; dec_nbr is the variable used to store the decimal number temp sub A,#10 ; each nibbles represent 2 decimal digits 0..9,0..9 jrc unit inc dec_nbr jra temp unit add A,#10 ; We add 10 because we substracted it one more time. swap dec_nbr ; We put the number of tens in the MSB part. OR A,dec_nbr ; A contains the rest, we add it with tens. Trick 4: How to deduce a parity bit of X content value? (returned in C) ld Y,#8 ; Number of bits to shift. clr A loop srl X ; Unsigned division of X by 2 adc A,#0 ; A is equal to the number of 1 in X. dec Y jrne loop ; Continue until Y=0. srl A ; IfCarry=1, X not even; if Carry=0, Xeven. 83/96 83 SOFTWARE Library 5.2 DBSET/DBRES, Dynamic Bit Set/Reset Inputs: reg reg XThe byte address to manipulate AThe bit position Action: Output: Set or Reset the bit number A (0..7) at byte address X No register modified Variable definition: WORDS segment 'rom' bittbl dc.b $01,$02,$04,$08,$10,$20,$40,$80 Program Listing: WORDS segment 'rom' ; Dynamic Bit set .dbset push CC push A and A,#$07 ld Y,A ld A,(bittbl,Y) or A,(X) ld (X),A pop A pop CC ret ; Dynamic bit reset .dbres push CC push A and A,#$07 ld Y,A ld A,(bittbl,Y) cpl A and A,(X) ld (X),A pop A pop CC ret ; Push CC into the stack to save its value. ; Push A into the stack to save its value. ; To have a bit number between 0 and 7. ; Point on the corresponding mask. ; Put the result at X address. ; Restore A from the stack. ; Restore CC from the stack. 84/96 84 SOFTWARE Library 5.3 JMPCALLTBL, Implementation of jump/call vector tables Inputs: X ptr BYTEThe selected function (1) WORDVector table address (1)X = 00..7FJump Function[X] X = 80..FFCall Function[X] Action:Implement a function array (smallest and fastest way) Variable definition: WORDS segment 'rom' .ptr DC.W fn0,fn1,fn2,null,fn4 .fn0 inc X ret .fn1 srl X ret .fn2 sll X ret .fn4 dec X ret .null ret Program Listing JPCALLFNX sll jrnc call nop ret jump ld push ld push ret A,({ptr+1},X) ; Load of the address of the function A ; to execute in A. A,(ptr,X) A X jump jump ; If no overflow by shifting left X, jump. 85/96 85 SOFTWARE Library 5.4 Unsigned Word Multiplication ; Multiplication A * B ; ; DATE : 21/11/96 ; REVISION : V01.00 ; ; SOFTWARE DESCRIPTION : This routine multiplies two 16 bit numbers ; A and B, the result is saved into four 8 bits ; registers (16x16= 32 bits) ; A and B >= 0. ; ; INPUT PARAMETERS : OPERAND_A registers contain the number A. ; OPERAND_B registers contain the number B. ; ; ; ; OUTPUT PARAMETERS : res registers contain the result. ; ;BYTE : 63 bytes ; ;EXAMPLE : ;***** program ***** ; ld A,#$F3 ; ld operand_a,A ; ld A,#$D3 ; ld {operand_a+1},A ; ld A,#$FC ; ld operand_b,A ; ld A,#$C3 ; ld {operand_b+1},A ; CALL multiw ; - do... ; - do... ; ;***** subroutine ***** ; . multiw ; END ; 86/96 86 SOFTWARE Library .multiw push A push X ; save Accumulator in stack ; save X register in stack ld X,operand_b ;\ ld A,operand_a ; | Multiplies MSB operand mul X,A ; / ld res,X ;and store in the 2 MSB result registers ld {res+1},A ld X,{operand_a+1} ;\ ld A,{operand_b+1} ; | Multiplies LSB operand mul X,A ;/ ld {res+2},X ; and store in the 2 LSB result registers ld {res+3},A ld X,operand_a ;\ ld A,{operand_b+1} ; | Multiplies cross operands mul X,A ;/ add A,{res+2} ; Add to previous result ld {res+2},A ld A,X adc A,{res+1} ld {res+1},A ld A,res adc A,#0 ld res,A ld X,operand_b ;\ ld A,{operand_a+1} ; | Multiplies cross operands mul X,A ;/ add A,{res+2} ; Add to previous result ld {res+2},A ld A,X adc A,{res+1} ld {res+1},A ld A,res adc A,#0 ld res,A pop X ; restore context before the CALL pop A ; restore context before the CALL ret ; and go back to main program 87/96 87 SOFTWARE Library 5.5 Unsigned Long Word by Word Division ; Long by Word division A/B ; DATE : 22/11/96 ; REVISION : V01.00 ; ; SOFTWARE DESCRIPTION : This routine divides one 32 bits number A by ; a 16-bit number B. The result is saved in two ; registers. ; A and B >= 0. ; ; INPUT PARAMETERS : DIVIDEND registers contain the DIVIDEND (32 b). ; DIVISOR registers contain the DIVISOR (16 b). ; ; INTERNAL PARAMETERS : TEMPQUOT registers contain the QUOTIENT ; temporary value (32 b). ; ; OUTPUT PARAMETERS : QUOTIENT registers contain the result (16 b). ; As the result is not stored on 32 bits, this ; division is not valid in the general case. ; ; BYTE : 94 bytes ; ; EXAMPLE : ;***** program ***** ; ld A,#$0E ; ld dividend,A ; ld A,#$DC ; ld {dividend+1},A ; ld A,#$BA ; ld {dividend+2},A ; ld A,#$98 ; ld {dividend+3},A ; ld A,#$AB ; ld divisor,A ; ld A,#$CD ; ld {divisor+1},A ; CALL div_lxw ; - do... ; - do... ; ;***** subroutine ***** ; . div_lxw ; END 88/96 88 SOFTWARE Library .div_lxw push A push X ld ld ld ld ld ld ld ld .execute sla {dividend+3} ;Shift left dividend with 32 leading Zeros rlc {dividend+2} rlc {dividend+1} rlc dividend rlc {tempquot+3} rlc {tempquot+2} rlc {tempquot+1} rlc tempquot sla {quotient+1} ; The result cannot be greater than 16 bits rlc quotient ; so we can shift left the quotient ld A,tempquot ; Test is left dividend is greater or equal or A,{tempquot+1} ; to the divisor jrne dividendlsgreater ld A,{tempquot+2} cp A,divisor jrugt dividendlsgreater jrult nosubstract ld A,{tempquot+3} cp A,{divisor+1} jrult nosubstract .dividendlsgreater ; Subtract divisor from left dividend ld A,{tempquot+3} sub A,{divisor+1} ld {tempquot+3},A ; save Accumulator in stack ; save X register in stack X,#32 ; Initialization process A,#0 ; We use the load instruction quotient,A ; which is faster than the {quotient+1},A ; clear instruction for tempquot,A ; multiple short datas. {tempquot+1},A ; For a smaller code size {tempquot+2},A ; you'd better use the clear {tempquot+3},A ; instruction 89/96 89 SOFTWARE Library ld A,{tempquot+2} sbc A,divisor ld {tempquot+2},A ld A,{tempquot+1} sbc A,#0 ld {tempquot+1},A ld A,tempquot sbc A,#0 ld tempquot,A inc {quotient+1} jrne nosubstract inc quotient .nosubtract dec X ; Decrement loop counter jrne execute ; if X = 0 then exit else continue pop X pop A ret ; restore context before the CALL ; restore context before the CALL ; and go back to main program ; The result cannot be greater than 16 bits ; so we can increment the quotient 90/96 90 SOFTWARE Library 5.6 Min./Max. Check ; CHECK MIN / MAX ; ; DATE : 22/11/96 ; REVISION : V01.00 ; ; SOFTWARE DESCRIPTION : This routine tests if a 16 bit numbers value ; is within a predefined range. ; ; MIN =< DATA =< MAX ; ; INPUT PARAMETERS : DATA registers contain the number to test. ; MIN registers contain the minimum value. ; MAX registers contain the maximum value. ;[ ; OUTPUT PARAMETERS : The C flag is updated according to the result. ; C=1 means that the test has failed. ; ; BYTE : 32 bytes ; ; EXAMPLE : ;***** program ***** ; ld A,#$25 ; ld data,A ; ld A,#$00 ; ld {data+1},A ; ld A,#$00 ; ld min,A ; ld A,#$C3 ; ld {min+1},A ; ld A,#$CC ; ld max,A ; ld A,#$05 ; ld {max+1},A ; CALL check_min_max ; - do... ; - do... ; ;***** subroutine ***** ; .check_min_max ; END 91/96 91 SOFTWARE Library .check_min_max push A ; save Accumulator in stack push X ; save X register in stack ld X,data ; get DATA MSB in X ld A,{data+1} ; get DATA LSB in A cp X,max ; Compare MSB with MAX jrugt out_of_range ; if greater than exit jrne comp_min ; else if equals compare LSB cp A,{max+1} jrugt out_of_range ; LSB greater than exit comp_min cp X,min ; same thing with the LSB and the min value jrult out_of_range jrne in_range cp A,{min+1} jrult out_of_range in_range rcf jra exit out_of_range scf exit pop X pop A ret ; Value in range so reset C flag ; the value is within the two values ; Value out of range so set C flag ; restore context before the CALL ; restore context before the CALL ; and go back to main program 92/96 92 SOFTWARE Library 5.7 Range Check ; CHECK RANGE for a WORD ; DATE : 22/11/96 ; REVISION : V01.00 ; SOFTWARE DESCRIPTION : This routine tests if a 16 bit numbers value ; is within a predefined range ; MEDIAN - DELTA =< DATA =< MEDIAN + DELTA ; INPUT PARAMETERS : DATA registers contain the number to test. ; MEDIAN registers contain the median value. ; DELTA registers contain the delta value to add ; and subtract to the MEDIAN value. ; OUTPUT PARAMETERS : The C flag is updated according to the result. ; C=1 means that the test has failed. ; NOTES: This routine uses three previous sub routines. ; check_min_max ; addw ; subw ; BYTE : 66 bytes ; ; EXAMPLE : ;***** program ***** ; ld A,#$25 ; ld data,A ; ld A,#$00 ; ld {data+1},A ; ld A,#$00 ; ld delta,A ; ld A,#$23 ; ld {delta+1},A ; ld A,#$CC ; ld median,A ; ld A,#$05 ; ld {median+1},A ; CALL check_range ; - do... ; - do... ; ;***** subroutine ***** ; .addw ; .subw ; .check_min_max ; .check_range ; END 93/96 93 SOFTWARE Library .check_range push A ; save Accumulator in stack push X ; save X register in stack ld A,{median+1} ; get median' LSB add A,{delta+1} ; add delta' LSB ld {res_add+1},A ; store LSB ld A,median ; get median' MSB adc A,delta ; add delta' MSB with LSB's carry ld res_add,A ; store MSB jrnc no_ovfmax ld A,#$FF ld max,A ld {max+1},A no_ovfmax ld ld ld ld ; test if an overflow occured ; if yes then the MAX value is set to FFFFh ; (saturation) A,res_add ; else there is no overflow, then max,A ; the computed value is the MAX value to keep. A,{res_add+1} {max+1},A ld A,{median+1} ; get median' LSB sub A,{delta+1} ; sub delta' LSB ld {res_sub+1},A ; store LSB ld A,median ; get median' MSB sbc A,delta ; sub delta' MSB with LSB's carry ld res_sub,A ; store MSB jrnc no_ovfmin ; test if an overflow occured clr A ; if yes then the MIN value is set to 0000h ld min,A ; (saturation) ld {min+1},A 94/96 94 SOFTWARE Library no_ovfmin ld ld ld ld A,res_sub ; else there is no overflow, then min,A ; the computed value is the MIN value to keep. A,{res_sub+1} {min+1},A push A ; save Accumulator in stack push X ; save X register in stack call check_min_max ; Then we check if the value is within the range ; set by max and min. pop A ; restore context before the CALL pop X ; restore context before the CALL ret ; The result depends of the C flag. 95/96 95 SOFTWARE Library "THE PRESENT NOTE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH A NOTE AND/OR THE USE MADE BY CUSTOMERS OF THE INFORMATION CONTAINED HEREIN IN CONNEXION WITH THEIR PRODUCTS." Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c)1999 STMicroelectronics - All Rights Reserved. Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. STMicroelectronics Group of Companies Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www. st.com 96/96 96 |
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