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PIC16C715
In-Circuit Serial Programming (ICSPTM) for PIC16C715 OTP MCUs
This document includes the programming specifications for the following devices:
* PIC16C715
Pin Diagrams
PDIP, SOIC, Windowed CERDIP
1.0
PROGRAMMING THE PIC16C715
RA2/AN2 RA3/AN3/VREF RA4/T0CKI MCLR /V PP VSS RB0/INT RB1 RB2 RB3
*1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
RA1/AN1 RA0/AN0 OSC1/CLKIN OSC2/CLKOUT VDD RB7 RB6 RB5 RB4
PIC16C715
The PIC16C715 can be programmed using a serial method. In serial mode the PIC16C715 can be programmed while in the users system. This allows for increased design flexibility. This programming specification applies to PIC16C715 devices in all packages.
1.1
Hardware Requirements
The PIC16C715 requires two programmable power supplies, one for VDD (2.0V to 6.5V recommended) and one for VPP (12V to 14V). Both supplies should have a minimum resolution of 0.25V.
1.2
Programming Mode
The programming mode for the PIC16C715 allows programming of user program memory, special locations used for ID, and the configuration word for the PIC16C715.
PIN DESCRIPTIONS (DURING PROGRAMMING): PIC16C715
During Programming Pin Name RB6 RB7 MCLR/VPP VDD VSS Pin Name CLOCK DATA VPP VDD VSS Pin Type I I/O P P P Pin Description Clock input Data input/output Programming Power Power Supply Ground
Legend: I = input, O = Output, P = Power
ICSP is a trademark of Microchip Technology Inc.
(c) 1997 Microchip Technology Inc.
DS30278A-page 1
PIC16C715
2.0
2.1
PROGRAM MODE ENTRY
User Program Memory Map
TABLE 2-1:
IMPLEMENTATION OF PROGRAM MEMORY IN THE PIC16C715
Program Memory Size 0x000-0x7FF (2K) Access to Program Memory PC<10:0>
The user memory space extends from 0x0000 to 0x1FFF (8K). Table 2-1 shows actual implementation of program memory in the PIC16C715 family. When the PC reaches the last location of the implemented program memory, it will wrap around and address a location within the physically implemented memory (Figure 2-1). In programming mode the program memory space extends from 0x0000 to 0x3FFF, with the first half (0x0000-0x1FFF) being user program memory and the second half (0x2000-0x3FFF) being configuration memory. The PC will increment from 0x0000 to 0x1FFF and wrap to 0x000 or 0x2000 to 0x3FFF and wrap around to 0x2000 (not to 0x0000). Once in configuration memory, the highest bit of the PC stays a '1', thus always pointing to the configuration memory. The only way to point to user program memory is to reset the part and reenter program/verify mode, as described in Section 2.3. In the configuration memory space, 0x2000-0x20FF are utilized. When in a configuration memory, as in the user memory, the 0x2000-0x20FF segment is repeatedly accessed as PC exceeds 0x20FF (Figure 2-1).
Device PIC16C715
A user may store identification information (ID) in four ID locations. The ID locations are mapped in [0x2000 : 0x2003]. It is recommended that the user use only the six least significant bits of each ID location where the least two significant bits are the parity bits. In some devices, the ID locations read-out in a scrambled fashion after code protection is enabled. For these devices, it is recommended that ID location is written as "11 1111 1000 bbbb pp" where 'bbbb' is ID information. Note: All other locations are reserved and should not be programmed.
In other devices, the ID locations read out normally, even after code protection. To understand how the devices behave, refer to Table 4-1. Note: ID's require parity clocked in/out but not checked.
To understand the scrambling mechanism after code protection, refer to Section 4.1.
FIGURE 2-1:
PROGRAM MEMORY MAPPING
2KW
0000h
Implemented
2000h 2001h 2002h 2003h 2004h 2005h 2006h 2007h
ID Location ID Location ID Location ID Location Reserved Reserved Reserved Configuration Word
03FFh 0400h
Implemented
07FFh 0800h 0BFFh 0C00h 0FFFh 1000h
Reserved
1FFFh
207Fh
Reserved
20FFh 2100h
Reserved Reserved
3FFFh
DS30278A-page 2
(c) 1997 Microchip Technology Inc.
In-Circuit Serial Programming
2.2 Program Memory Parity
The PIC16C715 has on-chip parity bits that can be used to verify the contents of the program memory during runtime. Parity bits may be useful in applications in order to increase overall reliability of the system. Due to the on-chip parity bits the entire program memory word has been enlarged to 16 bits. The user is responsible to generate and program the correct parity for a given program memory word. The two parity bits are computed on alternating bits of the program word. One computation is performed using even parity, the other using odd parity as shown in Figure 2-2.
FIGURE 2-2:
EPROM MEMORY WITH PARITY CHECKING
E 13 12 11
P 10
R 9
O 8
M 7
6
S 5
T 4
I 3
C 2
K 1
S 0 PO PE
ERROR
(c) 1997 Microchip Technology Inc.
DS30278A-page 3
PIC16C715
2.3 Program/Verify Mode
2.3.1 SERIAL PROGRAM/VERIFY OPERATION The program/verify mode is entered by holding pins RB6 and RB7 low while raising MCLR pin from VIL to VIHH (high voltage). Once in this mode the user program memory and the configuration memory can be accessed and programmed in serial fashion. The mode of operation is serial, and the memory that is accessed is the user program memory. RB6 is a Schmitt Trigger input in this mode. The sequence that enters the device into the programming/verify mode places all other logic into the reset state (the MCLR pin was initially at VIL). This means that all I/O are in the reset state (Hi-impedance inputs). Note: The MCLR pin should be raised as quickly as possible from VIL to VIHH. this is to ensure that the device does not have the PC incremented while in valid operation range. The RB6 pin is used as a clock input pin, and the RB7 pin is used for entering command bits and data input/output during serial operation. To input a command, the clock pin (RB6) is cycled 6 times. Each command bit is latched on the falling edge of the clock with the least significant bit (LSB) of the command being input first. The data on pin RB7 is required to have a minimum setup and hold time of 100 ns with respect to the falling edge of the clock. Commands that have data associated with them (read and load) are specified to have a minimum delay of 1 s between the command and the data. After this delay the clock pin is cycled 18 times with the first cycle being a start bit and the last cycle being a stop bit. Data is also input and output LSb first. Therefore, during a read operation the LSb will be transmitted from pin RB7 on the rising edge of the second cycle, and during a load operation the LSb will be latched on the falling edge of the second cycle. A minimum 1 s delay is also specified between consecutive commands. 2.3.2 LOAD CONFIGURATION
After receiving this command, the program counter (PC) will be set to 0x2000. By then applying 18 cycles to the clock pin, the chip will load 16-bits a "data word" as described above, to be programmed into the configuration memory. A description of the memory mapping schemes for normal operation and configuration mode operation is shown in Figure 2-1. After the configuration memory is entered, the only way to get back to the user program memory is to exit the program/verify test mode by taking MCLR low (VIL).
TABLE 2-2:
COMMAND MAPPING (SERIAL OPERATION)
Command Mapping (msb ... lsb) X X X X X X X X X X X X 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 X X X X X X Data start_bit, data (16), stop_bit start_bit, data (16), stop_bit start_bit, data (16), stop_bit
Load Data, Set PC = 2000h Load Data for Program Memory Read Data from Program Memory Increment Address Begin Programming End Programming
DS30278A-page 4
(c) 1997 Microchip Technology Inc.
In-Circuit Serial Programming
FIGURE 2-3: PROGRAM FLOW CHART - PIC16C715 PROGRAM MEMORY
Start
Set VDD = VDDP*
N=0 No Program Cycle N > 25 Yes Report Programming Failure
Read Data Command
N=N+1 N=# of Program Cycles No
Increment Address Command
Data Correct? Yes Apply 3N Additional Program Cycles
Program Cycle No Load Data Command
All Locations Done? Yes Verify all Locations @ VDD min.* VPP = VIHH2
Begin Programming Command
Wait 100 s Data Correct? Yes Verify all Locations @ VDD max. VPP = VIHH2 No Report Verify @ VDD min. Error End Programming Command
Data Correct? Yes Done
No
Report Verify @ VDD max. Error
*V DDP = VD D range for programming. VDD min = MinimumDD for device operation. V VDD max = Maximum DD for device operation. V
(c) 1997 Microchip Technology Inc.
DS30278A-page 5
PIC16C715
FIGURE 2-4: PROGRAM FLOW CHART - PIC16C715 CONFIGURATION WORD & ID LOCATIONS
Start
Load Configuration Command
N=0
No
Yes Program ID Loc?
Program Cycle
Read Data Command
Increment Address Command
No N=N+1 N=# of Program Cycles
Data Correct? Yes
No Address = 2004 Yes Yes Increment Address Command Report ID Configuration Error Apply 3N Program Cycles No N > 25
Increment Address Command
Increment Address Command
Program Cycle 100 times
Read Data Command
No Data Correct? Yes
Report Program No ID/Config. Error No Yes Done Data Correct?
Data Correct? Yes Set V = VDDmax V max DD DD Read Data Command Set V = V PP IHH2
Set V = VDDmin V min DD DD Read Data Command Set V = V PP IHH2
DS30278A-page 6
(c) 1997 Microchip Technology Inc.
In-Circuit Serial Programming
2.3.2.1 LOAD DATA
2.4
After receiving this command, the chip will load in a 16-bit "data word" when 18 cycles are applied, as described previously. A timing diagram for the load data command is shown in Figure 5-1. 2.3.2.2 READ DATA
Programming Algorithm Requires Variable VDD
The PIC16C715 uses an intelligent algorithm. The algorithm calls for program verification at VDDmin as well as VDDmax. Verification at VDDmin guarantees good "erase margin". Verification at VDDmax guarantees good "program margin". The actual programming must be done with VDD in the VDDP range (4.75 - 5.25V). VDDP = VCC range required during programming. VDD min. = minimum operating VDD spec for the part. VDDmax = maximum operating VDD spec for the part. Programmers must verify the PIC16C715 at its specified VDDmax and VDDmin levels. Since Microchip may introduce future versions of the PIC16C715 with a broader VDD range, it is best that these levels are user selectable (defaults are ok). Note: Any programmer not meeting these requirements may only be classified as "prototype" or "development" programmer but not a "production" quality programmer.
After receiving this command, the chip will transmit data bits out of the memory currently accessed starting with the second rising edge of the clock input. The RB7 pin will go into output mode on the second rising clock edge, and it will revert back to input mode (hi-impedance) after the 18th rising edge. A timing diagram of this command is shown in Figure 5-2. 2.3.2.3 INCREMENT ADDRESS
The PC is incremented when this command is received. A timing diagram of this command is shown in Figure 5-3. 2.3.2.4 BEGIN PROGRAMMING
A load command (load configuration or load data) must be given before every begin programming command. Programming of the appropriate memory (test program memory or user program memory) will begin after this command is received and decoded. Programming should be performed with a series of 100 s programming pulses. A programming pulse is defined as the time between the begin programming command and the end programming command. 2.3.2.5 END PROGRAMMING
After receiving this command, the chip stops programming the memory (configuration program memory or user program memory) that it was programming at the time.
(c) 1997 Microchip Technology Inc.
DS30278A-page 7
PIC16C715
3.0 CONFIGURATION WORD
The PIC16C715 family members have several configuration bits. These bits can be programmed (reads '0') or left unprogrammed (reads '1') to select various device configurations. Figure 3-1 provides an overview of configuration bits. Note: Parity bits are clocked in/out but not checked.
FIGURE 3-1:
Bit Number: PIC16C715
CONFIGURATION WORD BIT MAP
15
CP1
14
CP0
13
CP1
12
CP0
11
10
9
MPEEN
8
BODEN
7
CP1
6
CP0
5
PWRTE
4
WDTE
3
FOSC1
2
FOSC0
1
P
0
P
CP1 CP0
bit 9:
MPEEN, Memory Parity Error Enable 1: Memory parity Checking is enabled 0: Memory Parity Checking is disabled
bit 7-6: CP1:CP0, Code Protect
Device PIC16C715 CP1 0 0 1 1 CP0 Code Protection 0 All memory protected Upper 3/4 memory protected 1 Upper 1/2 memory protected 0 Code protection off 1
bit 8: BODEN, Brown-out Enable bit 1 = Enabled 0 = Disabled bit 5: PWRTE, Power-up Timer Enable bit 0 = Power up timer enabled 1 = Power up timer disabled bit 4: WDTE, WDT Enable bit 1 = WDT enabled 0 = WDT disabled
bit 3-2: FOSC1:FOSC0, Oscillator Selection bit 11: RC oscillator 10: HS oscillator 01: XT oscillator 00: LP oscillator bit 1-0: Parity bits for Configuration Word
DS30278A-page 8
(c) 1997 Microchip Technology Inc.
In-Circuit Serial Programming
4.0 CODE PROTECTION
4.1
The program code written into the EPROM can be protected by writing to the CP0 & CP1 bits of the configuration word. Note: Code protection should be the last test for a device, since the areas protected cannot be reprogrammed. Code protection is permanent for any device.
Programming Locations 0x000 to 0x7FF after Code Protection
For all PIC16C715 devices, once code protection is enabled, all protected segments read '0's (or "garbage values") and are prevented from further programming. All unprotected segments, including ID locations and configuration word, read normally. These locations can be programmed.
4.2
Embedding Configuration Word and ID Information in the Hex File
To allow portability of code, the programmer is required to read the configuration word and ID locations from the hex file when loading the hex file. If configuration word information was not present in the hex file then a simple warning message may be issued. Similarly, while saving a hex file, configuration word and ID information must be included. An option to not include this information may be provided. Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer.
TABLE 4-1:
PIC16C715
CONFIGURATION WORD
To code protect: * Protect all memory * Protect upper 1/2 memory * Protect upper 3/4 memory * No code protection
000000XX00XXXXXX 101010XX10XXXXXX 010101XX01XXXXXX 111111XX11XXXXXX R/W in Protected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read All 0's, Write Disabled Read Unscrambled, Write Enabled R/W in Unprotected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled
Program Memory Segment Configuration Word (0x2007) Unprotected memory segment Protected memory segment ID Locations (0x2000 : 0x2003)
(c) 1997 Microchip Technology Inc.
DS30278A-page 9
PIC16C715
4.3
4.3.1
Checksum
CHECKSUM CALCULATIONS
Checksum is calculated by reading the contents of the PIC16C715 memory locations and adding up the opcodes up to the maximum user addressable location, e.g., 0x7FF for the PIC16C715. Any carry bits exceeding 16-bits are neglected. Finally, the configuration word (appropriately masked) is added to the checksum. Checksum computation for each member of the PIC16C715 devices is shown in Table 4-2. The checksum is calculated by summing the following: * The contents of all program memory locations * The configuration word, appropriately masked * Masked ID locations (when applicable) The least significant 16 bits of this sum is the checksum. The following table describes how to calculate the checksum for each device. Note that the checksum calculation differs depending on the code protect setting. Since the program memory locations read out differently depending on the code protect setting, the table describes how to manipulate the actual program mem-
ory values to simulate the values that would be read from a protected device. When calculating a checksum by reading a device, the entire program memory can simply be read and summed. The configuration word and ID locations can always be read. Note that some older devices have an additional value added in the checksum. This is to maintain compatibility with older device programmer checksums.
TABLE 4-2:
Device
PIC16C715
CHECKSUM COMPUTATION
Code Protect Checksum* 0x25E6 at Blank 0 and max Value address
OFF SUM[0x0000:0x07FF] + (CONFIG & 0x3FFF) 0x37FF 0x03CD 1/2 SUM[0x0000:0x03FF] + (CONFIG & 0x3FFF) + SUM_ID 0x5EEE 0x10A3 3/4 SUM[0x0000:0x01FF] + (CONFIG & 0x3FFF) + SUM_ID 0x4BDE 0xFD93 ALL (CONFIG & 0x3FFF) + SUM_ID 0x38CE 0x049C Legend: CFGW = Configuration Word SUM[a:b] = [Sum of locations a through b inclusive] SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. For example, ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746. *Checksum = [Sum of all the individual expressions] MODULO [0xFFFF] + = Addition & = Bitwise AND
DS30278A-page 10
(c) 1997 Microchip Technology Inc.
In-Circuit Serial Programming
5.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS
AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE TABLE 5-1:
Standard Operating Conditions Operating Temperature: +10C TA +40C, unless otherwise stated, (20C recommended) Operating Voltage: 4.5V VDD 5.5V, unless otherwise stated. Parameter No. General P1 P2 VDDP Supply voltage during programming IDDP Supply current (from VDD) during programming 4.75 -- 5.0 -- 5.25 20 V mA Sym. Characteristic Min. Typ. Max. Units Conditions
Note 1: Program must be verified at the minimum and maximum VDD limits for the part. Note 2: VIHH must be greater than VDD + 4.5V to stay in programming/verify mode.
TABLE 5-1:
AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE
Standard Operating Conditions Operating Temperature: +10C TA +40C, unless otherwise stated, (20C recommended) Operating Voltage: 4.5V VDD 5.5V, unless otherwise stated. Parameter No. P3 P4 P5 P6 P9 P8 Sym. Characteristic Min. VDDmin 12.75 VDD + 4.0 -- 0.8 VDD 0.2 VDD Typ. -- -- -- -- -- -- Max. VDDmax 13.25 13.5 50 -- -- Units V V -- mA V V Schmitt Trigger input Schmitt Trigger input Conditions Note 1 Note 2
VDDV Supply voltage during verify VIHH1 Voltage on MCLR/VPP during programming VIHH2 Voltage on MCLR/VPP during verify IPP VIH1 VIL1 Programming supply current (from VPP) (RB6, RB7) input high level (RB6, RB7) input low level
Serial Program Verify P1 P2 P3 P4 P5 TR TF MCLR/VPP rise time (VSS to VHH) for test mode entry MCLR Fall time -- -- 100 100 1.0 -- -- -- -- -- 8.0 8.0 -- -- -- s s ns ns s
TSET1 Data in setup time before clock THLD1 Data in hold time after clock TDLY1 Data input not driven to next clock input (delay required between command/data or command/command) TDLY2 Delay between clock to clock of next command or data TDLY3 Clock to date out valid (during read data) THLD0 Hold time after MCLR
P6 P7 P8
1.0 200 2
-- -- --
-- -- --
s ns s
Note 1: Program must be verified at the minimum and maximum VDD limits for the part. Note 2: VIHH must be greater than VDD + 4.5V to stay in programming/verify mode.
(c) 1997 Microchip Technology Inc.
DS30278A-page 11
PIC16C715
FIGURE 5-1:
VIHH MCLR/ VPP P8 1 RB6 (CLOCK) RB7 (DATA) 0 P3 P4 100ns min. Reset 1s min. P3 1 100ns 0 0 0 0 P5 P4 2 3 4 5 6 100ns P6 1s min.1 2 3 4 5 15
\LOAD DATA COMMAND (PROGRAM/VERIFY)
0
0
} }
} }
100ns min.
Program/Verify Test Mode
FIGURE 5-2:
VIHH MCLR /V PP
READ DATA COMMAND (PROGRAM/VERIFY)
100ns P8 1 2 3 4 5 6 P6 1s min.1 2 3 4 5 15
RB6 (CLOCK) RB7 (DATA) 0 P3 0 P4 100ns 1 0 0 0
P7 P5 1s min. RB7 input
} }
100ns min. RB7 = output
Reset
Program/Verify Test Mode
FIGURE 5-3:
MCLR /V PP
INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY)
VIHH P6 1s min. Next Command 1 2
1 RB6 (CLOCK) RB7 (DATA)
2
3
4
5
6
0
1
1
0
0
0 P5
0
0
P3 P4
1s min.
Program/Verify Test Mode
Reset
} }
100ns min
DS30278A-page 12
(c) 1997 Microchip Technology Inc.
In-Circuit Serial Programming
NOTES:
(c) 1997 Microchip Technology Inc.
DS30278A-page 13
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All rights reserved. (c)1997, Microchip Technology Incorporated, USA. 8/97
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS30278A-page 14
(c) 1997 Microchip Technology Inc.

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