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ST486DX/DX2
5 Volt CPUs
PRELIMINARY DATA
ON-CHIP 8-KBYTE WRITE-BACK CACHE - Up to 15% higher performance than write-through IMPROVED 486DX/DX2 PERFORMANCE - Clock doubled core speeds up to 80 MHz - Integrated FPU 10% faster than 80486DX - Up to 50 MHz bus speeds for fast local bus systems INDUSTRY STANDARD 486 COMPATIBILITY - 486DX socket and instruction set compatible - Runs DOS, Windows, OS/2, UNIX - Standard 168-pin PGA (PC Bench 8.0, 80MHZ) - Industry-wide write-back chipset suppor - Burst-mode write capability - Configurable as write-back or write-through ADVANCED POWER MANAGEMENT - Fast SMI interrupt with separate memory space - Fully static design permits dynamic clock control - Software or hardware initiated low power suspend - Automatic FPU power-down mode
The SGS-THOMSON ST486DX/DX2 5 volt CPUs are advanced 486DX/DX2 compatible processors. These CPUs incorporate an on-chip 8KByte write-back cache and an integrated math coprocessor. The on-chipwrite-back cache allowsup to 15% higher performance by eliminating unnecessary external write cycles. On traditional write-through CPUs, these external write cycles can create bus bottlenecks affecting system wide performance. The integrated floating point unit, improves performance up to 10% over the 80486DX as measured using Power Meter Whetstone test. These processors are designed to meet the power management requirements in the newest generation of low-power desktops and notebooks. Power is saved by taking advantage of advanced power management features such as static circuitry, SMM, and automatic FPU power-down. Fast entry and exit of SMM allows frequent use of the SMM feature without noticeable performance degradation. This CPU family maintains compatibility with the installed base of x86 software and provides essential socket compatibility with the 486DX/DX2
Decoder Control ROM Address Sequencer Control Branch Control
Limit Unit
16-byte Instruction Queue
SUSP# Core Clock Prefetch Data Bus
32
Immediate
Microcode ROM Immediate
Bus Clock
SMM, Suspend Mode and Clock Control
SUSPA# CLK SMI# SMADS#
Execution Pipeline
Execution Unit 3-Input Multiplier Shift Register Adder Unit File Unit Unit Linear Address Bus
Memory Data Bus
Byte Muxes & I/O Regs
8 Write Buffers
D31-D0 Data Buffers 32
Cache and Memory Management
Memory Management Unit
Prefetch Unit
8 KByte Instr/Data Cache
FPU
Control
Bus Control
Control
Instruction Address Bus Data AddressBus
Address Buffers
A31-A2 BE3#-BE0#
486DX Compatible Bus Interface
1738600
1
ST486/DX/DX2 5Volt CPUs - PRODUCT OVERVIEW
1.0
PRODUCT OVERVIEW
The SGS THOMSON ST486DXTM 5-volt microprocessors are advanced 486DX/DX2 microprocessors. The ST486DX CPU operates at the same speed as the external bus and the ST486DX2 CPU operates at twice the external bus speed. The "ST486DX/DX2" designation refers to either the ST486DX or ST486DX2 microprocessor. A more complete product description can be found in the SGS-Thomson ST486DX/DX2 data book. (see ordering instructions). The CPUs in the ST486DX/DX2 family are high speed 5-volt CPUs attaining clock-doubled core speeds of up to 80 MHz. The ST486DX/DX2 8-KByte cache can be configured to run in traditional write-through mode or in the higher performance write-back mode. Write-back mode eliminates unnecessary external memory write cycles offering up to 15% higher overall performance (80 MHz, PC Bench 8.0) than write-through mode. The ST486DX/DX2 supports 8, 16 and 32-bit data types and operates in real, virtual 8086 and protected modes. The CPU can access up to 4 GBytes of physical memory using a 32-bit burst mode bus. Floating point instructions are parallel processed using an on-chip math coprocessor. The ST486DX/DX2 CPUs are ideal design solutions for low-powered "Green PC" desktops as well as portable computers. These microprocessors typically draw only 450 A, while the input clock is stopped in suspend mode, due to their static design. System Management Mode (SMM) allows the implementation of transparent system power management or the software emulation of I/O peripheral devices.
A list of ST486DX/DX2 5-volt parts, including their operating frequency, and package types are listed on page 12 of this document.
1.1
Clock-Doubled CPU Core
The clock-doubled ST486DX2 CPU core operates at twice the frequency of the external clock input, while continuing to operate the bus interface at the external clock frequency. This configuration provides high frequency CPU performance without requiring a high speed interface to external memory. The ST486DX2 provides up to 1.8 times the performance of a 486DX at the same external clock frequency. This level of performance is achieved by doubling the frequency of the input clock and using the resulting signal to drive the CPU core. To further enhance this architecture, the ST486DX2 reduces the performance penalty of slow external memory accesses through use of an on-chip write-back cache and eight write buffers. The CPU core consists of a five-stage pipeline optimized for minimal instruction cycle times and includes all necessary hardware interlocks to permit successive instruction execution overlap. The execution stage of the pipeline executes simple but frequently used instructions in a single clock cycle and the hardware multiplier executes 16-bit integer multiplies in only three clocks.
1.2
On-Chip Write-Back Cache
The ST486DX/DX2 on-chip cache can be configured to run in traditional write-through mode or in a higher performance write-back mode. The write-back cache mode was specifically designed to optimize performance of the CPU core by eliminating bus bottlenecks caused by unnecessary external write cycles. This write-back architecture is especially effec-
2
ST486/DX/DX2 5Volt CPUs - PRODUCT OVERVIEW
tive in improving performance of the clockdoubled ST486DX2 CPU. Traditional write-through cache architectures require that all writes to the cache also update external memory simultaneously. These unnecessary write cycles create bottlenecks which result in CPU stalls and adversely impact performance. In contrast, a write-back architecture allows data to be written to the cache without updating external memory. With a write-back cache, external write cycles are only required when a cache miss occurs, a modified line is replaced in the cache, or when an external bus master requires access to data. The ST486DX/DX2 cache is an 8-KByte unified instruction and data cache implemented using a four-way set associative architecture and a least recently used (LRU) replacement algorithm. The cache is designed for optimum performance in write-back mode, however, the cache can be operated in write-through mode. The cache line size is 16 bytes and new lines are only allocated during memory read cycles. Valid status is maintained on a 16-byte cache line basis, but modified or "dirty" status for write-back mode is maintained on a 4-byte (double-word) basis. Therefore, only the double-words that have been modified are written back to external memory when a line is replaced in the cache. The CPU core can access the cache in a single internal clock cycle for both reads and writes.
1.4
System Management Mode
System Management Mode (SMM) provides an additional interrupt and a separate address space that can be used for system power management or software transparent emulation of I/O peripherals. SMM is entered using the System Management Interrupt (SMI#) or SMINT instruction. While running in isolated SMM address space, the SMI interrupt routine can execute without interfering with the operating system or application programs. After entering SMM, portions of the CPU state are automatically saved. Program execution begins at the base of SMM address space. The location and size of the SMM memory are programmable within the ST486DX/DX2. Eight SMM instructions have been added to the 486 instruction set that permit software entry into SMM, as well as saving and restoring the total CPU state when in SMM mode.
1.5
Power Management
The ST486DX/DX2 power management features allow for a dramatic improvement in battery life over systems designed with non-static 486 processors. During suspend mode the typical current consumption is less than 1 percent of the full operation current. Suspend mode is entered by either a hardware or a software initiated action. Using the hardware method to initiate suspend mode involves a two-pin handshake between the SUSP# and SUSPA# signals. The software can initiate suspend mode through the execution of the HALT instruction. Once in suspend mode, the ST486DX/DX2 power consumption is further reduced by stopping the external clock input. The resulting current draw is typically less than 500 A. Since the ST486DX/DX2 is static, no internal data is lost when the clock is stopped.
1.3
FPU Operations
Since the FPU is resident within the CPU, the overhead associated with external math coprocessor cycles is eliminated. If the FPU is not in use, the FPU is automatically powered down. This feature reduces overall power consumption. The integrated FPU results in the addition of two new pins FERR# (replaces ERROR#) and IGNNE#.
3
ST486/DX/DX2 5Volt CPUs - PRODUCT OVERVIEW
1.6
Signal Summary
The ST486DX/DX2 signal set includes five cache interface signals, two coprocessor interface signals, two power management signals, and two system management mode signals.
A31-A2 A20M# AHOLD BOFF# BRDY# BS16#, BS8# CLK EADS# FLUSH# IGNNE# INTR INVAL HOLD KEN# NMI RDY# RESET SMI# SUSP# UP# WM_RST 5 4 3 1 1 1 4 3 1 1 1 1 1 2 2 1 1 ADS# BE3#-BE0# BLAST# BREQ
ST486DX/DX2 CPU
D31-D0 D/C# DP3-DP0 FERR# HITM# HLDA LOCK# M/IO# PCD PCHK# PLOCK# PWT RPLSET(1-0) RPLVAL# SMADS# SUSPA# W/R#
1 - Cache Interface 2 - Coprocessor Interface 3 - Power Management
4 - System Management Mode 5 - Reset Input
1738000
Figure 1 - 1.
4
ST486/DX/DX2 5Volt CPUs - ELECTRICAL SPECIFICATIONS
2.0
ELECTRICAL SPECIFICATIONS
Electrical specifications in this chapter are valid for both the ST486DX and the clock-doubled ST486DX2. The ST486DX2 differs from the ST486DX in that the ST486DX2 internal CPU core operates at twice the frequency of the bus interface.
not require connection to external pull-up or pull-down resistors. The SUSP# pin is unique in that it is connected to a pull-up resistor only when SUSP# is not asserted. Table 2 - 1. Pins Connected to Internal Pull-Up and Pull-Down Resistors
SIGNAL A20M# AHOLD BOFF# BS16# BS8# BRDY# EADS# FLUSH# IGNNE# INVAL KEN# RDY# UP# SUSP# WM_RST RESISTOR 20-k pull-up 20-k pull-down 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-down
2.1 2.1.1
Electrical Connections Power and Ground Connections and Decoupling
Due to the high frequency of operation of the ST486DX/DX2, it is necessary to install and test this device using standard high frequency techniques. The high clock frequencies used in the ST486DX/DX2 and its output buffer circuits can cause transient power surges when several output buffers switch output levels simultaneously. These effects can be minimized by filtering the DC power leads with low-inductance decoupling capacitors, using low impedance wiring, and by utilizing all of the VCC and GND pins.
2.1.2
Pull-Up/Pull-Down Resistors
It is recommended that the ADS#, LOCK# and SMI# output pins be connected to pull-up resistors, as indicated in Table 2-2. The external pull-ups guarantee that the signals remain negated during hold acknowledge states. Table 2 - 2. Pins Requiring External Pull-Up Resistors
EXTERNAL RESISTOR 20-k pull-up 20-k pull-up 20-k pull-up
Table 2-1 lists the input pins which are internally connected to pull-up and pull-down resistors. The pull-up resistors are connected to VCC and the pull-down resistors are connected to VSS. When unused, these inputs do
SIGNAL ADS# LOCK# SMI#
5
ST486/DX/DX2 5Volt CPUs - ELECTRICAL SPECIFICATIONS
2.1.3
Unused Input Pins
2.2
Absolute Maximum Ratings
All inputs not used by the system designer and not listed in Table 2-1 (Page 5) should be connected either to ground or to VCC. Connect active-high inputs to ground through a 20 k (10%) pull-down resistor and activelow inputs to VCC through a 20 k (10%) pull-up resistor to prevent possible spurious operation.
2.1.4
NC Designated Pins
Pins designated NC should be left disconnected. Connecting an NC pin to a pull-up resistor, pull-down resistor, or an active signal could cause unexpected results and possible circuit malfunctions. Table 2 - 3.
The following table lists absolute maximum ratings for the ST486DX/DX2 microprocessors. Stresses beyond those listed under Table 2-3 limits may cause permanent damage to the device. These are stress ratings only and do not imply that operation under any conditions other than those listed under "Recommended Operating Conditions" Table 2-4 (Page 6) is possible. Exposure to conditions beyond Table 2-3 may (1) reduce device reliability and (2) result in premature failure even when there is no immediately apparent sign of failure. Prolonged exposure to conditions at or near the absolute maximum ratings (Table 2-3) may also result in reduced useful life and reliability.
Absolute Maximum Ratings
ST486DX/DX2 MIN MAX -65 +110 -65 +150 -0.5 6.5 -0.5 VCC + 0.5 10 25 UNITS C C V V mA mA NOTES Power Applied No Bias With Respect to VSS With Respect to VSS Power Applied Power Applied
PARAMETER Case Temperature Storage Temperature Supply Voltage, VCC Voltage On Any Pin Input Clamp Current, IIK Output Clamp Current, IOK
2.3
Recommended Operating Conditions
Table 2-4 presents the recommended operating conditions for the ST486DX/DX2 device. Table 2 - 4. Recommended Operating Conditions
ST486DX/DX2 MIN MAX 0 +85 4.75 5.25 2 VCC+0.3 -0.3 0.8 -1 5 UNITS C V V V mA mA NOTES Power Applied With Respect to Vss
PARAMETER TC Case Temperature VCC Supply Voltage VIH High Level Input VIL Low Level Input IOH Output Current (High) IOL Output Current (Low)
VOH=VOH(MIN) VOL=VOL(MAX)
6
ST486/DX/DX2 5Volt CPUs - ELECTRICAL SPECIFICATIONS
2.4
DC Characteristics
DC Characteristics (at Recommended Operating Conditions)
ST486DX/DX2 MIN MAX 0.45 UNITS NOTES
Table 2 - 5.
PARAMETER
VOL Output Low Voltage V IOL = 5 mA VOH Output High Voltage 2.4 V IOH = -1 mA 07
ST486/DX/DX2 5Volt CPUs - MECHANICAL SPECIFICATIONS
3.0 3.1
MECHANICAL SPECIFICATIONS 168-Pin PGA Package
The pin assignments for the ST486DX/DX2 168-pin PGA package are shown in Figure 3-1. The pins are listed by signal name and pin number in Table 3-2.
S
R
Q
P
N
M
Vss
L
Vss
K
V ss
J
NC
H
Vs s
G
Vs s
F
E
Vss
D
C
B
D19
A
D20
A27
A28
A31
D0
D2
DP1
D9
D11
1
A26 A25
1
Vss
A29 D1
Vc c
D6
Vc c
D5
D3
Vcc
D8
Vc c
D13
D18
D21
D22
2
A23
2
Vc c
A17 A30 DP0 D4 D7 D14 D16 DP2 D12 D15 D10 D17
CLK
Vss
NC
3
INVAL
3
Vss
A19
Vc c
Vss
D23
4
A14 A18 A21
4
Vcc Vs s
DP3
5
Vs s Vcc
A24 D27 D25 D24
5
6
A12 A15 A22
7
Vss Vc c
A20
8
Vss Vc c
A16
9
Vs s Vc c
A13
ST486DX or ST486DX2 168-Pin PGA
6
D26
Vc c
Vs s
7
D28 D31 D29
8
D30
Vc c
Vs s
9
SMADS# NC SUSPA#
10
Vss Vcc
A9
(Top View)
10
UP#
Vc c
Vs s
11
Vss
A11
11
A5
RPLSET0 NC SMI#
12
A10
12
A8 A7 RPLVA L# WM_RST RPLSET1
13
Vs s Vcc
A2
FERR# NC NC
13 14
A6 A3
BREQ
14
HLDA LOCK# D/C#
PWT BE0# BE2# BRDY# SUSP# KEN# HOL D A20M# FLUSH# NMI IGNNE#
15
A 4 B LAST# PLOCK# Vc c
M/IO#
15
Vc c Vcc Vc c
BE1#
Vc c
Vc c
RDY#
Vc c
BS8#
RESET
NC
INTR
16
ADS# HITM# PCHK#
16
Vss
W/R#
Vs s
Vss
Vss
PCD
Vs s
Vss
BE3#
Vss
BOFF# BS16# EADS# AHOLD
17
17
S
R
Q
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1738300
Figure 3 - 1.
168-Pin PGA Package Pin Assignments
8
ST486/DX/DX2 5Volt CPUs - MECHANICAL SPECIFICATIONS
Table 3 - 2.
Signal Name A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 Pin No. Q14 R15 S16 Q12 S15 Q13 R13 Q11 S13 R12 S7 Q10 S5 R7 Q9 Q3 R5 Q4 Q8
168-Pin PGA Package Pin Numbers Sorted by Signal Name
Signal Name A29 A30 A31 ADS# AHOLD BE0# BE1# BE2# BE3# BLAST# BOFF# BRDY# BREQ BS8# BS16# CLK D/C# D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 Pin No. P2 P3 Q1 S17 A17 K15 J16 J15 F17 R16 D17 H15 Q15 D16 C17 C3 M15 P1 N2 N1 H2 M3 J2 L2 L3 F2 D1 E3 Signal Name D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 DP0 DP1 DP2 DP3 EADS# FERR# FLUSH# Pin No. C1 G3 D2 K3 F3 J3 D3 C2 B1 A1 B2 A2 A4 A6 B6 C7 C6 C8 A8 C9 B8 N3 F1 H3 A5 B17 C14 C15 Signal Name HITM# HLDA HOLD IGNNE# INTR INVAL KEN# LOCK# M/IO# NC NC NC NC NC NC NC NMI PCD PCHK# PLOCK# PWT RDY# RESET RPLSET0 RPLSET1 RPLVAL# SMADS# SMI# Pin No. R17 P15 E15 A15 A16 S4 F15 N15 N16 A3 A14 B10 B12 B14 B16 J1 B15 J17 Q17 Q16 L15 F16 C16 C12 A13 C13 C10 A12 Signal Name SUSP# SUSPA# UP# VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS Pin No. G15 A10 C11 B7 B9 B11 C4 C5 E2 E16 G2 G16 H16 K2 K16 L16 M2 M16 P16 R3 R6 R8 R9 R10 R11 R14 A7 A9 Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS W/R# WM_RST Pin No. A11 B3 B4 B5 E1 E17 G1 G17 H1 H17 K1 K17 L1 L17 M1 M17 P17 Q2 R4 S6 S8 S9 S10 S11 S12 S14 N17 B13
Table 3 - 1.
A20M# D15 A21 A22 A23 A24 A25 A26 A27 A28 Q5 Q7 S3 Q6 R2 S2 S1 R1
9
ST486/DX/DX2 5Volt CPUs - MECHANICAL SPECIFICATIONS
3.3
Thermal Characteristics
The ST486DX/DX2 is designed to operate when case temperature is between 0 - 85C. The case temperature is measured on the top center of the package. The maximum die temperature (TJ MAX) and the maximum ambient temperature (TaMAX) can be calculated using the following equations. Tj MAX = Tc + (PMAX x jc) Ta MAX = Tj - (PMAX x ja) where: Tj MAX = Maximum average junction temperature (C) Tc = Case temperature at top center of package (C) PMAX = Maximum device power dissipation (W) jc = Junction-to-case thermal resistance (C/W) Ta MAX = Maximum ambient temperature (C) Tj = Average junction temperature (C) ja = Junction-to-ambient thermal resistance (C/W)
PGA Package Table 3-3 lists the junction-to-ambient and junction-to-case thermal resistances for the PGA package. Table 3-4 lists the maximum ambient temperatures permitted for various clock frequencies and airflows for the PGA Package for Vcc equal to 5.25 volts. Package dimensions for the heatsink used for the thermal analysis are shown in Figure 3-2 (Page 11) and Table 3-5 (Page 11). Table 3 - 3. PGA Package Thermal Resistance and Airflow
AIRFLOW (FT/MIN) PGA THERMAL RESISTANCE (C/W) WITH HEATSINK ja 0 200 400 600 800 12 8 6 4.5 4 jc 3.5 3.5 3.5 3.5 3.5 WITHOUT HEATSINK ja 17 15 12 10 9 jc 3.0 3.0 3.0 3.0 3.0
10
ST486/DX/DX2 5Volt CPUs - MECHANICAL SPECIFICATIONS
Table 3 - 4.
CPU INTERNAL CLOCK FREQUENCY 33 MHz 33 MHz 40 MHz 50 MHz 66 MHz 80 MHz
PGA Package Maximum Ambient Temperature (TA) with VCC =5.25 V
AIRFLOW HEATSINK 0 (FT/MIN) No Yes Yes Yes Yes Yes 17 C 43 C 39 C 32 C 26 C see note 200 (FT/MIN) 26 C 63 C 60 C 57 C 53 C see note 400 (FT/MIN) 41 C 73 C 71 C 69 C 67 C 65 C 600 (FT/MIN) 51 C 80 C 79 C 78 C 78 C 77 C 800 (FT/MIN) 55 C 82 C 82 C 81 C 81 C 81 C
Note: The ST486DX2-80 (80MHz) requires a minimum airflow of 400 (FT/MIN) for safe operation. Active heatsink (fan incorporated) is recommended
B C
A
D
1720703
Figure 3 - 2.
Heatsink for PGA Package Table 3 - 5.
SYMBOL A B C D
Typical PGA Heatsink Dimensions
MILLIMETERS 6.1 1.3 4.8 39.1 INCHES 0.24 0.05 0.19 1.54
11
ST486/DX/DX2 5Volt CPUs - MECHANICAL SPECIFICATIONS
ST SGS-THOMSON Prefix Device Name 486DX Clock Doubling Blank = 1x clock 2 = Clock doubling Voltage Blank = 5 volts
486DX
2-
80
GS
Speed (internal clock frequency) 33 = 33 MHz 40 = 40 MHz 50 = 50 MHz 66 = 66 MHz 80 = 80 MHz Package Type G = PGA Package
Temperature Range S = 0 to 85o C Case Temp B = 0 to 70o C Case Temp
1724300
To order the complete ST486DX/DX2 DATABOOK use order code: DBST486DXST/1
ST486DX and ST486DX2 Part Numbers
PART NUMBER
Vcc (V)
ST486DX-33GS ST486DX-40GS ST486DX-50GS ST486DX2-50GS ST486DX2-66GS ST486DX2-80GS
5.0 5.0 5.0 5.0 5.0 5.0
FREQUENCY (MHz) BUS INTERNAL 33 33 40 40 50 50 25 50 33 66 40 80
PACKAGE PGA x x x x x x
12
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics.
(c) 1995 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China- France - Germany - Hong Kong - Italy- Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.

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