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PD - 9.1496A
PRELIMINARY Logic-Level Gate Drive Advanced Process Technology l Isolated Package l High Voltage Isolation = 2.5KVRMS l Sink to Lead Creepage Dist. = 4.8mm l Fully Avalanche Rated Description
l l
IRLI520N
HEXFET(R) Power MOSFET
D
VDSS = 100V RDS(on) = 0.18
G
ID =8.1A
S
Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The TO-220 Fullpak eliminates the need for additional insulating hardware in commercial-industrial applications. The moulding compound used provides a high isolation capability and a low thermal resistance between the tab and external heatsink. This isolation is equivalent to using a 100 micron mica barrier with standard TO-220 product. The Fullpak is mounted to a heatsink using a single clip or by a single screw fixing.
TO-220 FULLPAK
Absolute Maximum Ratings
Parameter
ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS EAS IAR EAR dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Mounting torque, 6-32 or M3 screw
Max.
8.1 5.7 35 30 0.20 16 85 6.0 3.0 5.0 -55 to + 175 300 (1.6mm from case ) 10 lbf*in (1.1N*m)
Units
A W W/C V mJ A mJ V/ns C
Thermal Resistance
Parameter
RJC RJA Junction-to-Case Junction-to-Ambient
Typ.
--- ---
Max.
5.0 65
Units
C/W 3/16/98
IRLI520N
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
V(BR)DSS
V(BR)DSS/TJ
Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Drain to Sink Capacitance
RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss C
Min. 100 --- --- --- --- 1.0 3.1 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- ---
Typ. --- 0.11 --- --- --- --- --- --- --- --- --- --- --- --- 40 35 23 22
Max. Units Conditions --- V VGS = 0V, ID = 250A --- V/C Reference to 25C, ID = 1mA 0.18 VGS = 10V, ID = 6.0A 0.22 VGS = 5.0V, ID = 6.0A 0.26 VGS = 4.0V, ID = 5.0A 2.0 V VDS = VGS, ID = 250A --- S VDS = 25V, ID = 6.0A 25 VDS = 100V, VGS = 0V A 250 VDS = 80V, VGS = 0V, TJ = 150C 100 VGS = 16V nA -100 VGS = -16V 20 ID = 6.0A 4.6 nC VDS = 80V 10 VGS = 5.0V, See Fig. 6 and 13 --- VDD = 50V --- ID = 6.0A ns --- RG = 11, VGS = 5.0V --- RD = 8.2, See Fig. 10 Between lead, 4.5 --- 6mm (0.25in.) nH G from package 7.5 --- and center of die contact 440 --- VGS = 0V 97 --- VDS = 25V pF 50 --- = 1.0MHz, See Fig. 5 12 --- = 1.0MHz
D
S
Source-Drain Ratings and Characteristics
IS
ISM
VSD trr Qrr ton
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time
Min. Typ. Max. Units
Conditions D MOSFET symbol --- --- 8.1 showing the A G integral reverse --- --- 35 p-n junction diode. S --- --- 1.3 V TJ = 25C, IS = 6.0A, VGS = 0V --- 110 160 ns TJ = 25C, IF = 6.0A --- 410 620 nC di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. 11 ) Starting TJ = 25C, L = 4.7mH RG = 25, IAS = 6.0A. (See Figure 12) ISD 6.0A, di/dt 340A/s, VDD V(BR)DSS, TJ 175C
Pulse width 300s; duty cycle 2%. t=60s, =60Hz
Uses IRL520N data and test conditions
IRLI520N
100
VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V TOP
100
ID , D rain-to-S ource C urrent (A )
10
ID , D rain-to-S ource C urrent (A )
VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V TOP
10
2.5V
1
1
2.5V
0.1 0.1 1
20 s P U LS E W ID TH T J = 25C
10
A
0.1 0.1 1
20 s P U LS E W ID TH T J = 175C
10
A
100
100
V D S , D rain-to-S ource V oltage (V )
V D S , D rain-to-S ource V oltage (V )
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
100
3.0
R D S (on ) , D rain-to-S ource O n R esistance (N orm alized)
I D = 10A
I D , D ra in -to-S o urc e C urren t (A )
2.5
T J = 2 5 C
10
T J = 1 7 5 C
2.0
1.5
1
1.0
0.5
0.1 2 4 6
VDS = 5 0V 2 0 s P U L S E W ID T H
8 10
A
0.0 -60 -40 -20 0 20 40 60 80
V G S = 10V
100 120 140 160 180
A
V G S , G a te -to -S o u rc e V o lta g e (V )
T J , Junction T em perature (C )
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
IRLI520N
800
V G S , G ate-to-S ource V oltage (V )
V GS C iss C rss C oss
= = = =
0V , f = 1M H z C gs + C gd , C ds S H O R TE D C gd C ds + C gd
15
I D = 6.0A V D S = 80V V D S = 50V V D S = 20V
12
C , C apacitanc e (pF )
600
C is s
9
400
C os s
200
6
C rs s
3
0 1 10 100
A
0 0 5 10
FO R TE S T C IR C U IT S E E FIG U R E 13
15 20 25
A
V D S , D rain-to-S ource V oltage (V )
Q G , Total G ate C harge (nC )
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
100
100
I S D , R everse D rain C urrent (A )
O P E R A TIO N IN TH IS A R E A LIM ITE D B Y R D S (on)
10 s
10
TJ = 175C
I D , D rain C urrent (A )
10 100 s
T J = 25C
1m s 1 10 m s
1
0.1 0.4 0.6 0.8 1.0
V G S = 0V
1.2
A
0.1 1
T C = 25C T J = 175C S ingle P ulse
10 100
A
1000
1.4
V S D , S ource-to-D rain V oltage (V )
V D S , D rain-to-S ource V oltage (V )
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
IRLI520N
10.0
VDS
8.0
RD
VGS RG
D.U.T.
+
I D , Drain Current (A)
-VDD
6.0
5.0V
Pulse Width 1 s Duty Factor 0.1 %
4.0
Fig 10a. Switching Time Test Circuit
2.0
VDS 90%
0.0 25 50 75 100 125 150 175
TC , Case Temperature ( C)
Fig 9. Maximum Drain Current Vs. Case Temperature
10% VGS
td(on) tr t d(off) tf
Fig 10b. Switching Time Waveforms
10
Thermal Response (Z thJC )
D = 0.50 0.20 0.10 0.05 0.02 0.01 0.1 SINGLE PULSE (THERMAL RESPONSE) P DM t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak TJ = P DM x Z thJC + TC 0.0001 0.001 0.01 0.1 1
1
0.01 0.00001
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
IRLI520N
200
E A S , S ingle P ulse A valanc he E nergy (m J)
TO P
160
15V
B O TTO M
ID 2.4A 4.2A 6.0 A
VDS
L
D R IV E R
120
RG
10V
D .U .T
IA S tp
+ V - DD
80
A
0 .0 1
40
Fig 12a. Unclamped Inductive Test Circuit
0 25 50 75 100 125 150
A
175
V (B R )D S S tp
S tarting T J , Junction T em perature (C )
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
IAS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator Same Type as D.U.T.
50K 12V .2F .3F
QG
5.0 V
QGS VG QGD
VGS
3mA
D.U.T.
+ V - DS
IG
ID
Charge
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
Fig 13b. Gate Charge Test Circuit
IRLI520N
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
-
+
RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
+ VDD
Driver Gate Drive P.W. Period D=
P.W. Period VGS=10V
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
VDD
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS
IRLI520N
Package Outline
TO-220 Fullpak Outline Dimensions are shown in millimeters (inches)
10 .60 (.41 7 ) 10 .40 (.40 9 ) o 3.40 (.1 33 ) 3.10 (.1 23 ) -A 3.70 (.145 ) 3.20 (.126 ) 4 .8 0 (.1 89 ) 4 .6 0 (.1 81 ) 2 .8 0 (.1 10) 2 .6 0 (.1 02) LE A D A S S IG N M E N T S 1 - GATE 2 - D R A IN 3 - SOU RC E
7.10 (.2 80 ) 6.70 (.2 63 )
1 6.00 (.6 30) 1 5.80 (.6 22)
1.15 (.04 5) M IN . 1 2 3
NOTES: 1 D IM E N S IO N IN G & TO L E R A N C IN G P E R A N S I Y 1 4.5 M , 19 8 2 2 C O N T R O LL IN G D IM E N S IO N : IN C H .
3.3 0 (.1 30) 3.1 0 (.1 22) -B1 3.70 (.5 40) 1 3.50 (.5 30) C D
A 1 .4 0 (.05 5) 3X 1 .0 5 (.04 2) 2 .54 (.10 0 ) 2X 3X 0 .9 0 (.0 35) 0 .7 0 (.0 28) 0.25 (.0 10) M AM B 3X 0 .4 8 (.0 1 9) 0 .4 4 (.0 1 7)
B
2 .85 (.11 2 ) 2 .65 (.10 4 )
M IN IM U M C R E E P A G E D IS T A N C E B E TW E E N A -B -C -D = 4.8 0 (.1 89 )
Part Marking Information
TO-220 Fullpak
E X AE X A M P: L E : IS HIS A N AIR F IR F I8 4 0 G MPLE TH T IS IS N 1 0 1 0 W ITH IT H S E M B L Y L Y W AS ASSEMB L O TL O T D E D E 1E 4 0 1 CO CO 9B M
A
IN TE R N A T IO N A L IN R E T E R N A R IO N A L C T IF IE T IR FF I81 0 G R E C T IF IE R IR 1 0 4 0 LO GO 9246 LOGO 9 B 40 1 1 M E 92 45 A S S E MML Y Y ASSE B BL LOT T COO D E LO CDE
P A R T N U M B E RA PART NUMBER
D A TE C O D E (Y Y W E ) O D E DAT W C Y(Y Y= Y E)A R Y WW YY = W AR W W = YE E E K W W = W EEK
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331 EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020 IR CANADA: 15 Lincoln Court, Brampton, Ontario L6T 3Z2, Tel: (905) 453 2200 IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590 IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111 IR FAR EAST: 171 (K&H Bldg.) 30-4 Nishi-ikebukuro 3-chome, Toshima-ku, Tokyo Japan Tel: 81 33 983 0086 IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 16907 Tel: 65 221 8371 Data and specifications subject to change without notice. 3/98

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