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| 1P AL C2 2V 10B This is an abbreviated datasheet. Contact a Cypress representative for complete specifications. For new designs, please refer to the PALCE22V10 fax id: 6006 PALC22V10B Reprogrammable CMOS PAL(R) Device Features * Advanced second generation PAL architecture * Low power -- 90 mA max. standard -- 100 mA max. military * CMOS EPROM technology for reprogrammability * Variable product terms -- 2 x (8 through 16) product terms * User-programmable macrocell -- Output polarity control -- Individually selectable for registered or combinatorial operation -- 15 ns commercial and industrial 10 ns tCO 10 ns tS 15 ns tPD 50 MHz -- 15 ns and "20 ns" military 10/15 ns tCO 10/17 ns tS 15/20 ns tPD 50/31 MHz * Up to 22 input terms and 10 outputs * Enhanced test features -- Phantom array -- Top test -- Bottom test -- Preload * High reliability -- Proven EPROM technology -- 100% programming and functional testing * Windowed DIP, windowed LCC, DIP, LCC, PLCC available Functional Description The Cypress PALC22V10B is a CMOS second-generation programmable logic array device. It is implemented with the familiar sum-of-products (AND-OR) logic structure and a new concept, the "Programmable Macrocell." The PALC22V10B is executed in a 24-pin 300-mil molded DIP, a 300-mil windowed cerDIP, a 28-lead square ceramic leadless chip carrier, a 28-lead square plastic leaded chip carrier, and provides up to 22 inputs and 10 outputs. When the windowed cerDIP is exposed to UV light, the 22V10B is erased and can then be reprogrammed. The programmable macrocell provides the capability of defining the architecture of each output individually. Each of the 10 potential outputs may be specified as "registered" or "combinatorial." Polarity of each output may also be individually Logic Block Diagram (PDIP/CDIP) V SS 12 I 11 I 10 I 9 I 8 I 7 I 6 I 5 I 4 I 3 I 2 CP/I 1 PROGRAMMABLE ANDARRAY (132X 44) 8 10 12 14 16 16 14 12 10 8 Reset Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Preset 13 I 14 I/O9 15 I/O8 16 I/O7 17 I/O6 18 I/O5 19 I/O4 20 I/O3 21 I/O2 22 I/O1 23 I/O0 24 V CC V10B-1 Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 June 1986 - Revised March 6, 1997 PALC22V10B Pin Configurations LCC Top View PLCC Top View I I I N/C I I I 5 6 7 8 9 10 11 4 3 2 1 282726 25 24 23 22 21 20 19 12131415161718 4 3 2 1 2827 26 I/O2 I/O3 I/O4 N/C I/O5 I/O6 I/O7 I I I N/C I I I 5 6 7 8 9 10 11 25 24 23 22 21 20 121314 1516 171819 I/O2 I/O3 I/O4 N/C I/O5 I/O6 I/O7 V10B-2 V10B-3 Document #: 38-00195-C (c) Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. |
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