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PM5357 S/UNI-622-POS
ERRATA PMC-2001584 ISSUE 1 S/UNI-622-POS REFERENCE DESIGN ERRATA
PM5357
S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
REFERENCE DESIGN ERRATA
ISSUE 1: DECEMBER 2000
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PM5357 S/UNI-622-POS
ERRATA PMC-2001584 ISSUE 1 S/UNI-622-POS REFERENCE DESIGN ERRATA
REVISION HISTORY Issue No. 1 Issue Date December, 2000 Details of Change This document contains errata information corresponding to the issue 2 of Reference Design document PMC-1981070. This fixes minor documentation errors, improvements and application hints.
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PM5357 S/UNI-622-POS
ERRATA PMC-2001584 ISSUE 1 S/UNI-622-POS REFERENCE DESIGN ERRATA
CONTENTS
1 2 ISSUE 1 ERRATA ........................................................................................................................... 1 REFERENCE DESIGN DOCUMENTATION DISCREPANCIES: .................................................... 2 2.1 2.2 2.3 2.4 3 TRACE IMPEDANCE SHOULD BE 50OHMS NOT 100 OHMS IN FIGURE 16 ............... 2 CHANGE THE 5V 77.76MHZ OSCILLATOR TO A LOW JITTER TYPE........................... 3 C47 CLARIFICATION IN THE BOM ................................................................................. 3 VCC TO XC1701L SHOULD BE 3.3 V AND NOT 5V ....................................................... 3
APPLICATION NOTES: .................................................................................................................. 4 3.1 3.2 3.3 CAUTION ON USING INDUCTORS TO FILTER POWER SUPPLIES............................. 4 CONNECTING A TTL SD FROM ODL TO SD PECL TYPE INPUT OF S/UNI-622-POS.. 5 INTERFACING A TTL SINGLE ENDED 77.76MHZ OSCILLATOR INTERFACE TO REFCLK+/- PECL INPUTS............................................................................................... 6
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PM5357 S/UNI-622-POS
ERRATA PMC-2001584 ISSUE 1 S/UNI-622-POS REFERENCE DESIGN ERRATA
LIST OF FIGURES
FIGURE 1: TRACE IMPEDANCE CORRECTION......................................................................................... 2 FIGURE 2: INDUCTOR TRANSIENTS MAY DAMAGE CMOS CIRCUITS ................................................... 4 FIGURE 3: INDUCTOR TRANSIENTS CLAMPED BY DIODES................................................................... 5 FIGURE 4: TTL TO PECL SD INPUT OF S/UNI-622-POS............................................................................ 6 FIGURE 5: TTL TO SINGLE ENDED PECL INTERFACE ............................................................................. 6
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PM5357 S/UNI-622-POS
ERRATA PMC-2001584 ISSUE 1 S/UNI-622-POS REFERENCE DESIGN ERRATA
1
ISSUE 1 ERRATA This issue 1 contains errata applied to the Issue 2 PMC-1981070, S/UNI-622-POS Reference Design. The issue 2 Reference Design and issue 1 errata supersede all prior editions and versions.
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PM5357 S/UNI-622-POS
ERRATA PMC-2001584 ISSUE 1 S/UNI-622-POS REFERENCE DESIGN ERRATA
2 2.1
REFERENCE DESIGN DOCUMENTATION DISCREPANCIES: Trace Impedance should be 50Ohms not 100 ohms in Figure 16 The controlled trace impedance for the RXD+/- and TXD+/- were wrongly labeled as being 100 ohms each in Figure 16 of the reference design document. In Figure 1: Trace Impedance Correction, the circled traces are shown correctly as being 50 ohms each (100 ohms differential). Figure 1: Trace Impedance Correction
Figure 16: Mixing PECL 5V and 3.3V ODL and 77MHz Oscillator 49.9 ohm, 100 ohm, R1 and R2 are external resistors and not internal to any of these devices. They are shown like this to illustrate that they must be physicaly placed past the chip pins/balls on the underside side of the PCB ferrite choke, less than 1 ohm resistance Vcc1 Vcc1
63.4
0.1F Zo = 50
4cm max TX+
49.9ohm 49.9ohm
TXDP
S/UNI-622-POS TX-
TXDN ODL RXP Vcc PECL outputs
Zo = 50
1H
Zo = 50
Rb1
RD+
+
100 Zo = 50
RDPECLV SD
10 F 0.1F
5V PECL ODL 3.3V PECL ODL
Vss
RXN Rb1 SD Rb1
Vp
Vcc1 5V 3.3V Rb 330ohm 150ohm Vp gnd 3.3V R1 68.1ohm 82.5ohm R2 196ohm 127ohm Vb1 3.7Vdc 2.0Vdc 5V OSC = Rb2= 330ohms 3.3V Osc = Rb2= 150 ohms 1 ohm Vcc2 10uF 0.1uF
Vcc1 REFCLK+ Out+ Rb2 77.7600MHz PECL OSC. 50 ohm R1 Vb1 R2
0.01F
Vcc1
0.01F
OutRb2 50 ohm REFCLK-
R1 Vb1 R2
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PM5357 S/UNI-622-POS
ERRATA PMC-2001584 ISSUE 1 S/UNI-622-POS REFERENCE DESIGN ERRATA
2.2
Change the 5V 77.76MHz Oscillator to a low Jitter type In section 16, Rev 3 BOM (Bill of Materials), page 2, under item OSC_PECL_77.76MHZ., 200ppm, column Manufacturer, remove the 5V type Saronix 99T27M. In it's place, insert (add) the following low jitter oscillator: Saronix PECL SONET oscillator with low jitter output, (3.5ps rms and 1ps cycle to cycle). Series SEL2400/SEL3400. PECL3401AA-77.76 PECL3401B-77.76 77.76 MHz, 20ppm, 0-70 C, 5V (for WAN applications) 77.76 MHz, 50ppm, 0-70 C, 5V ( for LAN applications)
2.3
C47 clarification in the BOM C47 in the BOM on page 1 of section 16 is listed as a 0.1uF X7R. It should be listed as a 10uF, 10V Tantalum.
2.4
Vcc to XC1701L should be 3.3 V and not 5V The XC1701L PROMS on page 6 of 8 of Revision 3 schematics are 3.3V type and they are connected to a 3.3V FPGA. VCC of U9, U12, U16, and U17 should be connected to 3.3VD and not to Vcc as shown. Also, R1, R2 and C1on this page should be connected to 3.3VD and not Vcc
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PM5357 S/UNI-622-POS
ERRATA PMC-2001584 ISSUE 1 S/UNI-622-POS REFERENCE DESIGN ERRATA
3 3.1
APPLICATION NOTES: Caution on using Inductors to filter power supplies. Sometimes inductors are used to filter power supplies to CMOS semiconductors and to reduce currents in hot-card insert applications. In such cases, care must be exercised to prevent damage to CMOS IC's. When power is applied to LC circuits, the ringing at the load and line side can cause voltages that exceed the chips maximum ranges and cause permanent damage to the device. Also on power down, such as hot card insertion and extraction, the voltage spikes induced by the inductor can cause permanent device damage and cause sparking at the connector/switch thus reducing component life. See figures below for more detail. Because the LC forms a tank circuit, the resultant ringing voltage could be greater than Vcc and lower than ground on both sides of the inductor as shown in Figure 2: Inductor Transients may damage CMOS circuits. Figure 2: Inductor Transients may damage CMOS circuits
Power switch or connector Vcc source Inductor CMOS load
C Over and under voltage causes damage to CMOS chip Vcc
Vcc
Switch - OFF GND Switch - OFF Switch - ON t GND Switch - ON
In Figure 2: Inductor Transients may damage CMOS circuits, D2 acts to commute the inductor voltage generated when power is abruptly removed from the primary side of the inductor. The voltage across the inductor is clamped by D2 to max 0.7V in the reverse direction. D1 acts to prevent the primary side from high voltages which may cause arcing across the switch. D3 acts to prevent the secondary side from over voltage by clamping action of the zener type device. Also, the under voltage is clamped to -0.7 V.
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PM5357 S/UNI-622-POS
ERRATA PMC-2001584 ISSUE 1 S/UNI-622-POS REFERENCE DESIGN ERRATA
Figure 3: Inductor Transients Clamped by Diodes
Power switch or connector Vcc source D1
Ultra Fast diode D2 clamped transients eliminate CMOS damage CMOS load
Inductor Fast Zener crowbar device
D3
clamped transients reduce switch wear Vcc
Vcc
GND Switch - OFF Switch - ON
t
GND Switch - OFF Switch - ON
t
3.2
Connecting a TTL SD from ODL to SD PECL type input of S/UNI-622-POS The SD input of the POS has a much bigger dynamic range than the standard true PECL receiver. Also the SD signal switches so infrequently that it can be considered as a DC signal. The figure below shows how to connect a TTL level signal to a single ended PECL input using a standard signal diode and a pullup resistor. TTL outputs typically are less than 0.4V for a low and more than 2.0V for a logic high. TTL drivers can sink a lot more current than they can source. When the ODL's TTL SD output is low (<0.4V), current is drawn through the 3.3K resistor and the diode is forward biased. The voltage on the anode side of the diode now will be less than 1.1V (ground plus 0.4V plus the diode drop of 0.7 V). A 1.1V is lower than the 1.95V LVPECL threshold and will be recognized as a low. When the TTL SD output switches high, theoretically its output will be greater than 2.4 V. The diode will be off and the voltage on the anode side of the diode will be higher than 2.4V+0.7V = 3.1V which is well above than 1.95V required for a LVPECL high.
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PM5357 S/UNI-622-POS
ERRATA PMC-2001584 ISSUE 1 S/UNI-622-POS REFERENCE DESIGN ERRATA
Figure 4: TTL to PECL SD input of S/UNI-622-POS
Vcc Vcc 3.3 Kohms Vcc SD LVPECL type input 3.3V PECLV S/UNI-622-POS PM5357 or S/UNI-622-MAX PM5356 Vcc 1.95Vdc PECL threshold 1.1V (0.4+0.7) t
SD TTL output ODL
Signal Diode
>2.0V TTL SD output <0.4V
3.3
Interfacing a TTL single ended 77.76MHz Oscillator Interface to REFCLK+/- PECL inputs In some cases, a PECL oscillator or VCXO may be substituted for a cheaper TTL type. The circuit below will interface a single ended TTL signal to the PECL-like inputs of the S/UNI's differential REFCLK+/- inputs. Filter the power supply well to the TTL clock source as any power supply noise may frequency modulate the output. Depending on the current draw, use a small 1 ohm resistor to keep the voltage drop (IR) across the resistor as low as possible. Figure 5: TTL to Single ended PECL Interface
3.3V 0.1uF 1.95Vdc 330 ohms 1 ohm 0.1uF 10uF GND 3.3V or 5V TTL 77.76MHz Source An Oscilator or VCXO keep distance as short as possible 0.1uF 158 ohms Zo=50ohm 49.9 ohms 49.9 ohms REFCLK+ Differential PECL type inputs REFCLKS/UNI-622-POS PM5357 or S/UNI-622-MAX PM5356 PECLV Vcc 220 ohms
3.3V or 5V
Vcc
TTL output
3.3V >2.4V 1.95Vdc 0.8Vp-p <0.4V 77.76 MHz TTL Signal at TTL Source f
Attenuated, level shifted 77.76 MHz TTL Signal at REFCLK+ POS input
f
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PM5357 S/UNI-622-POS
ERRATA PMC-2001584 ISSUE 1 S/UNI-622-POS REFERENCE DESIGN ERRATA
The TTL signal has to be attenuated from about 2.4Vdc p-p about to 0.8 Vp-p. This is done as a simple resistor divider using the 158 ohms and 49.9 ohms. Then we have to ac couple to level shift so that the 0.8V signal is centered around 1.95Vdc, which is the sweet spot of the PECL like differential receivers of the S/UNI device. The single ended signal is terminated into the 49.9 (50 ohm) resistor to reduce reflections and thus jitter. The REFCLK- input is biased at the mid point of the LVPECL at 1.95 V. So the input at REFCLK+ will swing above and below this voltage at REFCLK-. Do not use a TTL to PECL converter chip as it will generate too much jitter for this application.
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PM5357 S/UNI-622-POS
ERRATA PMC-2001584 ISSUE 1 S/UNI-622-POS REFERENCE DESIGN ERRATA
CONTACTING PMC-SIERRA, INC. Please report any functional discrepancies or datasheet errors to: PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200
Document Information: document@pmc-sierra.com Corporate Information: info@pmc-sierra.com Application Information: apps@pmc-sierra.com (604) 415-4533 Web Site: http://www.pmc-sierra.com
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 1999,2000 PMC-Sierra, Inc. PMC-2001584 (R1) ref PMC-1981070 (R2) Issue date: October, 2000
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