View 1951042_963768.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PMC-Sierra, Inc.
APPLICATION NOTE ISSUE 3
PM7975 NIC
LASAR Opitcal Network Interface Card (NIC)
PM7375 LASAR155
TM
LASAR OPTICAL NETWORK INTERFACE CARD (NIC) REFERENCE DESIGN
Preliminary Information Issue 3: March 1996
PMC-Sierra, Inc.
8501 Commerce Court, Burnaby, BC Canada V5A 4N3 604 668 7300
PMC-Sierra, Inc.
APPLICATION NOTE ISSUE 3
PM7975 NIC
LASAR Opitcal Network Interface Card (NIC)
CONTENTS LIST OF CHANGES ........................................................................................................1 REFERENCES .................................................................................................................1 1. 2. 3. OVERVIEW...............................................................................................................2 FUNCTIONAL DESCRIPTION..............................................................................3 BOARD LAYOUT DESCRIPTION ........................................................................6
APPENDIX A: BILL OF MATERIAL ...............................................................................9 APPENDIX B: SCHEMATICS........................................................................................14 APPENDIX C: LAYOUT ..................................................................................................15
PMC-951042
i
Issue 3
PMC-Sierra, Inc.
APPLICATION NOTE ISSUE 3
PM7975 NIC
LASAR Opitcal Network Interface Card (NIC)
LIST OF CHANGES The following changes have been made to the issue 2 of the document: Document Changes * * * * Updated schematics Updated layout Added functional and layout description of the NIC card Added bill of material
Schematic Changes * * * * * Removed all headers Removed U4 and its decoupling caps and pullups Changed regulators to 1.5 A 7805 TO220 packages Add additional solder bridges and decoupling caps Added chassis ground points
Layout Changes * * * re-routed the analog portion of the PM7375 for manufacturability redefined the power and ground planes moved the location of U1 and the two bracket mounting holes
REFERENCES PCI Special Interest Group, "PCI Local Bus Specification Revision 2.0", April 30, 1993 PMC-931127, LASAR-155 Longform Datasheet, Issue 3, March 5, 1996
PMC-951042
1
Issue 3
PMC-Sierra, Inc.
APPLICATION NOTE ISSUE 3
PM7975 NIC
LASAR Opitcal Network Interface Card (NIC)
1. OVERVIEW The PM7975 LASAR Optical Network Interface Card (NIC) is a Peripheral Component Interconnect (PCI) Bus Local ATM network interface card which contains the PM7375 Local Segmentation and Reassembly & Physical Layer device (LASAR-155) and an optical PMD to provide a local ATM network interface using SONET/SDH framing at 155.52 or 51.84 Mbit/s and ATM Adaptation Layer 5 (AAL5). The PCI bus interface is compliant with the PCI SIG Specification Rev. 2.0 and provides scatter/gather DMA of packets. The LASAR-155 device implements SONET/SDH transmission convergence, ATM cell mapping, ATM Adaptation Layer, and PCI Bus memory management functions for a 155.52 or 51.84 Mbit/s ATM User Network Interface (UNI). The NIC is configured, monitored, and powered through a 5 Volt/32bit PCI connector. The PMD deploys a standard 9-pin single-mode or multi-mode optical transceiver module. An on-board oscillator provides a reference for the LASAR-155's integrated clock and data recovery unit on the receive side, and the clock synthesis unit on the transmit side.
PMC-951042
2
Issue 3
PMC-Sierra, Inc.
APPLICATION NOTE ISSUE 3
PM7975 NIC
LASAR Opitcal Network Interface Card (NIC)
2. FUNCTIONAL DESCRIPTION 2.1. Block Diagram
PCI Rev. 2.0 5V/32-bit Connector Interface
PCI I/F Pins
LASAR-155
ALOS-
SD
tx line bit serial TXD+
TXDTRCLK-
Optics
PECL Buffer
Tx+ Tx-
TXD+/-
RXD+/Rx+ Rx-
rx line RXD+ bit serialRXDRRCLK-
74FCT541 19.44 MHz Osc
2.2.
LASAR-155 (U2)
The LASAR-155 is a single-chip Peripheral Component Interface (PCI) Bus Local ATM Network Interface using SONET/SDH framing at 155.52 or 51.84 Mbit/s and ATM Adaptation Layer 5 (AAL-5). For a complete description of the LASAR-155, please refer to PMC-931127, LASAR-155 Longform Datasheet. The NIC implements the following features of the LASAR: * Implements the ATM Physical Layer according to the ATM Forum User Network Interface Specification and ITU-TS Recommendation I.432, and the ATM
3
Issue 3
PMC-951042
PMC-Sierra, Inc.
APPLICATION NOTE ISSUE 3
PM7975 NIC
LASAR Opitcal Network Interface Card (NIC)
Adaptation Layer Type 5 (AAL-5) for Broadband ISDN according to ITU-TS Recommendation I.363. * * Supports multimode or single mode optical modules or twisted pair wiring (UTP5) modules. Directly supports a 32-bit PCI compliant bus interface for configuration, monitoring and transfer of packet data, with an on-chip DMA controller with scatter/gather capabilities. Using the LASAR-155's on-chip 96 cell receive buffer to accommodate up to 270 s of PCI Bus latency. Supports simultaneous segmentation and reassembly of 128 virtual circuits (VCs) in both transmit and receive directions. Provides leaky bucket peak cell rate enforcement using 8 programmable peak queues coupled with sub peak control on a per VC basis; provides sustainable cell rate enforcement using the programmable peak cell rate queues and per VC token bucket averaging; and provides aggregate peak cell rate enforcement. Line Interface
* * *
2.3.
The receive line interface consist of PECL outputs of the PMD transceiver module terminated and ac coupled into the RXD+/- inputs of the LASAR-155. To ensure that there is a clock in the absence of incoming signal, the signal detect (SD) output of the PMD transceiver is connected to the ALOS- input of the LASAR-155 while the ALOS+ input is ac coupled to ground. In normal operation (good incoming signal) the LASAR-155 recovers the clock from the incoming data. Under the loss of signal condition, the LASAR-155 will squelch the data on the receive data (RXD+/-) pins and its phase locked loop will switch to the reference clock (19.44 MHz) to keep the recovered clock in range. This technique guarantees that the LASAR-155 will generate a Loss Of Signal (LOS) indication when the PMD transceiver device loses incoming signal. The transmit line interface consist of the LASAR-155's CMOS transmit outputs which are AC-coupled, attenuated, terminated, buffered via a PECL buffer (100EL16), and connected to the PECL inputs of the PMD transceiver module. The 100EL16 is used because the long trace length (high capacitance),which the TXD+/- CMOS outputs will otherwise have to drive, will affect the rise and fall time of TXD+/- outputs. As a result, the 100EL16 is placed near the LASAR-155 to provide buffering for the TXD+/- CMOS outputs and drive the 50 Ohm transmission lines to the PMD transceiver module's PECL inputs. The PMD transceiver module can be a single-mode or multi-mode optical transceiver, or a UTP5 transceiver of the same footprint.
PMC-951042
4
Issue 3
PMC-Sierra, Inc.
APPLICATION NOTE ISSUE 3
PM7975 NIC
LASAR Opitcal Network Interface Card (NIC)
2.4.
Oscillator (Y1)
The 19.44 MHz TTL oscillator provides a reference to the clock and data recovery circuitry of the LASAR-155 on the receive side, and clock synthesis circuitry of the LASAR-155 on the transmit side via a 74FCT541 8-bit buffer/line driver. The outputs of the buffer are series terminated and connected to the RRCLK- and TRCLK- inputs of the LASAR-155, while its RRCLK+ and TRCLK+ inputs are connected to their respective ground. 2.5. PCI Connector and LED
The PCI connector is configured as a 5 Volt/32-bit, PCI SIG Rev. 2.0 compliant expansion daughter card edge connector. The on board LED is driven directly by the receive alarm (RALM) output of the LASAR-155. The LED is on when RALM output of the is high (under loss of signal, line AIS, path AIS, loss of frame, loss of pointer, or loss of cell delineation state), and off when RALM output is low. A low power LED should be deployed if a buffer is not used.
PMC-951042
5
Issue 3
PMC-Sierra, Inc.
APPLICATION NOTE ISSUE 3
PM7975 NIC
LASAR Opitcal Network Interface Card (NIC)
3. BOARD LAYOUT DESCRIPTION The NIC has four layers: (from the top down) layer 1 and 4 for signals, layer 2 for ground plane, and layer 3 for power planes. The dimension of the NIC conforms to the 5V PCI Raw Short Card, with custom mounting hole locations. the NIC layout follows high speed signal layout guide lines as well as the PCI Rev. 2.0 Spec. layout restrictions. The PCI SIG specification has stringent and detailed rules on decoupling, power consumption, trace length limits, routing, trace impedance, as well as signal loading. Therefore, it is essential to consult the latest PCI specification before proceeding with new designs and layouts. 3.1. Power and Ground Distribution
Discrete transmit, receive, and digital power planes can be connected together using solder bridges. The power coming off the PCI bus 5 Volt power supply pins is also isolated by solder bridges or Schottky diodes from the rest of the board. In addition, the transmit and receive section can also be powered through their respective voltage regulators which draw their power from the +12 Volt supply pin on the PCI bus. One continuous ground plane is used with cuts to isolate the transmit and receive analog grounds from each other as well as from the digital grounds. The oscillator, the 74FCT541 buffer, the transmit analog sections of the PMD transceiver and the LASAR-155 share the same transmit analog power and ground planes. The receive sections of the PMD transceiver and the LASAR-155 share the same receive analog power and ground planes. All of LASAR-155's analog power supply pins use ferrite beads to filter out Vcc noise. A 0.1 uF bypassing capacitor is placed near each ferrite bead supply its respective analog Vcc pin, while a 0.01 uF decoupling capacitor is placed near each analog or digital Vcc pin. In addition, ferrite beads are used on transmit and receive analog ground pins of the LASAR-155 to reduce ground noise. The solder bridge are shown below: Solder Bridge SB1, SB11, SB10, & SB9 SB15 Purpose Vcc from PCI connector to board digital Vcc plane connects output of regulator U5 to the receive analog power plane Standard Configuration open short
PMC-951042
6
Issue 3
PMC-Sierra, Inc.
APPLICATION NOTE ISSUE 3
PM7975 NIC
LASAR Opitcal Network Interface Card (NIC)
SB5 & SB6
connect receive analog power plane to digital power plane connects output of regulator U4 to the transmit analog power plane connect transmit analog power plane to digital power plane connect PMD module (optical or utp5) mounting pins to chassis ground connect PMD module (optical or utp5) mounting pins to board ground
open
SB14
short
SB2 & SB4
open
SB3 & SB7
short
SB12 & SB8
open
With the standard configuration, the receive and transmit analog planes are powered via regulators U5 and U4 separately. The mounting posts of the PMD transceiver is connected to the chassis ground via a chassis ground island placed under the PMD transceiver device on the ground plane and the solder bridges SB3 and SB7. 3.2. * Component Placement
The LASAR-155 device is placed such that all the PCI interface traces are within the specified length limits of the PCI Rev. 2.0 Spec., while being as close to the PMD transceiver as possible. The PECL buffer (U3) is placed close to the LASAR-155 TXD+/- outputs to reduce the transmission line lengths these two CMOS outputs have to drive. The 74FCT541 buffer is placed between the transmit and receive analog sections of the LASAR-155 so that each of its two outputs can be routed to the transmit or receive reference clock inputs without crossing any discontinuity on the power or ground planes which serve as image planes for return currents as well as to control the impedance of the transmission lines. The oscillator (Y1) is placed near the 74FCT541 inputs on the transmit analog section. LASAR-155 loop filter components are placed near the chip on the same side. All termination resistors are placed as close to the inputs as possible on the same side.
7
Issue 3
* *
* * *
PMC-951042
PMC-Sierra, Inc.
APPLICATION NOTE ISSUE 3
PM7975 NIC
LASAR Opitcal Network Interface Card (NIC)
*
All pull down resistors are placed near the LASAR-155 output pins. Routing and Termination
3.3. * *
All high speed traces are routed over continuous image planes (power or ground planes) All traces carrying transmit and receive data are transmission lines with 50 Ohm controlled impedance. These traces should be routed on the same side and kept as short as possible. All differential signals are of the same length and routed close to each other. Reference clock signals from the 74FCT541 are 75 Ohm transmission lines with series termination. Two termination schemes are provided for the PECL signals to and from the PMD transceiver. One scheme is the 50 Ohm Thevenin equivalent termination (81 Ohm to Vcc in series with 130 Ohm to ground), and the other scheme uses 330 Ohm pull downs and 100 Ohm termination. All PCI signal traces have an impedance of 75 Ohms +/- 10%
* * *
*
PMC-951042
8
Issue 3
PMC-Sierra, Inc.
APPLICATION NOTE ISSUE 3
PM7975 NIC
LASAR Opitcal Network Interface Card (NIC)
APPENDIX A: BILL OF MATERIAL Item Refdes Total Description 1 C15 1 Capacitor, 100uF, electrolytic, Radial leads, 0.196" spacing, 25 Volts rating preferred, 16 Volts is the next preferred rating if 25 Volt caps are not available. 2. C28 2 Capacitor, 47uF, electrolytic, Radial leads, 0.196" C66 spacing, 25 Volts rating preferred, 16 Volts is the next preferred rating if 25 Volt caps are not available. 3 P1 1 Refers to the PCB itself, no parts required. 4 Y1 1 19.44 MHz, 20 ppm, DIP Osc, 0.26" case, 14 pins DIP, TTL levels, Connor Winfield, S54R8-19.44MHz, or equivalent 19 Ferrite Beads, surface mount, 0.2", Fair_rite 5 L1 #2743019446. L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L13 L14 L15 L16 L17 L18 L19 L20 6 D2 2 3.0 A max average rect. current D4 20 Volts max peak reverse voltage approximately 0.475 peak max. forward voltage DO-201AD package 7 U1 1 Fiber Optics transceiver, 9 Pins, HP HFBR5205 8 D1 1 Lower power LED, red, 0.1" spacing, 1 - 5 mA operating current 9 U2 1 PM7375, LASAR-155, 0.50 mm pitch, 208 pin PQFP, PMC-Sierra 10 J7 2 pcb mount SMA connectors J9
PMC-951042
9
Issue 3
PMC-Sierra, Inc.
APPLICATION NOTE ISSUE 3
PM7975 NIC
LASAR Opitcal Network Interface Card (NIC)
11
C8 C17 C20 C22 C27 C33 C39 C42 C44 C47 C50 C53 C55 C58 C61 C62 C63 C67 C68 C71 C74 C76 C78 C79 C80 C81 C82
27
Capacitors, 0.1 uF MultiLayer Ceramic chip capacitor, 50V, Size 1206, Surface mount
PMC-951042
10
Issue 3
PMC-Sierra, Inc.
APPLICATION NOTE ISSUE 3
PM7975 NIC
LASAR Opitcal Network Interface Card (NIC)
12
13
C2 C3 C5 C10 C11 C12 C13 C14 C16 C18 C19 C23 C24 C25 C26 C29 C30 C31 C32 C34 C35 C36 C37 C40 C41 C43 C45 C46 C48 C51 C52 C56 C57 C59 C60 C64 C65 C69 C70 C72 C75 C77 C7 C21 C38
42
Capacitors, 0.01 uF MultiLayer Ceramic chip capacitor, 50V, Size 805, Surface mount
3
Capacitors, 47 pF MultiLayer Ceramic chip capacitor, 50V, Size 805, Surface mount
PMC-951042
11
Issue 3
PMC-Sierra, Inc.
APPLICATION NOTE ISSUE 3
PM7975 NIC
LASAR Opitcal Network Interface Card (NIC)
14 15 16 17
C1 C4 R31 R6 R16 R27 R33 R35 R37 R42 R25 R26 R34 R28 R9 R13 R17 R21 R22 R5 R8 R36 R12 R38 R39 R23 R40 R41 R44 R29 R43 R45 R46 C49 C54 C73 C83 C84
value to be determined 2 1 2 5 Resistors, 27 ohm 1/10 watt MF 5%, Size 805, Surface mount Resistors, 100 ohm 1/10 watt MF 1%, Size 805, Surface mount Resistors, 10K ohm 1/10 watt MF 5%, Size 805, Surface mount
18 19 20 21
1 2 1 5
Resistor, 160 ohm 1/10 watt MF 1%, Size 805, Surface mount Resistors, 237 ohm 1/10 watt MF 1%, Size 805, Surface mount Resistors, value dependent on the LED used, 1/10 watt MF 5%, Size 805, Surface mount Resistors, 330 ohm 1/10 watt MF 1%, Size 805, Surface mount
22 23 24 25
3 1 2 4
Resistor, 49.9 ohm 1/10 watt MF 1%, Size 805, Surface mount Resistor, 68.1 ohm 1/10 watt MF 1%, Size 805, Surface mount Resistors, 75.0 ohm 1/10 watt MF 1%, Size 805, Surface mount Resistor, 81 ohm 1/10 watt MF 1%, Size 805, Surface mount Resistors, 130 ohm 1/10 watt MF 1%, Size 805, Surface mount Capacitors Pol. 10 uF, Panasonic TEH series, Resin molded chips tantalum electrolytic capacitor, EIA Size C, surface mount, 25 Volts or 16 Volts. 25 Volt rating preferred; 16 Volt is the next preferred rating
26
4
27
5
PMC-951042
12
Issue 3
PMC-Sierra, Inc.
APPLICATION NOTE ISSUE 3
PM7975 NIC
LASAR Opitcal Network Interface Card (NIC)
28
C6 C9 RN3 U6 U3 U4 U5 Q1 SB1 SB2 SB3 SB4 SB5 SB6 SB7 SB8 SB9 SB10 SB11 SB12 SB14 SB15 TP1 TP2 TP6 TP8 TP10 TP12
2 1 1 1 2 1 14
29 30 31 32 33 34
Capacitors Pol. 6.8 uF, Panasonic TEH series, Resin molded chips tantalum electrolytic capacitor, EIA Size C, Surface mount, 25 Volt rating preferred; 16 Volt is the next preferred rating Chip-resistor array, 10K ohm x 8, SOIC package, 8 resistors in 1 package non-inverting 8-bit buffers/line drivers, Cypress, CY74FCT541, 20 pin SOIC, or equivalent PECL buffer, MC100EL16 or equivalent, 8 pin SOIC 7805, Positive 5 Volt, 1.5 AMP voltage regulator, TO220 package Discrete Transistor, NPN, SOT23 package, surface mount solder bridges
35
6
test points
PMC-951042
13
Issue 3
PMC-Sierra, Inc.
APPLICATION NOTE ISSUE 3
PM7975 NIC
LASAR Opitcal Network Interface Card (NIC)
APPENDIX B: SCHEMATICS
PMC-951042
14
Issue 3
10
9
8
7
6
5
4
3
2
1
NOTE: PLACE ALL THE TERMINAL RESISTOR OR NETWORK AS CLOSE TO SIGNAL END PINS AS POSSIBLE Y1 POWER GND U6 A1 A2 A3 A4 A5 A6 A7 A8 R38 75 2 VCC
2D10< 2C10<
REVISIONS
ZONE
V_+12V VCC V_TAVD<3..1> V_RAVD<4..1>
2B7> 2A7>
REV
A1 A2 A3 A4 A5
DESCRIPTION
-12V TCK GROUND TDO +5V +5V INTB# INTD# PRSNT1# RESERVED PRSNT2# GROUND GROUND RESERVED GROUND CLK GROUND REQ# +5V AD[31] AD[29] GROUND AD[27] AD[25] +3.3V C/BE[3]# AD[23] GROUND AD[21] AD[19] +3.3V AD[17] C/BE[2]# GROUND IRDY# +3.3V DEVSEL# GROUND LOCK# PERR# +3.3V SERR# +3.3V C/BE[1]# AD[14] GROUND AD[12] AD[10] GROUND
B1 B2 B3 B4 B5 B6 B7 2 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 24 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 9 13 12 11 10 15 14 18 17 16 22 21 20 19 23 28 27 26 25 31 30 29
DATE
APPR
H
2C4>
V_CLK
14 7
OUT
8
TA
TTL/CMOS_19.44MHZ
V_TXVDD
H
2 3 4 5 6 7 8 9 1 19 10
Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
18 17 16 15 14 13 12 11 20 7 6
1
1 2
75 OHM 75 OHM
R39 U3
75
TRST# +12V TMS TDI +5V INTA# INTC# +5V RESERVED +5V RESERVED GROUND GROUND RESERVED RST# +5V GNT# GROUND RESERVED AD[30] +3.3V AD[28] AD[26] GROUND AD[24] IDSEL +3.3V AD[22] AD[20] GROUND AD[18] AD[16] +3.3V FRAME# GROUND TRDY# GROUND STOP# +3.3V SDONE SBO# GROUND PAR AD[15] +3.3V AD[13] AD[11] GROUND AD[09]
MC100EL16
PCI_5V_32BIT_CARD_CONNECTOR P1 CONNECTED TO CONNECTED TO BOARD VCC VIA SOLDER BRIDGE PCIVCC
1
VCC Q QB D DB
8 2 3 2
R13 330 2
R9 330 2
R5 49.9 R26
R36 49.9
1
1
1
0.01UF C3
C62 0.1UF
2
0.01UF
2B9
BUFFER DRAWS POWER FROM TRANSMIT SECTION TX
1
237 R34
237
TA
VC G1 G2 G 74FCT541
4
2
2
VBB VEE TA
5
2
123
U2 VDD_AC<16..1> VDD_DC<10..1> TAVD<3..1> RAVD<4..1> TXVDD TA
120 121
PM7375
A6 A7 A8
+C15 100UF
1
1
TXVBB TA
2
C14 TA 0.01UF
2C4>
V_BUTX
TA
C5
TRCLKP TRCLKN TXDP TXDN ALOSN ALOSP RRCLKP RRCLKN RXDP RXDN
1
1
1
1 2
ROMP
132
A9 A10
2
G 2D4>
2E4>
OPRX OPTX
6 5 2
TX BUFFER +/- SWAPPED AT BOTH INPUTS AND OUTPUTS 50_OHM 100 R6 50 OHM
1
TXDP TXDN
126 127 139 138
TRSTB TCK TMS TDI TDO PCIINTB
74 72 73 71 70 195
TRSTB TCK
A11 A12 A13
G
TMS
A14
U1 TX_VCC RX_VCC TXDP TXDN SD RXDP RXDN
8 7 4 2 3
NOTE: ALTERNATIVE TERMINATION INDICATED 50_OHM 50_OHM 50_OHM BELOW RA
TXODP TXODN SD RXODP RXODN R17 330 2 R21 330 R22 330
2
C2 RA 0.01UF RRCLKN
2
142 143
TDI TDO PCIINTB
A15 A16 A17 A18 A19
1
C10 R16 100 1
1
10 11
CHASIS1 CHASIS2
50 OHM 50 OHM VCC
2 1
2 136 0.01UF 137
C12
1 2
2
2
0.01UF R33 10K MPENB RXPHYBP RFIFOEB TXPHYBP TFIFOEB XOFF
153 152 93 92 75 114
RSTB MPENB RXPHYBP RFIFOEB TXPHYBP TFIFOEB XOFF RDAT<7..0> PCICLK GNTB REQB
124 198 200 201
RSTB PCICLK GNTB REQB
A20 A21 A22 A23 A24 A25 A26
F
F
1
1
RA
1 3
RA
2 4
RA
SB8 P<1> P<2> P<3> P<4>
SOLDER_BRIDGE
2 4
1 3
SB12 P<1> P<2> P<3> P<4>
SOLDER_BRIDGE
1
VCC RN3
1 2 3 4 5 6 7 8
RES_ARRAY_8
10K
16 15 14 13 12 11 10 9
1 3
SB7 P<1> P<2> P<3> P<4>
SOLDER_BRIDGE
2 4
1 3
SB3 P<1> P<2> P<3> P<4>
SOLDER_BRIDGE
2 4
RXPHYBP TXPHYBP RFIFOEB XOFF RRDENB TFIFOEB
3
R31 27
1 196 2
A27 A28
RRDENB
108 107
RRDENB RSOC TDAT<7..0>
PCICLKO SYSCLK
81
SYSCLK
A29 A30 A31
E
91
NOTE
1
TWRENB TSOC RALM RCP RGFC RFP RCLK TCLK TFPO TCP TGFC TXC
IDSEL
12
IDSEL
A32 A33
E
2
90
1.0K
TP2 CHASIS GND T
TP1 CHASIS GND T
R28
1. 2. 3. 4.
PLACE ALL PULL DOWNS CLOSE TO THE SOURCE PLACE ALL TERMINATION RESISTORS CLOSE TO THE INPUTS ALL TRANSMISSION LINES ARE 50 OHMS PLACE ALL DECOUPLING CAPS CLOSE TO THE POWER PINS
D1
2 2
1
448P
1
157 110 111 109 96 155 158 112
PM7375 LASAR
FRAMEB IRDYB TRDYB DEVSELB STOPB LOCKB
29 30 31 32 33 34
FRAMEB IRDYB TRDYB DEVSELB STOPB LOCKB PERRB SERRB PAR
A34 A35 A36 A37 A38 A39 A40
1
D
PERRB SERRB PAR
35 36 37
A41 A42 A43 A44 A45
D
1
R35 10K
2
113 125
NOTE
ALTERNATIVE TRANSMISSION LINE TERMINATION
VCC IF THE FOLLOWING TERMINATION SCHEME IS USED DO NOT POPULATE R6, R9 & R13 TXODP
2 2 1 1
1
VCC
R37 10K 1 2
159 162
INTB RDB WRB CSB/CS1B ALE/CS2B A<8..0> D<8..0> D/A<15..9>
AD<31..0> C/BEB<3..0>
AD<31..0> C/BEB<3..0> Q1
3
A46 A47 A48 A49
10K R27
163 2 2
CSB
161 160
C 130 R23 R46 81
21 21
LFO VSS_AC<16..1> VSS_DC<12..1> LFN LFP TXVSS TAVS<3..1> RAVS<4..1>
147 148 2 1 149
1
1
R42 10K
2N3904
2 2
C C7 47PF
A52 A53 A54 A55
C/BE[0]# +3.3V AD[06] AD[04] GROUND AD[02] AD[00] +5V REQ64# +5V +5V
AD[08] AD[07] +3.3V AD[05] AD[03] GROUND AD[01] +5V ACK64# +5V +5V
B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62
8 0 7 6 5 4 3 2 1 0
2B9
TX 81
R12
2
TA R29
+ 68
2 1
R41
130
R25
160
C9 6.8UF
2
RA
11
TXODN
49.9
R8
A56 A57 A58 A59 A60 A61 A62
1
1
128
RA B IF THE FOLLOWING TERMINATION SCHEME IS USED DO NOT POPULATE R17, R21 & R16 RXODP
2 2
2
RA
1
+
C6 6.8UF
2B7> 2A7> 2B4> 2D7> 2C7> 2B3>
TAVS<3..1> RAVS<4..1>
TA V_RAVD<2>
2C7>
B
R44
130
R45
21
2D9
21
RX 81
NOTE
RA CHECK THE LATEST PCI SPEC FOR COMPONENT AND LAYOUT RESTRICTIONS
81
R40
130
R43
PMC-Sierra, Inc.
DRAWING TITLE=LASAR_REF ABBREV=LORD LAST_MODIFIED=Thu Apr DOCUMENT NUMBER: PMC951042 ISSUE: ISSUE 3 DATE: A
1
RXODN A
1
4 10:31:09 1996
TITLE: LASAR OPTICAL REFERENCE DESIGN MAIN ENGINEER: Y. SUE 2
96/02/27 OF 2
PAGE: 1 TRUE 1
10
9
8
7
6
5
4
3
10
9
8
7
6
5
4
3
2
1
REVISIONS
NOTE H FOR TESTING PURPOSE ONLY LASAR SIDE VCC
2H4> 1H1
PCI CONNECTOR SIDE
LASAR SIDE VCC
PCI CONNECTOR SIDE
2H6> 1H1
ZONE
REV
DESCRIPTION
DATE
APPR
H
1 3
SB1 P<1> P<2> P<3> P<4>
SOLDER_BRIDGE
2 4
PCIVCC D2
PCIVCC
SOLDER BRIDGE ADDED TO ALLOW TX AND RX TO BE CONNECTED TO VCC AS AN OPTION
1 3
SB11 P<1> P<2> P<3> P<4>
SOLDER_BRIDGE
2 4
2
1
1N5820 D4 SB5 P<1> P<2> P<3> P<4>
SOLDER_BRIDGE
1 3
SB10 P<1> P<2> P<3> P<4>
SOLDER_BRIDGE
VCC
2 4
2 4
2
1
2D9
RX
G
1N5820
1 3
G VCC
2 4
1 3
SB9 P<1> P<2> P<3> P<4>
SOLDER_BRIDGE
2 4
2D9
RX
1 3
SB6 P<1> P<2> P<3> P<4>
SOLDER_BRIDGE
VCC
DECOUPLING FOR VDD_AC SB4 P<1> P<2> P<3> P<4>
SOLDER_BRIDGE
VCC
2 4
2B9
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
TX
1 3
F
F VCC
2 4
C24 0.01UF
2 2
C30 0.01UF
2
C35 0.01UF
2
C41 0.01UF
2
C46 0.01UF
2
C52 0.01UF
2
C59 0.01UF
2
C64 0.01UF
2
C69 0.01UF
2
C72 0.01UF
2
C31 0.01UF
2
C36 0.01UF
2
C75 0.01UF
2
C70 0.01UF
2
C56 0.01UF
2
C16 0.01UF
2B9
TX
1 3
SB2 P<1> P<2> P<3> P<4>
SOLDER_BRIDGE
VCC
DECOUPLING FOR VDD_DC
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
E
C19 0.01UF
C13 C57 0.01UF 0.01UF
C51 0.01UF
C45 0.01UF
C40 0.01UF
C34 0.01UF
C29 0.01UF
C23 0.01UF
C18 0.01UF
2
+C84 +C83 10UF 10UF
2
1
+C73 10UF
C68 C80 0.1UF 0.1UF
2 2 2
1
C63 0.1UF E
2
DECOUPLING FOR OPTICS RECEIVE VCC
1 1
1 3
SB15 P<1> P<2> P<3> P<4>
SOLDER_BRIDGE
2B9 TX
2 4 1 1
1
L3 FB
2
OPTX C25 0.01UF
C76 0.1UF
2
C71 0.1UF
2
C20 0.1UF
2 2
1G10>
FOR TEST PURPOSES ONLY J7
5 2
RA V_+12V
1H4>
RA
1
RX U5
1 3 1 1 1
1
2D9 RX
DECOUPLING FOR RAVD L8 FB
2 1 1
FB V_RAVD<4>
1H5<
INPUT
OUTPUT GND
2
TP10 GND T
SMA
4 1 1 1 5
J9
2
1
L2
2
TA DECOUPLING FOR OPTICS TRANSMIT VCC OPRX 1G10> C8 C11 0.01UF 0.1UF
2 2
3
13
TP6 T GND D
1
D
2
2
+
2
+
2
2B3> 1B6<
2
2
47UF
7805
10UF
0.1UF
1
L7 FB
RA
2 1 1
TBD
2 1
14
C66
C4 TP8 T SIG
V_RAVD<3> C43 0.01UF RAVS<3>
C82 0.1UF
2 2
1H5< 2B9
1
TP12 T SIG
TX
1
1H4>
V_+12V
1
1
RA L6 FB
2 2 1 1 1 1 1 1
1
2B3> 1B6<
L5 FB
2
DECOUPLING FOR V_CLK V_CLK C37 0.01UF
1H10<
1
V_RAVD<2> C38 47PF RAVS<2>
C58 0.1UF
2 2
C53 0.1UF
2
C50 0.1UF
2
C42 0.1UF
2
C22 0.1UF
C81 0.1UF
2
1B4<
1H5<
C44 0.1UF
2 2
TA
2B3> 1B6<
1
1
1
RA
1 1
L9 FB
C
1 3
1
L4 FB
2
DECOUPLING FOR V_BUTX V_BUTX
1G10<
2
V_RAVD<1> C32 0.01UF RAVS<1>
1
C54
C47
C17 0.1UF
C48 0.01UF RAVS<4>
RA
C1 TBD
SMA
V_+12V
1H4>
SB14 P<1> P<2> P<3> P<4>
SOLDER_BRIDGE
2 4
C79 0.1UF
2 2
1H5<
C27 0.1UF
2 2
C77 0.01UF TA
C
RA DECOUPLING FOR TAVD
2B3> 1B6<
U4
1
INPUT
OUTPUT GND
2
3 1 1
1
L16 FB
2
1
1
V_TAVD<3> C26 0.01UF TAVS<3>
2
2
+C28
+C49
C33 0.1UF
TX TA
1
C61 0.1UF L15 FB
2
1H5<
1
2B4> 1B6<
2
2
2
47UF B
7805
10UF
2
1
1
V_TAVD<2> C21 47PF TAVS<2>
C55 0.1UF
2
1H5<
1 1
L20 FB L18 FB L13 FB
1 2 2 3 2
L19
2
TAVS<3..1>
4
RAVS<4..1>
2C7> 2D7> 1B6<
2A7> 2B7> 1B6<
1
FB L17 FB L10 FB L1 FB
2
3
B DRAWING TITLE=LASAR_REF ABBREV=LORD LAST_MODIFIED=Mon Apr 1 09:36:41 1996
TA
1
2B4> 1B6<
L14 FB
2
1
1
V_TAVD<1> C65 0.01UF
1
2
1
1
2
2
C67 0.1UF
2 2
1H5<
1
2
1
1
1
1
1
C74 0.1UF
2
C78 0.1UF TA
2
TAVS<1> C60 0.01UF
1
L11 FB
TA
2
2B4> 1B6<
TA
1H5<
RA
V_TXVDD
TA
C39 0.1UF
2
PMC-Sierra, Inc.
ONE SOLID PLANE WITH CUTS DOCUMENT NUMBER: PMC951042 ISSUE: ISSUE 3 DATE: A
TA A DECOUPLING FOR TXVDD
2
TA
RA
TITLE: LASAR OPTICAL REFERENCE DESIGN POWER SUPPLY & DECOUPLING ENGINEER: Y. SUE 2
96/02/27 OF 2
PAGE: 2 TRUE 1
10
9
8
7
6
5
4
3
PMC-Sierra, Inc.
APPLICATION NOTE ISSUE 3
PM7975 NIC
LASAR Opitcal Network Interface Card (NIC)
APPENDIX C: LAYOUT
PMC-951042
15
Issue 3
PMC-Sierra, Inc.
APPLICATION NOTE ISSUE 3
PM7975 NIC
LASAR Opitcal Network Interface Card (NIC)
NOTES Contact us for ATM support. Fax Phone (604)668-7301 (604)668-7300
Internet apps@pmc-sierra.bc.ca
Seller will have no obligation or liability in respect of defects or damage caused by unauthorized use, mis-use, accident, external cause, installation error, or normal wear and tear. There are no warranties, representations or guarantees of any kind, either express or implied by law or custom, regarding the product or its performance, including those regarding quality, merchantability, fitness for purpose, condition, design, title, infringement of thirdparty rights, or conformance with sample. Seller shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon, the information contained in this document. In no event will Seller be liable to Buyer or to any other party for loss of profits, loss of savings, or punitive, exemplary, incidental, consequential or special damages, even if Seller has knowledge of the possibility of such potential loss or damage and even if caused by Seller's negligence. (c) 1996 PMC-Sierra, Inc. PMC-951042 Printed in Canada Issue date: March, 1996
PMC-Sierra, Inc.
8501 Commerce Court, Burnaby, BC Canada V5A 4N3 604-668-7300

▲Up To Search▲

Price & Availability of 1951042

	To Download 1951042 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .