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19-1315; Rev 1; 12/97
Low-Power, Dual, 10-Bit, Voltage-Output DACs with Serial Interface MAX5158/MAX5159
_______________General Description
The MAX5158/MAX5159 low-power, serial, voltageoutput, dual, 10-bit digital-to-analog converters (DACs) consume only 500A from a single +5V (MAX5158) or +3V (MAX5159) supply. These devices feature Rail-toRail(R) output swing and are available in a space-saving 16-pin QSOP package. To maximize dynamic range, the DAC output amplifiers are configured with an internal gain of +2V/V. The 3-wire serial interface is SPITM/QSPITM and MicrowireTM compatible. Each DAC has a doublebuffered input organized as an input register followed by a DAC register, which allows the input and DAC registers to be updated independently or simultaneously with a 16-bit serial word. Additional features include a 2A programmable shutdown, hardware-shutdown lockout, a separate reference-voltage input for each DAC that accepts AC and DC signals, and an active-low clear input (CL) that resets all registers and DACs to zero. The MAX5158/MAX5159 provide a programmable logic pin for added functionality and a serial-data output pin for daisy chaining.
____________________________Features
o 10-Bit Dual DAC with Internal Gain of +2V/V o Rail-to-Rail Output Swing o 8s Settling Time o Single-Supply Operation: +5V (MAX5158) +3V (MAX5159) o Low Quiescent Current: 500A (normal operation) 2A (shutdown mode) o SPI/QSPI and Microwire Compatible o Available in Space-Saving 16-Pin QSOP Package o Power-On Reset Clears Registers and DACs to Zero o Adjustable Output Offset
______________Ordering Information
PART MAX5158CPE MAX5158CEE MAX5158EPE MAX5158EEE MAX5158MJE TEMP. RANGE 0C to +70C 0C to +70C -40C to +85C -40C to +85C -55C to +125C PIN-PACKAGE 16 Plastic DIP 16 QSOP 16 Plastic DIP 16 QSOP 16 CERDIP*
________________________Applications
Digital Offset and Gain Adjustment P-Controlled Systems Motion Control Remote Industrial Controls
Ordering Information continued at end of data sheet. *Contact factory for availability.
_________________________________________________________Functional Diagram
DOUT CL PDL DGND AGND VDD REFA OSA DECODE CONTROL R
R INPUT REG A DAC REG A DAC A R OUTA OSB
16-BIT SHIFT REGISTER SR CONTROL
MAX5158 MAX5159
LOGIC OUTPUT SCLK UPO INPUT REG B DAC REG B DAC B
R OUTB
CS
DIN
REFB
Rail-to-Rail is a registered trademark of Nippon Motorola Ltd. Microwire is a trademark of National Semiconductor Corp. SPI and QSPI are trademarks of Motorola, Inc.
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 For small orders, phone 408-737-7600 ext. 3468.
Low-Power, Dual, 10-Bit Voltage-Output DACs with Serial Interface MAX5158/MAX5159
ABSOLUTE MAXIMUM RATINGS
VDD to AGND............................................................-0.3V to +6V VDD to DGND ...........................................................-0.3V to +6V AGND to DGND ..................................................................0.3V OSA, OSB to AGND........................(AGND - 4V) to (VDD + 0.3V) REF_, OUT_ to AGND.................................-0.3V to (VDD + 0.3V) Digital Inputs (SCLK, DIN, CS, CL, PDL) to DGND............................................................(-0.3V to +6V) Digital Outputs (DOUT, UPO) to DGND ................................................-0.3V to (VDD + 0.3V) Maximum Current into Any Pin .........................................20mA Continuous Power Dissipation (TA = +70C) Plastic DIP (derate 10.5mW/C above +70C) ...........842mW QSOP (derate 8.30mW/C above +70C) ...................667mW CERDIP (derate 10.00mW/C above +70C) ..............800mW Operating Temperature Ranges MAX515_ _C_ E .................................................0C to +70C MAX515_ _E_ E ..............................................-40C to +85C MAX515_ _MJE.............................................-55C to +125C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS--MAX5158
(VDD = +5V 10%, VREFA = VREFB = 2.048V, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25C (OS_ tied to AGND for a gain of +2V/V).) PARAMETER STATIC PERFORMANCE Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Offset Tempco Gain Error Gain-Error Tempco VDD Power-Supply Rejection Ratio REFERENCE INPUT Reference Input Range Reference Input Resistance REF RREF Minimum with code 1558 hex Input code = 1FF8 hex, VREF_ = 0.67Vp-p at 0.75VDC Input code = 0000 hex, VREF_ = (VDD - 1.4 Vp-p) at 1kHz SINAD Input code = 1FF8 hex, VREF_ = 1Vp-p at 1.25VDC, f = 25kHz CL, PDL, CS, DIN, SCLK CL, PDL, CS, DIN, SCLK 200 VIN = 0V to VDD 0.001 8 1 3 0.8 0 18 25 VDD - 1.4 V k PSRR Normalized to 2.048V 2.7V VDD 5.5V INL DNL VOS_ TCVOS (Note 1) Guaranteed monotonic Code = 2 Normalized to 2.048V 4 -0.1 4 20 260 1 10 1 1 6 Bits LSB LSB mV ppm/C LSB ppm/C V/V SYMBOL CONDITIONS MIN TYP MAX UNITS
MULTIPLYING-MODE PERFORMANCE Reference 3dB Bandwidth Reference Feedthrough Signal-to-Noise plus Distortion Ratio DIGITAL INPUTS Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Input Capacitance VIH VIL VHYS IIN CIN V V mV A pF 300 -82 75 kHz dB dB
2
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Low-Power, Dual, 10-Bit, Voltage-Output DACs with Serial Interface
ELECTRICAL CHARACTERISTICS--MAX5158 (continued)
(VDD = +5V 10%, VREFA = VREFB = 2.048V, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25C (OS_ tied to AGND for a gain of +2V/V).) PARAMETER DIGITAL OUTPUTS (DOUT, UPO) Output High Voltage Output Low Voltage DYNAMIC PERFORMANCE Voltage Output Slew Rate Output Settling Time Output Voltage Swing OSA or OSB Input Resistance Time Required to Exit Shutdown Digital Feedthrough Digital Crosstalk POWER SUPPLIES Positive Supply Voltage Power-Supply Current Power-Supply Current in Shutdown Reference Current in Shutdown TIMING CHARACTERISTICS SCLK Clock Period SCLK Pulse Width High SCLK Pulse Width Low CS Fall to SCLK Rise Setup Time SCLK Rise to CS Rise Hold Time SDI Setup Time SDI Hold Time SCLK Rise to DOUT Valid Propagation Delay SCLK Fall to DOUT Valid Propagation Delay SCLK Rise to CS Fall Delay CS Rise to SCLK Rise Hold CS Pulse Width High tCP tCH tCL tCSS tCSH tDS tDH tDO1 tDO2 tCS0 tCS1 tCSW CLOAD = 200pF CLOAD = 200pF 10 40 100 (Note 4) 100 40 40 40 0 40 0 80 80 VDD IDD (Note 3) 4.5 0.5 2 0 CS = VDD, fDIN = 100kHz, VSCLK = 5Vp-p ROS_ SYMBOL VOH VOL SR To 1/2LSB of full-scale, VSTEP = 4V Rail-to-rail (Note 2) 24 CONDITIONS ISOURCE = 2mA ISINK = 2mA MIN VDD - 0.5 0.13 0.75 8 0 to VDD 34 25 5 5 5.5 0.65 10 1 0.4 TYP MAX UNITS V V V/s s V k s nV-s nV-s V mA A A ns ns ns ns ns ns ns ns ns ns ns ns
MAX5158/MAX5159
IDD(SHDN) (Note 3)
Note 1: Accuracy is specified from code 2 to code 1023. Note 2: Accuracy is better than 1LSB for VOUT_ greater than 6mV and less than VDD - 50mV. Guaranteed by PSRR test at the end points. Note 3: Digital inputs are set to either VDD or DGND, code = 0000 hex, RL = . Note 4: SCLK minimum clock period includes rise and fall times.
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3
Low-Power, Dual, 10-Bit Voltage-Output DACs with Serial Interface MAX5158/MAX5159
ELECTRICAL CHARACTERISTICS--MAX5159
(VDD = +2.7V to +3.6V, VREFA = VREFB = 1.25V, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C (OS_ pins tied to AGND for a gain of +2V/V).) PARAMETER STATIC PERFORMANCE Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Offset Tempco Gain Error Gain-Error Tempco VDD Power-Supply Rejection Ratio REFERENCE INPUT (VREF) Reference Input Range Reference Input Resistance REF RREF Minimum with code 1558 hex Input code = 1FF8 hex, VREF_ = 0.67Vp-p at 0.75VDC Input code = 0000 hex, VREF_ = (VDD - 1.4)Vp-p at 1kHz SINAD Input code = 1FF8 hex, VREF_ = 1Vp-p at 1VDC, f = 15kHz CL, PDL, CS, DIN, SCLK CL, PDL, CS, DIN, SCLK 200 VIN = 0V to VDD 0 8 ISOURCE = 2mA ISINK = 2mA VDD - 0.5 0.13 0.75 To 1/2LSB of full-scale, VSTEP = 2.5V Rail-to-rail (Note 6) ROS_ 24 8 0 to VDD 34 25 CS = VDD, fDIN = 100kHz, VSCLK = 3Vp-p 5 5 0.4 1 2.2 0.8 0 18 25 VDD - 1.4 V k PSRR Normalized to 1.25V 2.7V VDD 3.6V INL DNL VOS TCVOS (Note 5) Guaranteed monotonic Code = 3 Normalized to 1.25V 6.5 -0.1 6.5 40 320 1 10 1 1 6 Bits LSB LSB mV ppm/C LSB ppm/C V/V SYMBOL CONDITIONS MIN TYP MAX UNITS
MULTIPLYING-MODE PERFORMANCE Reference 3dB Bandwidth Reference Feedthrough Signal-to-Noise plus Distortion Ratio DIGITAL INPUTS Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Input Capacitance DIGITAL OUTPUTS Output High Voltage Output Low Voltage Voltage Output Slew Rate Output Settling Time Output Voltage Swing OSA or OSB Input Resistance Time Required for Valid Operation after Shutdown Digital Feedthrough Digital Crosstalk VOH VOL SR V V V/s s V k s nV-s nV-s VIH VIL VHYS IIN CIN V V mV A pF 300 -82 73 kHz dB dB
DYNAMIC PERFORMANCE (DOUT, UPO)
4
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Low-Power, Dual, 10-Bit, Voltage-Output DACs with Serial Interface
ELECTRICAL CHARACTERISTICS--MAX5159 (continued)
(VDD = +2.7V to +3.6V, VREFA = VREFB = 1.25V, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C (OS_ pins tied to AGND for a gain of +2V/V).) PARAMETER POWER SUPPLIES Positive Supply Voltage Power-Supply Current Power-Supply Current in Shutdown Reference Current in Shutdown TIMING CHARACTERISTICS SCLK Clock Period SCLK Pulse Width High SCLK Pulse Width Low CS Fall to SCLK Rise Setup Time SCLK Rise to CS Rise Hold Time SDI Setup Time SDI Hold Time SCLK Rise to DOUT Valid Propagation Delay SCLK Fall to DOUT Valid Propagation Delay SCLK Rise to CS Fall Delay CS Rise to SCLK Rise Hold CS Pulse Width High tCP tCH tCL tCSS tCSH tDS tDH tDO1 tDO2 tCS0 tCS1 tCSW CLOAD = 200pF CLOAD = 200pF 10 40 100 (Note 4) 100 40 40 40 0 50 0 120 120 SYMBOL VDD IDD (Note 7) CONDITIONS MIN 2.7 0.5 1 TYP MAX 3.6 0.6 8 1 UNITS V mA A A
MAX5158/MAX5159
IDD(SHDN) (Note 7)
ns ns ns ns ns ns ns ns ns ns ns ns
Note 5: Accuracy is specified from code 3 to code 1023. Note 6: Accuracy is better than 1LSB for VOUT greater than 6mV and less than VDD - 80mV. Guaranteed by PSRR test at the end points. Note 7: Digital inputs are set to either VDD or DGND, code = 0000 hex, RL = .
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Low-Power, Dual, 10-Bit Voltage-Output DACs with Serial Interface MAX5158/MAX5159
__________________________________________Typical Operating Characteristics
(VDD = +5V, RL = 10k, CL = 100pF, OS_ pins tied to AGND, TA = +25C, unless otherwise noted.)
MAX5158
REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE
MAX5158/5159-01
SUPPLY CURRENT vs. TEMPERATURE
MAX5158/5159 toc02
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY
VREF = 1Vp-p @ 2.5VDC CODE = 1FF8 (HEX) -40 THD + NOISE (dB)
MAX5158/5159 toc03
0 -2 -4 RELATIVE OUTPUT (dB) -6 -8 -10 -12 -14 -16 -18 -20 1 370 740 1110 1480 VREF = 0.67Vp-p @ 2.5VDC CODE = 1FF8 (HEX)
700 650 SUPPLY CURRENT (A) 600 550 500 450 400 VREF = 2.048V RL = -55 -35 -15 5 25 45 65 CODE = 0000 (HEX) CODE = 1FF8 (HEX)
-30
-50
-60
-70
-80 1 10 FREQUENCY (kHz) 100
1850
85 105 125
FREQUENCY (kHz)
TEMPERATURE (C)
FULL-SCALE ERROR vs. RESISTIVE LOAD
MAX5158/5159 toc04
REFERENCE FEEDTHROUGH AT 1kHz
-60 -70 RELATIVE OUTPUT (dB) -80 -90 -100 -110 -120 -130 -140 VREF = 3.6Vp-p @ 1.88VDC CODE = 0000 (HEX)
MAX5158/5159 toc05
SHUTDOWN CURRENT vs. TEMPERATURE
VREF = 1V 5 SHUTDOWN CURRENT (A) 4 3 2 1 0
MAX5158/5159 toc06
0.50 0.25 FULL-SCALE ERROR (LSB) 0 -0.25 -0.5 -0.75 -1.0 0.1 1 RL (k) 10
-50
6
-150 100 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 FREQUENCY (kHz)
-55 -35 -15
5
25
45 65
85 105 125
TEMPERATURE (C)
OUTPUT FFT PLOT
-10 -20 RELATIVE OUTPUT (dB) -30 -40 -50 -60 -70 -80 -90 -100 0.5 1.6 2.7 3.8 4.9 6.0 NOTE: RELATIVE TO FULL-SCALE VREF = 2.45Vp-p @ 1.225VDC f = 1kHz CODE = 1FF8 (HEX)
MAX5158/5159 toc07
DYNAMIC RESPONSE RISE TIME
MAX5158/5159 toc08
DYNAMIC RESPONSE FALL TIME
MAX5158/5159 toc09
0
CS 5V/div
CS 5V/div
OUT_ 1V/div
OUT_ 1V/div
2s/div VREF = 2.048V VREF = 2.048V
2s/div
FREQUENCY (kHz)
6
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Low-Power, Dual, 10-Bit, Voltage-Output DACs with Serial Interface
____________________________Typical Operating Characteristics (continued)
(VDD = +3V, RL = 10k, CL = 100pF, OS_ pins tied to AGND, TA = +25C, unless otherwise noted.)
MAX5158/MAX5159
REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE
MAX5158/5159 toc10
MAX5159
SUPPLY CURRENT vs. TEMPERATURE
MAX5158/5159 toc11
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY
VREF = 1Vp-p @ 1VDC CODE = 1FF8 (HEX) -40 THD + NOISE (dB)
MAX5158/5159 toc12
0 -2 -4 RELATIVE OUTPUT (dB) -6 -8 -10 -12 -14 -16 -18 -20 1 320 640 960 1280 VREF = 0.67Vp-p @ 0.75VDC CODE = 1FF8
560 540 SUPPLY CURRENT (A) 520 500 480 460 440 420 400 CODE = 0000 (HEX) VREF = 1V RL = CODE = 1FF8 (HEX)
-30
-50
-60
-70
-80 -55 -35 -15 5 25 45 65 85 105 125 1 10 FREQUENCY (kHz) 100 TEMPERATURE (C)
1600
FREQUENCY (kHz)
FULL-SCALE ERROR vs. RESISTIVE LOAD
MAX5158/5159 toc13
REFERENCE FEEDTHROUGH AT 1kHz
MAX5158/5159 toc14
SHUTDOWN CURRENT vs. TEMPERATURE
2.8 SHUTDOWN CURRENT (A) 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 VREF = 1V RL =
MAX5158/5159 toc15
0.50 0.25 FULL-SCALE ERROR (LSB) 0 -0.25 -0.50 -0.75 -1.00 0.1 1 RL (k) 10
-50 -60 -70 RELATIVE OUTPUT (dB) -80 -90 -100 -110 -120 -130 -140 -150 VREF = 1.6Vp-p @ 0.88VDC CODE = 0000 (HEX)
3.0
100
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 FREQUENCY (kHz)
-55 -35 -15
5
25
45
65
85 105 125
TEMPERATURE (C)
OUTPUT FFT PLOT
MAX5158/5159toc16
DYNAMIC RESPONSE RISE TIME
MAX5158/5159 toc17
DYNAMIC RESPONSE FALL TIME
MAX5158/5159 toc18
0 -10 -20 RELATIVE OUTPUT (dB) -30 -40 -50 -60 -70 -80 -90 -100 0.5 1.6 2.7 3.8 4.9 VREF = 1.4Vp-p @ 0.75VDC f = 1kHz CODE = 1FF8 (HEX)
CS 2V/div
CS 2V/div
OUT_ 500mV/div
OUT_ 500mV/div
6.0 VREF = 1.25V
2s/div VREF = 1.25V
2s/div
FREQUENCY (kHz)
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7
Low-Power, Dual, 10-Bit Voltage-Output DACs with Serial Interface MAX5158/MAX5159
_____________________________Typical Operating Characteristics (continued)
(VDD = +5V (MAX5158), VDD = +3V (MAX5159), RL = 10k, CL = 100pF, OS_ pins tied to AGND, unless otherwise noted.)
MAX5158/MAX5159
MAX5158 SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5158/5159 TOC19
MAX5159 SUPPLY CURRENT vs. SUPPLY VOLTAGE
CODE = 1FF8 (HEX) SUPPLY CURRENT (mA) 0.55
MAX5158/5159 TOC19a MAX5158/5159 toc22
0.60 CODE = 1FF8 (HEX) SUPPLY CURRENT (mA) 0.55
0.60
0.50 CODE = 0000 (HEX) 0.45
0.50 CODE = 0000 (HEX) 0.45
0.40 4.50 4.75 5.00 5.25 5.50 SUPPLY VOLTAGE (V)
0.40
MAX5158 MAJOR-CARRY TRANSITION
MAX5158/5159 toc20
2.7
3.0
3.3
3.6
SUPPLY VOLTAGE (V)
CS 2V/div
OUT_ 50mV/div AC COUPLED
5s/div TRANSITION FROM 1000 (HEX) TO 0FF8 (HEX)
MAX5158 ANALOG CROSSTALK
MAX5158/5159 toc21
MAX5158 DIGITAL FEEDTHROUGH
OUTA 5V/div
SCLK 5V/div
OUTB 200V/div AC COUPLED
OUTA 500V/div AC COUPLED
250s/div VREF = 2.048V, GAIN = +2V/V, CODE = 1FF8 HEX
2.5s/div
8
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Low-Power, Dual, 10-Bit, Voltage-Output DACs with Serial Interface
_____________________Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NAME AGND OUTA OSA REFA CL CS DIN SCLK DGND DOUT UPO PDL REFB OSB OUTB VDD FUNCTION Analog Ground DAC A Output Voltage DAC A Offset Adjustment Reference for DAC A Active-Low Clear Input. Resets all registers to zero. DAC outputs go to 0V. Chip-Select Input Serial-Data Input Serial Clock Input Digital Ground Serial-Data Output User-Programmable Output Power-Down Lockout. The device cannot be powered down when PDL is low. Reference for DAC B DAC B Offset Adjustment DAC B Output Voltage Positive Power Supply
REF_ AGND SHOWN FOR ALL 1s ON DAC 2R 2R D0 2R D7 2R D8 2R D9 R R R R
MAX5158/MAX5159
OS_
R OUT_
Figure 1. Simplified DAC Circuit Diagram
VOUT = (VREF x NB / 1024) x 2 where NB is the numeric value of the DAC's binary input code (0 to 1023) and VREF is the reference voltage. The reference input impedance ranges from 18k (1558 hex) to several giga ohms (with an input code of 0000 hex). The reference input capacitance is code dependent and typically ranges from 15pF with an input code of all zeros to 50pF with a full-scale input code.
Output Amplifier
The output amplifiers on the MAX5158/MAX5159 have internal resistors that provide for a gain of +2V/V when OS_ is connected to AGND. These resistors are trimmed to minimize gain error. The output amplifiers have a typical slew rate of 0.75V/s and settle to 1/2LSB within 8s, with a load of 10k in parallel with 100pF. Loads less than 2k degrade performance. The OS_ pin can be used to produce an adjustable offset voltage at the output. For instance, to achieve a 1V offset, apply -1V to the OS_ pin to produce an output range from 1V to (1V + VREF x 2). Note that the DAC's output range is still limited by the maximum output voltage specification.
_______________Detailed Description
The MAX5158/MAX5159 dual, 10-bit, voltage-output DACs are easily configured with a 3-wire serial interface. These devices include a 16-bit data-in/data-out shift register, and each DAC has a double-buffered input composed of an input register and a DAC register (see Functional Diagram). In addition, trimmed internal resistors produce an internal gain of +2V/V that maximizes output voltage swing. The amplifier's offset-adjust pin allows for a DC shift in the DAC's output. Both DACs use an inverted R-2R ladder network that produces a weighted voltage proportional to the input voltage value. Each DAC has its own reference input to facilitate independent full-scale values. Figure 1 depicts a simplified circuit diagram of one of the two DACs.
Power-Down Mode
The MAX5158/MAX5159 feature a software-programmable shutdown mode that reduces the typical supply current to 2A. The two DACs can be shutdown independently, or simultaneously using the appropriate programming command. Enter shutdown mode by writing the appropriate input-control word (Table 1). In shutdown mode, the reference inputs and amplifier outputs become high impedance, and the serial interface
9
Reference Inputs
The reference inputs accept both AC and DC values with a voltage range extending from 0V to (VDD - 1.4V). Determine the output voltage using the following equation (OS_ = AGND):
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Low-Power, Dual, 10-Bit Voltage-Output DACs with Serial Interface MAX5158/MAX5159
remains active. Data in the input registers is saved, allowing the MAX5158/MAX5159 to recall the output state prior to entering shutdown when returning to normal mode. Exit shutdown by recalling the previous condition or by updating the DAC with new information. When returning to normal operation (exiting shutdown), wait 20s for output stabilization.
SCLK
SK
MAX5158 MAX5159
DIN
SO
MICROWIRE PORT
Serial Interface
CS I/O
Figure 2. Connections for Microwire
The MAX5158/MAX5159 3-wire serial interface is compatible with both Microwire (Figure 2) and SPI/QSPI (Figure 3) serial-interface standards. The 16-bit serial input word consists of an address bit, two control bits, 10 bits of data (MSB to LSB), and 3 sub-bits as shown in Figure 4. The address and control bits determine the MAX5158/MAX5159's response, as outlined in Table 1.
Table 1. Serial-Interface Programming Command
16-BIT SERIAL WORD
A0
0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0
C1
0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0
C0
1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0
D9..........................D0 S2-S0 (MSB) (LSB)
10-bit DAC data 10-bit DAC data 10-bit DAC data 10-bit DAC data 10-bit DAC data xxxxxxxxxx xxxxxxxxxx 0 0 1 x xxxxxx 1 0 1 x xxxxxx 1 1 0 x xxxxxx 1 1 1 x xxxxxx 0 1 0 x xxxxxx 0 1 1 x xxxxxx 1 0 0 1 xxxxxx 1 0 0 0 xxxxxx 0 0 0 x xxxxxx 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000
FUNCTION
Load input register A; DAC registers are unchanged. Load input register B; DAC registers are unchanged. Load input register A; all DAC registers are updated. Load input register B; all DAC registers are updated. Load all DAC registers from the shift register (start up both DACs with new data.). Update both DAC registers from their respective input registers (start up both DACs with data previously stored in the input registers). Shut down both DACs (provided PDL = 1). Update DAC register A from input register A (start up DAC A with data previously stored in input register A). Update DAC register B from input register B (start up DAC B with data previously stored in input register B). Shut down DAC A (provided PDL = 1). Shut down DAC B (provided PDL = 1). UPO goes low (default). UPO goes high. Mode 1, DOUT clocked out on SCLK's rising edge. Mode 0, DOUT clocked out on SCLK's falling edge (default). No operation (NOP).
x = Don't care Note: When A0, C1, and C0 = 0, then D9, D8, D7, and D6 become control bits. S2-S0 are sub bits, always zero.
10 ______________________________________________________________________________________
Low-Power, Dual, 10-Bit, Voltage-Output DACs with Serial Interface
+5V
SS
DIN
MOSI SPI/QSPI PORT
MAX5158 MAX5159
SCLK
SCK
CS
I/O
CPOL = 0, CPHA = 0
Figure 3. Connections for SPI/QSPI
The MAX5158/MAX5159's digital inputs are double buffered, which allows any of the following: loading the input register(s) without updating the DAC register(s), updating the DAC register(s) from the input register(s), or updating the input and DAC registers concurrently. The address and control bits allow the DACs to act independently. Send the 16-bit data as one 16-bit word (QSPI) or two 8-bit packets (SPI, Microwire), with CS low during this period. The address and control bits determine which register will be updated and the state of the registers when exiting shutdown. The 3-bit address/control determines the following: * registers to be updated * clock edge on which data is to be clocked out via the serial-data output (DOUT) * state of the user-programmable logic output * configuration of the device after shutdown. The general timing diagram of Figure 5 illustrates how data is acquired. Driving CS low enables the device to receive data. Otherwise, the interface control circuitry is disabled. With CS low, data at DIN is clocked into the register on the rising edge of SCLK. As CS goes high, data is latched into the input and/or DAC registers, depending on the address and control bits. The maximum clock frequency guaranteed for proper operation is 10MHz. Figure 6 depicts a more detailed timing diagram of the serial interface.
MAX5158/MAX5159
MSB ..................................................................................LSB 16 Bits of Serial Data Address Bits Control Bits MSB....DataBits...LSB Sub Bits
A0
C1, C0
D9.................. ......D0 S2-S0 10 Data Bits
1 Address/ 2 Control Bits
000
Figure 4. Serial-Data Format
CS COMMAND EXECUTED 1 DIN A0 C1 C0 D9 D8 D7 D6 8 D5 D4 9 D3 D2 D1 D0 S2 S1 16 S0
SCLK
Figure 5. Serial-Interface Timing Diagram
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11
Low-Power, Dual, 10-Bit Voltage-Output DACs with Serial Interface MAX5158/MAX5159
CS tCSO SCLK tDS DIN tDH tCSS tCL tCH tCP tCSH tCS1 tCSW
Figure 6. Detailed Serial-Interface Timing Diagram
SCLK
SCLK
SCLK
MAX5158 MAX5159
DIN CS DOUT DIN CS
MAX5158 MAX5159
DOUT DIN CS
MAX5158 MAX5159
DOUT
TO OTHER SERIAL DEVICES
Figure 7. Daisy Chaining MAX5158/MAX5159s
DIN SCLK CS1 CS2 CS3 TO OTHER SERIAL DEVICES
CS
CS
CS
MAX5158 MAX5159
SCLK DIN SCLK DIN
MAX5158 MAX5159
SCLK DIN
MAX5158 MAX5159
Figure 8. Multiple MAX5158/MAX5159s Sharing a Common DIN Line
12 ______________________________________________________________________________________
Low-Power, Dual, 10-Bit, Voltage-Output DACs with Serial Interface MAX5158/MAX5159
Table 2. Unipolar Code Table (Gain = +2)
DAC CONTENTS MSB LSB 11 1111 1111 (000)
+5V/+3V OS_
ANALOG OUTPUT
1023 +VREF x2 1024 513 +VREF x2 1024 512 +VREF x 2 = VREF 1024 511 +VREF x2 1024 1 +VREF 1024
REF_ VDD
MAX5158 MAX5159
DAC_ AGND GAIN = +2V/V
R
10
0000
0001 (000)
R OUT_ DGND
10
0000
0000 (000)
01
1111
1111 (000)
00 00
0000 0000
0001 (000) 0000 (000)
Figure 9. Unipolar Output Circuit (Rail-to-Rail)
0V
+5V/+3V REF_ OS_
Note: ( ) are for the sub bits.
Serial-Data Output The serial-data output, DOUT, is the internal shift register's output. DOUT allows for daisy chaining of devices and data readback. The MAX5158/MAX5159 can be programmed to shift data out of DOUT on SCLK's falling edge (Mode 0) or on the rising edge (Mode 1). Mode 0 provides a lag of 16 clock cycles, which maintains compatibility with SPI/QSPI and Microwire interfaces. In Mode 1, the output data lags 15.5 clock cycles. On power-up, the device defaults to Mode 0. User-Programmable Logic Output (UPO) UPO allows an external device to be controlled through the serial interface (Table 1), thereby reducing the number of microcontroller I/O pins required. On power-up, UPO is low. P Power-Down Lockout Input (PDL) The power-down lockout pin (PDL) disables software shutdown when low. When in shutdown, transitioning PDL from high to low wakes up the part with the output set to the state prior to shutdown. PDL can also be used to asynchronously wake up the device. Daisy Chaining Devices Any number of MAX5158/MAX5159s can be daisy chained by connecting the DOUT pin of one device to the DIN pin of the following device in the chain (Figure 7). Since the MAX5158/MAX5159's DOUT pin has an internal active pull-up, the DOUT sink/source capability determines the time required to discharge/charge a capacitive
VDD
VOS R
MAX5158 MAX5159
DAC _ AGND
R OUT_ DGND
Figure 10. Setting OS_ for Output Offset
load. Refer to the digital output VOH and VOL specifications in the Electrical Characteristics. Figure 8 shows an alternate method of connecting several MAX5158/MAX5159s. In this configuration, the data bus is common to all devices; data is not shifted through a daisy chain. More I/O lines are required in this configuration because a dedicated chip-select input (CS) is required for each IC.
__________Applications Information
Unipolar Output
Figure 9 shows the MAX5158/MAX5159 configured for unipolar, rail-to-rail operation with a gain of +2V/V. The MAX5158 can produce a 0V to 4.096V output with a 2.048V reference (Figure 9), while the MAX5159 can
13
______________________________________________________________________________________
Low-Power, Dual, 10-Bit Voltage-Output DACs with Serial Interface MAX5158/MAX5159
Table 3. Bipolar Code Table
DAC CONTENTS MSB LSB 11 1111 1111 (000) ANALOG OUTPUT
511 +VREF 512 1 +VREF 512
+5V/ +3V +5V/+3V 26k AC REFERENCE INPUT
MAX495
10 10 01
0000 0000 1111
0001 (000) 0000 (000) 1111 (000)
500mVp-p
10k REF VDD R OS_
0V
1 -VREF 512 511 -VREF 512 -VREF 512 = - VREF 512
DAC_
R OUT_
00
0000
0001 (000)
AGND
MAX5158 MAX5159
DGND
00
0000
0000 (000)
Figure 12. AC Reference Input Circuit Note: ( ) are for the sub bits.
V+
REF_
+5V/+3V
10k OS_
10k
PHOTODIODE REF_ +5V/+3V OS_ VDD R V+
VDD R
MAX5158 MAX5159
R DAC _ DGND AGND OUT_ 10k 10k
V+
MAX5158 MAX5159
VOUT
P DIN DAC _ AGND
R OUT_
VOUT
V-
DGND
VRPULLDOWN
Figure 11. Bipolar Output Circuit
Figure 13. Digital Calibration
produce a range of 0V to 2.5V with a 1.25V reference. Table 2 lists the unipolar output codes. An offset to the output can be achieved by connecting a voltage to OS_, as shown in Figure 10. By applying VOS_ = -1V, the output values will range between 1V and (1V + VREF x 2).
Using an AC Reference
In applications where the reference has an AC signal component, the MAX5158/MAX5159 have multiplying capabilities within the reference input voltage range specifications. Figure 12 shows a technique for applying a sinusoidal input to REF_, where the AC signal is offset before being applied to the reference input.
Bipolar Output
The MAX5158/MAX5159 can be configured for a bipolar output, as shown in Figure 11. The output voltage is given by the equation (OS_ = AGND): VOUT = VREF [((2 x NB) / 1024) - 1] where NB represents the numeric value of the DAC's binary input code. Table 3 shows digital codes and the corresponding output voltage for Figure 11's circuit.
14
Harmonic Distortion and Noise
The total harmonic distortion plus noise (THD+N) is typically less than -78dB at full scale with a 1Vp-p input swing at 5kHz. The typical -3dB frequency is 300kHz for both devices, as shown in the Typical Operating Characteristics.
______________________________________________________________________________________
Low-Power, Dual, 10-Bit, Voltage-Output DACs with Serial Interface MAX5158/MAX5159
VDD OSA
VIN
REFA CS SCLK DIN
MAX5158 MAX5159
R
R OUTA SHIFT REGISTER INPUT REG A INPUT REG B DAC REG A DAC REG B DACA
R1 R2
DACB R R
OUTB
R3 R4
VOUT
VREF
REFB
VOUT = GAIN - OFFSET OSB
IN
[ ][ ] = (V 2NA )( R2 )(1+ R4 ) (V [ 1024 R1+R2 R3 ] [
REF
2NB 1024
)( R4 )] R3
AGND
DGND
NA IS THE NUMERIC VALUE OF THE INPUT CODE FOR DACA. NB IS THE NUMERIC VALUE OF THE INPUT CODE FOR DACB.
Figure 14. Digital Control of Gain and Offset
Digital Calibration and Threshold Selection
Figure 13 shows the MAX5158/MAX5159 in a digital calibration application. With a bright light value applied to the photodiode (on), the DAC is digitally ramped until it trips the comparator. The microprocessor (P) stores this "high" calibration value. Repeat the process with a dim light (off) to obtain the dark current calibration. The P then programs the DAC to set an output voltage at the midpoint of the two calibrated values. Applications include tachometers, motion sensing, automatic readers, and liquid clarity analysis.
Power-Supply Considerations
On power-up, the input and DAC registers clear (set to zero code). For rated performance, VREF_ should be at least 1.4V below VDD. Bypass the power supply with a 4.7F capacitor in parallel with a 0.1F capacitor to AGND. Minimize lead lengths to reduce lead inductance.
Grounding and Layout Considerations
Digital and AC transient signals on AGND can create noise at the output. Connect AGND to the highest quality ground available. Use proper grounding techniques, such as a multilayer board with a low-inductance ground plane. Carefully lay out the traces between channels to reduce AC cross-coupling and crosstalk. Wire-wrapped boards and sockets are not recommended. If noise becomes an issue, shielding may be required.
Digital Control of Gain and Offset
The two DACs can be used to control the offset and gain for curve-fitting nonlinear functions, such as transducer linearization or analog compression/expansion applications. The input signal is used as the reference for the gain-adjust DAC, whose output is summed with the output from the offset-adjust DAC. The relative weight of each DAC output is adjusted by R1, R2, R3, and R4 (Figure 14).
______________________________________________________________________________________
15
Low-Power, Dual, 13-Bit Voltage-Output DACs with Serial Interface MAX5158/MAX5159
__________________Pin Configuration
TOP VIEW
AGND 1 OUTA 2 OSA 3 REFA 4 CL 5 CS 6 DIN 7 SCLK 8 16 VDD 15 OUTB 14 OSB
_Ordering Information (continued)
PART MAX5159CPE MAX5159CEE MAX5159EPE MAX5159EEE MAX5159MJE TEMP. RANGE 0C to +70C 0C to +70C -40C to +85C -40C to +85C -55C to +125C PIN-PACKAGE 16 Plastic DIP 16 QSOP 16 Plastic DIP 16 QSOP 16 CERDIP*
MAX5158 MAX5159
13 REFB 12 PDL 11 UPO 10 DOUT 9 DGND
*Contact factory for availability.
___________________Chip Information
TRANSISTOR COUNT: 3053 SUBSTRATE CONNECTED TO AGND
DIP/QSOP
________________________________________________________Package Information
QSOP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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