View 1714I_963390.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Final Electrical Specifications
LT1714 7ns, Low Power, 3V/5V Dual Rail-to-Rail Comparator
June 2000
FEATURES
s s s s s s s s
DESCRIPTIO
Ultrafast: 7ns at 20mV Overdrive 8.5ns at 5mV Overdrive Input Common Mode Extends Beyond Supplies Specified at Single 2.7V or 5V Supply or 5V TTL/CMOS Compatible Rail-to-Rail Outputs Low Power (Per Comparator): 5mA Dual Output Latch Capability Inputs Can Exceed Supplies Without Phase Reversal Available in 16-Lead Narrow SSOP
The LT(R)1714 is an UltraFastTM 7ns dual comparator featuring rail-to-rail inputs, complementary rail-to-rail outputs and dual internal output latches. Optimized for 3V and 5V power supplies, it operates over a single supply voltage range from 2.4V to 12V or from 2.4V to 6V dual supplies. The LT1714 is designed for ease of use in a variety of systems. In addition to the wide supply voltage flexibility, the rail-to-rail input common mode range extends 100mV beyond both supply rails, and the outputs are protected against phase reversal for inputs extending further beyond the rails. Also, the rail-to-rail inputs may be taken to opposite rails with no significant increase in input current. The rail-to-rail matched complementary outputs interface directly to TTL or CMOS logic and can sink 10mA to within 0.5V of GND or source 10mA to within 0.7V of V +. The LT1714 has dual internal TTL/CMOS compatible latches for retaining data at the outputs. The latch holds data as long as the latch pin is held high. Latch pin hysteresis provides protection against slow moving or noisy latch signals. The LT1714 is available in the 16-pin narrow SSOP.
, LTC and LT are registered trademarks of Linear Technology Corporation. UltraFast is a trademark of Linear Technology Corporation.
APPLICATIO S
s s s s s s s s s s s
High Speed Automatic Test Equipment Current Sense for Switching Regulators Crystal Oscillator Circuits High Speed Sampling Circuits High Speed A/D Converters Pulse Width Modulators Window Comparators Extended Range V/F Converters Fast Pulse Height/Width Discriminators Line Receivers High Speed Triggers
TYPICAL APPLICATIO
3V 2k 27
Propagation Delay vs Input Overdrive
9.0 8.5 TJ = 25C VSTEP = 100mV VOD = 20mV V + = 5V V - = 0V
Rail-to-Rail Pulse Width Modulator
PROPAGATION DELAY (ns)
8.0 7.5 7.0 6.5 6.0 5.5 tPD-
+
2k 1/2 LT1714
ANALOG INPUT
1k 0.001F 500pF
+
1/2 LT1714 MODULATOR OUTPUT
-
499
-
-
LT1809
1k 3V 1k 0.01F
+
1MHz TRIANGLE WAVE
1714 TA01
5.0
0
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
tPD+ 10 20 40 50 30 INPUT OVERDRIVE (mV) 60
1714 TA02
U
U
1
LT1714
ABSOLUTE
(Note 1)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW -IN A +IN A V- V+ V+ V- +IN B -IN B 1 2 3 4 5 6 7 8 16 LEA 15 GNDA 14 +OUT A 13 -OUT A 12 -OUT B 11 +OUT B 10 GNDB 9 LEB
Supply Voltage V + to V - ............................................................ 12.6V V + to GND ........................................................ 12.6V V - to GND .............................................- 10V to 0.3V Differential Input Voltage ................................... 12.6V Latch Pin Voltage ...................................................... 7V Input and Latch Current ..................................... 10mA Output Current (Continuous) .............................. 20mA Operating Temperature Range ................ - 40C to 85C Specified Temperature Range (Note 2) ... - 40C to 85C Junction Temperature .......................................... 150C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LT1714CGN LT1714IGN
GN PART MARKING 1714 1714I
GN PACKAGE 16-LEAD PLASTIC SSOP
TJMAX = 150C, JA = 150C/ W
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. V + = 5V, V - = - 5V, VCM = 0V, VLATCH = 0.8V, VOVERDRIVE = 20mV, unless otherwise specified.
SYMBOL PARAMETER V+ V- VOS Positive Supply Voltage Range Negative Supply Voltage Range (Note 3) Input Offset Voltage (Note 4) RS = 50, VCM = 0V RS = 50, VCM = 0V RS = 50, VCM = - 5V RS = 50, VCM = 5V CONDITIONS
q q q
MIN 2.4 -7
TYP
MAX 7 0
UNITS V V mV mV mV mV V/C A A A A V dB dB dB dB dB dB V/mV V V
1.0 1.0 2.0
q q
3.0 4.0 3.5 5.0 1 2 2 5 5.1
VOS/T IOS IB VCM CMRR PSRR+ PSRR- AV VOH VOL
Input Offset Voltage Drift Input Offset Current Input Bias Current (Note 5)
5 0.1 -7 - 15 - 5.1 62 60 68 65 65 60 5 4.5 4.3 70 80 80 25 4.8 4.6 0.20 0.35 0.4 0.5 - 1.5
q
Input Voltage Range Common Mode Rejection Ratio Positive Power Supply Rejection Ratio Negative Power Supply Rejection Ratio Small-Signal Voltage Gain Output Voltage Swing HIGH (Note 8) Output Voltage Swing LOW (Note 8) - 5V VCM 5V
q q
2.4V V + 7V, VCM = - 5V
q
- 7V V - 0V, VCM = 5V
q
1V VOUT 4V, RL = IOUT = 1mA IOUT = 10mA IOUT = - 1mA IOUT = - 10mA
q q q q
2
U
V V
W
U
U
WW
W
LT1714
ELECTRICAL CHARACTERISTICS
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. V + = 5V, V - = - 5V, VCM = 0V, VLATCH = 0.8V, COUT = 10pF, VOVERDRIVE = 20mV, unless otherwise specified.
SYMBOL PARAMETER I+ I- VIH VIL IIL tPD tPD tr tf tLPD tSU tH tDPW fMAX tJITTER Positive Supply Current (Per Comparator)
q
CONDITIONS
MIN
TYP 5.5 3.5
MAX 7.5 9.0 4.5 5.0 0.8 10
UNITS mA mA mA mA V V A ns ns ns ns ns ns ns ns ns ns MHz ps
Negative Supply Current (Per Comparator)
q
Latch Pin High Input Voltage Latch Pin Low Input Voltage Latch Pin Current Propagation Delay (Note 6) VLATCH = 5V VIN = 100mV, VOD = 20mV VIN = 100mV, VOD = 20mV VIN = 100mV, VOD = 5mV VIN = 100mV, VOD = 20mV 10% to 90% 90% to 10%
q q q
2
7
q
10 12 3
8.5 0.5 4 4 8 1.5 0 8
Differential Propagation Delay (Note 6) Output Rise Time Output Fall Time Latch Propagation Delay (Note 7) Latch Setup Time (Note 7) Latch Hold Time (Note 7) Minimum Latch Disable Pulse Width (Note 7) Maximum Toggle Frequency Output Timing Jitter
VIN = 100mVP-P Sine Wave VIN = 630mVP-P (0dBm) Sine Wave, f = 30MHz
65 15
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. V + = 2.7V or V + = 5V, V - = 0V, VCM = V +/2, VLATCH = 0.8V, VOVERDRIVE = 20mV, unless otherwise specified.
SYMBOL PARAMETER V+ VOS Positive Supply Voltage Range Input Offset Voltage (Note 4) RS = 50, VCM = 2.5V, V + = 5V RS = 50, VCM = 0V, V + = 5V RS = 50, VCM = 5V, V + = 5V RS = 50, VCM = 1.35V, V + = 2.7V RS = 50, VCM = 0V, V + = 2.7V RS = 50, VCM = 2.7V, V + = 2.7V RS = 50, VCM = 2.5V, V + = 5V CONDITIONS
q
MIN 2.4
TYP 1.0 1.0 1.5 1.0 1.0 1.5
MAX 7 3.0 3.5 5.0 4.0 3.5 5.0 4.0 1 2 2 3 V + + 0.1
UNITS V mV mV mV mV mV mV mV V/C A A A A V dB dB dB dB dB dB dB dB V/mV
q q q
VOS/T IOS IB VCM CMRR
Input Offset Voltage Drift Input Offset Current Input Bias Current (Note 5)
5 0.1 -6 - 12 - 0.1 60 58 57 55 65 60 65 60 5 70 70 80 80 25 - 1.5
q
Input Voltage Range (Note 9) Common Mode Rejection Ratio V + = 5V, 0V VCM 5V V + = 5V, 0V VCM 5V V + = 2.7V, 0V VCM 2.7V V + = 2.7V, 0V VCM 2.7V 2.4V V + 7V, VCM = 0V
q q q q
PSRR+ PSRR- AV
Positive Power Supply Rejection Ratio Negative Power Supply Rejection Ratio Small-Signal Voltage Gain
- 7V V - 0V, V + = 5V, VCM = 5V
q
1V VOUT 4V, RL =
3
LT1714
ELECTRICAL CHARACTERISTICS
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. V + = 2.7V or V + = 5V, V - = 0V, VCM = V +/2, VLATCH = 0.8V, COUT = 10pF, VOVERDRIVE = 20mV, unless otherwise specified.
SYMBOL PARAMETER VOH Output Voltage Swing HIGH CONDITIONS IOUT = 1mA, IOUT = 10mA, V + = 5V IOUT = 1mA, V + = 2.7V IOUT = 10mA, V + = 2.7V IOUT = - 1mA IOUT = - 10mA V + = 5V
q
MIN
q q q q q q
TYP 4.80 4.60 2.45 2.30 0.20 0.35 5 3
MAX
UNITS V V V V
V + = 5V
4.5 4.3 2.2 2.0
VOL I+ I- VIH VIL IIL tPD
Output Voltage Swing LOW Positive Supply Current (Per Comparator) Negative Supply Current (Per Comparator) Latch Pin High Input Voltage Latch Pin Low Input Voltage Latch Pin Current Propagation Delay (Note 6)
0.4 0.5 6.5 8.0 4.0 4.5 0.8 10
V V mA mA mA mA V V A ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ps
V + = 5V
q q q
2
VLATCH
= V+
q
VIN = 100mV, VOD = 20mV, V+ = 5V VIN = 100mV, VOD = 20mV, V+ = 5V VIN = 100mV, VOD = 5mV, V+ = 5V VIN = 100mV, VOD = 20mV, V+ = 2.7V VIN = 100mV, VOD = 20mV, V+ = 2.7V VIN = 100mV, VOD = 5mV, V+ = 2.7V VIN = 100mV, VOD = 20mV 10% to 90% 90% to 10%
8.0
q
10.5 12.0 11.0 12.5 3
9.0 8.0
q
9.0 0.5 4 4 8 1.5 0 8
tPD tr tf tLPD tSU tH tDPW fMAX tJITTER
Differential Propagation Delay (Note 6) Output Rise Time Output Fall Time Latch Propagation Delay (Note 7) Latch Setup Time (Note 7) Latch Hold Time (Note 7) Minimum Latch Disable Pulse Width (Note 7) Maximum Toggle Frequency Output Timing Jitter
VIN = 100mVP-P Sine Wave VIN = 630mVP-P (0dBm) Sine Wave, f = 30MHz
65 15
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LT1714C and LT1714I are guaranteed to meet specified performance from 0C to 70C. The LT1714C is designed, characterized and expected to meet specified performance from - 40C to 85C but is not tested or QA sampled at these temperatures. The LT1714I is guaranteed to meet specified performance from - 40C to 85C. Note 3: The negative supply should not be greater than the ground pin voltages and the maximum voltage across the positive and negative supplies should not be greater than 12V. Note 4: Input offset voltage (VOS) is defined as the average of the two voltages measured by forcing first one output, then the other to V +/2. Note 5: Input bias current (IB) is defined as the average of the two input currents. Note 6: Propagation delay (tPD) is measured with the overdrive added to the actual VOS. Differential propagation delay is defined as: tPD = tPD+ - tPD-. Load capacitance is 10pF. Due to test system
requirements, the LT1714 propagation delay is specified with a 1k load to ground for 5V supplies, or to mid-supply for 2.7V or 5V single supplies. Note 7: Latch propagation delay (tLPD) is the delay time for the output to respond when the latch pin is deasserted. Latch setup time (tSU) is the interval in which the input signal must remain stable prior to asserting the latch signal. Latch hold time (tH) is the interval after the latch is asserted in which the input signal must remain stable. Latch disable pulse width (tDPW) is the width of the negative pulse on the latch enable pin that latches in new data on the data inputs. Note 8: Output voltage swings are characterized and tested at V + = 5V and V - = 0V. They are designed and expected to meet these same specifications at V - = - 5V. Note 9: The input voltage range is tested under the more demanding conditions of V + = 5V and V - = -5V. The LT1714 is designed and expected to meet these specifications at V - = 0V.
4
LT1714 TYPICAL PERFOR A CE CHARACTERISTICS
Propagation Delay vs Load Capacitance
14 12
PROPAGATION DELAY (ns)
PROPAGATION DELAY (ns)
PROPAGATION DELAY (ns)
tPD+ tPD
-
10 8 6 4 2 0 0 TA = 25C V + = 5V V - = 0V VSTEP = 100mV OVERDRIVE = 20mV VCM = 2.5V 20 80 60 100 40 LOAD CAPACITANCE (pF) 120
1714 G01
NEGATIVE SUPPLY CURRENT PER COMPARATOR (mA)
POSITIVE SUPPLY CURRENT PER COMPARATOR (mA)
Positive Supply Current vs Positive Supply Voltage
7.0 6.5 6.0 V - = 0V 5.5 5.0 4.5 4.0 VIN = 100mV IOUT = 0 V - = -5V
3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 0
V + = 5V
POSITIVE SUPPLY CURRENT (mA)
2
6 8 10 4 POSITIVE SUPPLY VOLTAGE (V)
Input Bias Current vs Input Common Mode Voltage
3 2
OUTPUT VOLTAGE RELATIVE TO V + (V)
4.9 4.8 4.7 4.6 4.5 4.4 4.3 4.2 4.1 4.0 0.01
OUTPUT VOLTAGE RELATIVE TO GND (V)
INPUT BIAS CURRENT (A)
1 0 -1 -2 -3 -4 -5 -6
V + = 5V V - = 0V VIN = 0mV
-1
1 2 0 3 4 5 INPUT COMMON MODE VOLTAGE (V)
UW
1714 G04
1714 G07
Propagation Delay vs Input Common Mode Voltage
10.0 9.5 9.0 8.5 tPD+ 8.0 7.5 7.0 6.5 6.0 - 0.5 0.5 3.5 4.5 2.5 INPUT COMMON MODE (V) 1.5 5.5
1714 G02
Propagation Delay vs Positive Supply Voltage
10.0 9.5 9.0 8.5 8.0 7.5 7.0 6.5 6.0 0 2 10 12 4 8 6 POSITIVE SUPPLY VOLTAGE (V) 14
1714 G03
TA = 25C V + = 5V V - = 0V VSTEP = 100mV OVERDRIVE = 20mV
TA = 25C VSTEP = 100mV OVERDRIVE = 20mV VCM = 2.5V V - = 0V
tPD+
tPD-
tPD-
Negative Supply Current vs Negative Supply Voltage
4.0 3.8 VIN = 100mV IOUT = 0
Positive Supply Current vs Switching Frequency
40 V + = 5V - 35 V = 0V CLOAD = 10pF 30 25 20 15 10 5 0 0 20 10 30 SWITCHING FREQUENCY (MHz) 40
1714 G06
V + = 2.7V
12
4 3 2 5 6 1 NEGATIVE SUPPLY VOLTAGE (V)
7
1714 G05
Output High Voltage vs Source Current
5.0 V + = 5V V - = 0V VIN = 100mV 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1
Output Low Voltage vs Sink Current
V + = 5V V - = 0V VIN = 100mV
6
1 0.1 LOADING SOURCE CURRENT (mA)
10
1714 G08
0 0.01
1 0.1 LOADING SINK CURRENT (mA)
10
1714 G09
5
LT1714 TYPICAL PERFOR A CE CHARACTERISTICS
Output Timing Jitter vs Switching Frequency
200 180 V + = 5V V - = 0V VCM = 2.5V VIN = 630mVP-P (0dBm) SINE WAVE
OUTPUT TIMING JITTER (ps)
160 140 120 100 80 60 40 20 0 0 20
40 60 FREQUENCY (MHz)
PI FU CTIO S
- IN A (Pin 1): Inverting Input of A Channel Comparator. + IN A (Pin 2): Noninverting Input of A Channel Comparator. V - (Pins 3, 6): Negative Supply Voltage, Usually - 5V. Pins 3 and 6 should be connected together externally. V + (Pins 4, 5): Positive Supply Voltage, Usually 5V. Pins 4 and 5 should be connected together externally. + IN B (Pin 7): Noninverting Input of B Channel Comparator. - IN B (Pin 8): Inverting Input of B Channel Comparator. LEB (Pin 9): Latch Enable Input of B Channel Comparator. GNDB (Pin 10): Ground Supply Voltage of B Channel Comparator, Usually 0V. +OUT B (Pin 11): Noninverting Output of B Channel Comparator. - OUT B (Pin 12): Inverting Output of B Channel Comparator. - OUT A (Pin 13): Inverting Output of A Channel Comparator. +OUT A (Pin 14): Noninverting Output of A Channel Comparator. GNDA (Pin 15): Ground Supply Voltage of A Channel Comparator, Usually 0V LEA (Pin 16): Latch Enable Input of A Channel Comparator.
6
UW
1714 G10
Output Rising Edge
Output Falling Edge
VIN
VIN
VOUT
VOUT
80
U
U
U
LT1714
APPLICATIO S I FOR ATIO
Common Mode Considerations
The LT1714 is specified for a common mode range of - 5.1V to 5.1V on a 5V supply, or a common mode range of - 0.1V to 5.1V on a single 5V supply. A more general consideration is that the common mode range is from 100mV below the negative supply to 100mV above the positive supply, independent of the actual supply voltage. The criteria for common mode limit is that the output still responds correctly to a small differential input signal. When either input signal falls outside the common mode limit, the internal PN diode formed with the substrate can turn on resulting in significant current flow through the die. Schottky clamp diodes between the inputs and the supply rails speed up recovery from excessive overdrive conditions by preventing these substrate diodes from turning on. Input Bias Current Input bias current is measured with the outputs held at 2.5V with a 5V supply voltage. As with any rail-to-rail differential input stage, the LT1714 bias current flows into or out of the device depending upon the common mode level. The input circuit consists of an NPN pair and a PNP pair. For inputs near the negative rail, the NPN pair is inactive, and the input bias current flows out of the device; for inputs near the positive rail, the PNP pair is inactive, and these currents flow into the device. For inputs far enough away from the supply rails, the input bias current will be some combination of the NPN and PNP bias currents. As the differential input voltage increases, the input current of each pair will increase for one of the inputs and decrease for the other input. Large differential input voltages result in different input currents as the input stage enters various regions of operation. To reduce the influence of these changing input currents on system operation, use a low source resistance. Latch Pin Dynamics The internal latches of both LT1714 comparators retain the input data (output latched) when their respective latch pin goes high. Each latch pin will float to a low state when disconnected, but it is better to ground the latch when a flow-through condition is desired. The latch pin
U
is designed to be driven with either a TTL or CMOS output. It has built-in hysteresis of approximately 100mV, so that slow moving or noisy input signals do not impact latch performance. If only one of the comparators is being used at a given time, it is best to latch the second comparator to avoid any possibility of interactions between the comparators in the same package. High Speed Design Techniques A substantial amount of design effort has made the LT1714 relatively easy to use. As with most high speed comparators, careful attention to PC board layout and design is important in order to prevent oscillations. The most common problem involves power supply bypassing which is necessary to maintain low supply impedance. Resistance and inductance in supply wires and PC traces can quickly build up to unacceptable levels, thereby allowing the supply voltages to move as the supply current changes. This movement of the supply voltages will often result in improper operation. In addition, adjacent devices connected through an unbypassed supply can interact with each other through the finite supply impedances. Bypass capacitors furnish a simple solution to this problem by providing a local reservoir of energy at the device, thus keeping supply impedance low. Bypass capacitors should be as close as possible to the LT1714 supply pins. A good high frequency capacitor, such as a 0.1F ceramic, is recommended in parallel with a larger capacitor, such as a 4.7F tantalum. Poor trace routes and high source impedances are also common sources of problems. Keep trace lengths as short as possible and avoid running any output trace adjacent to an input trace to prevent unnecessary coupling. If output traces are longer than a few inches, provide proper termination impedances (typically 100 to 400) to eliminate any reflections that may occur. Also keep source impedances as low as possible, preferably less than 1k. The input and output traces should also be isolated from one another. Power supply traces can be used to achieve this isolation as shown in Figure 1, a typical topside layout of the LT1714 on a multilayer PC board. Shown is the topside metal etch including traces, pin escape vias and
W
UU
7
LT1714
APPLICATIO S I FOR ATIO
the land pads for a GN16 LT1714 and its adjacent X7R 0805 10nF bypass capacitors. The V +, V - and GND traces all shield the inputs from the outputs. Although the two V - pins are connected internally, they should be shorted together externally as well in order for both to function as shields. The same is true for the two V + pins. The two GND pins are not connected internally, but in most applications they are both connected directly to the ground plane. Another useful technique to avoid oscillations is to provide positive feedback, also known as hysteresis, from the output to the input. Increased levels of hysteresis, however, reduce the sensitivity of the device to input voltage levels, so the amount of positive feedback should be tailored to particular system requirements. The LT1714 is
1714 F01
Figure 1. Typical Topside Metal for Multilayer PCB Layout
RELATED PARTS
PART NUMBER LT1016 LT1116 LT1394 LT1671 LT1719 LT1720/LT1721 DESCRIPTION UltraFast Precision Comparator 12ns Single Supply Ground Sensing Comparator 7ns, UltraFast Single Supply Comparator 60ns, Low Power, Single Supply Comparator 4.5ns, Single Supply 3V/5V Comparator Dual/Quad, 4.5ns, Single Supply Comparator COMMENTS Industry Standard 10ns Comparator Single Supply Version of the LT1016 6mA Single Supply Comparator 450A Single Supply Comparator 4mA Comparator with Rail-to-Rail Outputs Dual/Quad Version of the LT1719
8
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
U
completely flexible regarding the application of hysteresis, due to rail-to-rail inputs and the complementary outputs. Specifically, feedback resistors can be connected from one or both outputs to their corresponding inputs without regard to common mode considerations. Figure 2 shows several configurations.
Q VIN
W
UU
+ -
50k 50 Q V + = 5V V - = -5V VHYST = 5mV (ALL 3 CASES) Q
50k 50 VIN
+ -
Q 100k
VREF
VIN+ VIN-
50
Q
+ -
100k
1714 F02
50
Q
Figure 2. Various Configurations for Introducing Hysteresis
1714I LT/LCG 0600 4K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 2000

▲Up To Search▲

Price & Availability of 1714I

	To Download 1714I Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .