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LTC1660 Micropower Octal 10-Bit DAC
FEATURES
s s s s s s s s s
DESCRIPTION
The LTC(R)1660 integrates eight high quality addressable 10-bit digital-to-analog converters (DACs) in a single tiny 16-pin Narrow SSOP package. Each buffered DAC consumes just 56A total supply current, yet is capable of supplying DC output currents in excess of 5mA and reliably driving capacitive loads up to 1000pF. Linear Technology's proprietary, inherently monotonic architecture provides excellent linearity while allowing for an exceptionally small external form factor. Ultralow supply current, power-saving Sleep Mode and extremely compact size make the LTC1660 ideal for battery-powered applications, while its straightforward usability, high performance and wide supply range make it an excellent choice as a general purpose converter.
, LTC and LT are registered trademarks of Linear Technology Corporation.
s
8 DACs in the Board Space of an SO-8 2.7V to 5.5V Single Supply Operation ICC(TYP) = 450A, Just 56A per DAC 1A Sleep Mode for Extended Battery Life Restores Last DAC Setting After Sleep Asynchronous CLR Function Power-On Reset Initializes All DACs to Zero Rail-to-Rail Voltage Outputs Drive up to 1000pF Three-Wire Serial Interface with Schmitt Trigger Inputs and Daisy-Chain Capability Differential Nonlinearity: 0.75LSB Max
APPLICATIONS
s s s s s
Mobile Communications Digitally Controlled Amplifiers and Attenuators Portable Battery-Powered Instruments Automatic Calibration for Manufacturing Remote Industrial Devices
BLOCK DIAGRA
GND 1
16 VCC
VOUT A
2
10-BIT DAC A
10-BIT DAC H
15 VOUT H
Differential Nonlinearity vs Input Code
1
14 VOUT G
VOUT B
3
10-BIT DAC B
10-BIT DAC G
0.8 0.6 0.4
VOUT C
4
10-BIT DAC C
10-BIT DAC F
13 VOUT F
0.2
LSB
0 -0.2
VOUT D
5
10-BIT DAC D
10-BIT DAC E
12 VOUT E
-0.4 -0.6
REF
6 CONTROL LOGIC ADDRESS DECODER
11
CLR
-0.8 -1 0 256 512 CODE 768 1023
1660 G02
CS/LD
7
10
DOUT
CLK
8
SHIFT REGISTER
9
DIN
1660 BD
U
W
U
1
LTC1660 ABSOLUTE
(Note 1)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW GND VOUT A VOUT B VOUT C VOUT D REF CS/LD CLK 1 2 3 4 5 6 7 8 16 VCC 15 VOUT H 14 VOUT G 13 VOUT F 12 VOUT E 11 CLR 10 DOUT 9 DIN
VCC to GND .............................................. - 0.5V to 7.5V Logic Inputs to GND ................................ - 0.5V to 7.5V VOUT A to VOUT H, REF .................. - 0.5V to (VCC + 0.5V) Maximum Junction Temperature ......................... 125C Operating Temperature Range LTC1660C.............................................. 0C to 70C LTC1660I ........................................... - 40C to 85C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................ 300C
ORDER PART NUMBER LTC1660CGN LTC1660CN LTC1660IGN LTC1660IN
GN PACKAGE 16-LEAD PLASTIC SSOP
N PACKAGE 16-LEAD PDIP
TJMAX = 125C, JA = 150C/W (GN) TJMAX = 125C, JA = 100C/W (N)
Consult factory for Military grade parts.
VCC = 2.7V to 5.5V, VREF VCC, VOUT Unloaded, TA = TMIN to TMAX, unless otherwise noted.
SYMBOL Accuracy Resolution Monotonicity DNL INL VOS FSE Differential Nonlinearity Integral Nonlinearity Offset Error VOS Temperature Coefficient Full-Scale Error Full-Scale Error Temperature Coefficient Reference Input Input Voltage Range Resistance Capacitance IREF VCC ICC Reference Current Positive Supply Voltage Supply Current Power Supply For Specified Performance VCC = 5V (Note 3) VCC = 3V (Note 3) Sleep Mode (Note 3) VOUT Shorted to GND (Sourcing) VOUT Shorted to VCC (Sinking) Rising (Notes 4, 5) Falling (Notes 4, 5) To 0.5LSB (Notes 4, 5)
q q q q q q
ELECTRICAL CHARACTERISTICS
PARAMETER
CONDITIONS
MIN 10 10
TYP
MAX
UNITS Bits Bits
VREF VCC - 0.1V (Note 2) VREF VCC - 0.1V (Note 2) VREF VCC - 0.1V (Note 2) Measured at Code 20 VCC = 5V, VREF = 4.096V
q q q q
0.1 0.6 10 15 3 30 0 35 65 15 0.001 2.7 450 340 1
0.75 2.5 30 15
V/C LSB V/C VCC V k pF 1 5.5 730 550 3 100 120 A V A A A mA mA V/s V/s s
q
Not in Sleep Mode (Note 6) Sleep Mode
q
q
DC Performance Short-Circuit Current Low Short-Circuit Current High AC Performance Voltage Output Slew Rate Voltage Output Settling Time 0.60 0.25 30
q q
2
U
LSB LSB mV
W
U
U
WW
W
LTC1660
VCC = 2.7V to 5.5V, VREF VCC, VOUT Unloaded, TA = TMIN to TMAX, unless otherwise noted.
SYMBOL Digital I/O VIH VIL VOH VOL ILK CIN Digital Input High Voltage Digital Input Low Voltage Digital Output High Voltage Digital Output Low Voltage Digital Input Leakage Digital Input Capacitance VCC = 2.7V to 5.5V VCC = 2.7V to 3.6V VCC = 4.5V to 5.5V VCC = 2.7V to 5.5V IOUT = - 1mA, DOUT Only IOUT = 1mA, DOUT Only VIN = GND to VCC (Note 6)
q q q q q q q q
ELECTRICAL CHARACTERISTICS
PARAMETER
CONDITIONS
MIN 2.4 2.0
TYP
MAX
UNITS V V
0.8 0.6 VCC - 1 0.4 10 10
V V V V A pF
TI I G CHARACTERISTICS
SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 PARAMETER DIN Valid to CLK Setup DIN Valid to CLK Hold CLK High Time CLK Low Time CS/LD Pulse Width LSB CLK High to CS/LD High CS/LD Low to CLK High DOUT Propagation Delay CLK Low to CS/LD Low CLR Pulse Width DIN Valid to CLK Setup DIN Valid to CLK Hold CLK High Time CLK Low Time CS/LD Pulse Width LSB CLK High to CS/LD High CS/LD Low to CLK High DOUT Propagation Delay CLK Low to CS/LD Low CLR Pulse Width VCC = 4.5V to 5.5V
VCC = 2.7V to 5.5V (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) CLOAD = 15pF (Note 6) (Note 6) (Note 6)
q q q q q q q q q q
The q denotes specifications which apply over the full operating temperature range. Note 1: Absolute maximum ratings are those values beyond which the life of a device may be impaired. Note 2: Nonlinearity and monotonicity are defined from code 20 to code 1023 (full scale). See Applications Information.
UW
(See Figure 1)
CONDITIONS
q q
MIN 40 0 30 30 30 30 30 5 20 100 60 0 50 50 50 50 50 5 30 120
TYP 15 -11 7 15 4 4 0 26 0 6 20 -14 8 12
MAX
UNITS ns ns ns ns ns ns ns
(Note 6) (Note 6) (Note 6) (Note 6) (Note 6) CLOAD = 15pF (Note 6) (Note 6) (Note 6)
q q q q q q q q
80
ns ns ns ns ns ns ns ns ns ns
47
150
ns ns ns
Note 3: Digital inputs at 0V or VCC. Note 4: Load is 10k in parallel with 100pF. Note 5: VCC = VREF = 5V. DAC switched between 0.1VFS and 0.9VFS, i.e., codes k = 102 and k = 922. Note 6: Guaranteed by design and not subject to test.
3
LTC1660 TYPICAL PERFOR A CE CHARACTERISTICS UW
Integral Nonlinearity (INL)
1 0.8 0.6 0.4 0.2 1 0.8 0.6 0.4 0.2
Differential Nonlinearity (DNL)
LSB
LSB
0 -0.2 -0.4 -0.6 -0.8 -1 0 256 512 CODE 768 1023
1660 G01
0 -0.2 -0.4 -0.6 -0.8 -1 0 256 512 CODE 768 1023
1660 G02
Minimum Supply Headroom vs Output Source Load Current
1400 1200 1000 VREF = 4.096V VOUT < 1LSB CODE = 1023 125C 1400 1200 1000
Minimum VOUT vs Output Sink Load Current
VCC = 5V CODE = 0
125C
VCC - VOUT (mV)
VOUT (mV)
800 600
25C -55C
800 25C 600 -55C 400 200 0
400 200 0 0 2
|I |
4 6 OUT (mA) (Sourcing)
8
10
1660 G03
0
2
|IOUT| (mA) (Sinking)
4
6
8
10
1660 G04
4
LTC1660 TYPICAL PERFOR A CE CHARACTERISTICS
Midscale Output Voltage vs Load Current
3 2.9 2.8 2.7
VOUT (V)
VREF = VCC CODE = 512 VCC = 5.5V
VOUT (V)
2.6 2.5 2.4 2.3 2.2 2.1 2 -30 -20 SOURCE -10 SINK 20 30
1660 G05
VCC = 5V
VCC = 4.5V
0 10 IOUT (mA)
Load Regulation vs Output Current
2 1.5 1 VCC = VREF = 5V CODE = 512 2 1.5 1
VOUT (LSB)
0.5 0 -0.5 -1 -1.5 -2 -2 SOURCE -1 0 IOUT (mA) SINK 1 2
1660 G07
VOUT (LSB)
UW
Midscale Output Voltage vs Load Current
2 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 -15 -12 -8 SOURCE SINK 8 12 15
1660 G06
VREF = VCC CODE = 512 VCC = 3.6V VCC = 3V
VCC = 2.7V
-4 0 4 IOUT (mA)
Load Regulation vs Output Current
VCC = VREF = 3V CODE = 512
0.5 0 -0.5 -1 -1.5 -2 -500 SOURCE 0 IOUT (A) SINK 500
1660 G08
5
LTC1660 TYPICAL PERFOR A CE CHARACTERISTICS
Large-Signal Step Response
5 CODE = 922 4 VCC = VREF = 5V 10% TO 90% STEP 2 ALL DIGITAL INPUTS SHORTED TOGETHER 1.6
SUPPLY CURRENT (mA)
SUPPLY CURRENT (A)
VOUT (V)
3
2
1
CODE = 102
0 0 20 40 60 TIME (s) 80 100
1660 G09
PIN FUNCTIONS
GND (Pin 1): System Ground. VOUT A to VOUT H (Pins 2-5 and 12-15): DAC Analog Voltage Outputs. The output range is 0 to VREF 1 - 1 1024 DIN (Pin 9): Serial Interface Data Input. Data on the DIN pin is shifted into the 16-bit register on the rising edge of CLK. CMOS and TTL compatible. DOUT (Pin 10): Serial Interface Data Output. Data appears on DOUT 16 positive CLK edges after being applied to DIN. May be tied to DIN of another LTC1660 for daisy-chain operaton. CMOS and TTL compatible. CLR (Pin 11): Asynchronous Clear Input. All internal shift and DAC registers are cleared to zero at the falling edge of the CLR signal, forcing the analog outputs to zero scale. CMOS and TTL compatible. VCC (Pin 16): Supply Voltage Input. 2.7V VCC 5.5V.
)
)
REF (Pin 6): Reference Voltage Input. 0V VREF VCC. CS/LD (Pin 7): Serial Interface Chip Select/Load Input. When CS/LD is low, CLK is enabled for shifting data on DIN into the register. When CS/LD is pulled high, CLK is disabled and data is loaded from the shift register into the specified DAC register(s), updating the analog output(s). CMOS and TTL compatible. CLK (Pin 8): Serial Interface Clock Input. CMOS and TTL compatible.
6
UW
Supply Current vs Logic Input Voltage
500 480 460 440 420 400 380 360 340 320 0 0 1 2 3 4 LOGIC INPUT VOLTAGE (V) 5
1660 G10
Supply Current vs Temperature
VCC = 5.5V VCC = 4.5V VCC = 3.6V
1.2
0.8
VCC = 2.7V
0.4
300 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
1660 G11
U
U
U
LTC1660
DEFINITIONS
Differential Nonlinearity (DNL): The difference between the measured change and the ideal 1LSB change for any two adjacent codes. The DNL error between any two codes is calculated as follows: DNL = (VOUT - LSB)/LSB Where VOUT is the measured voltage difference between two adjacent codes. Digital Feedthrough: The glitch that appears at the analog output caused by AC coupling from the digital inputs when they change state. The area of the glitch is specified in (nV)(sec). Full-Scale Error (FSE): The deviation of the actual fullscale voltage from ideal. FSE includes the effects of offset and gain errors (see Applications Information). Integral Nonlinearity (INL): The deviation from a straight line passing through the endpoints of the DAC transfer curve (Endpoint INL). Because the output cannot go below zero, the linearity is measured between full scale and the lowest code which guarantees the output will be greater than zero. The INL error at a given input code is calculated as follows: INL = [VOUT - VOS - (VFS - VOS)(code/1023)]/LSB Where VOUT is the output voltage of the DAC measured at the given input code. Least Significant Bit (LSB): The ideal voltage difference between two successive codes. LSB = VREF/1024 Resolution (n): Defines the number of DAC output states (2n) that divide the full-scale range. Resolution does not imply linearity. Voltage Offset Error (VOS): Nominally, the voltage at the output when the DAC is loaded with all zeros. A single supply DAC can have a true negative offset, but the output cannot go below zero (see Applications Information). For this reason, single supply DAC offset is measured at the lowest code that guarantees the output will be greater than zero.
BLOCK DIAGRA
W
U
U
GND
1
16 VCC
VOUT A
2
10-BIT DAC A
10-BIT DAC H
15 VOUT H
VOUT B
3
10-BIT DAC B
10-BIT DAC G
14 VOUT G
VOUT C
4
10-BIT DAC C
10-BIT DAC F
13 VOUT F
VOUT D
5
10-BIT DAC D
10-BIT DAC E
12 VOUT E
REF
6 CONTROL LOGIC ADDRESS DECODER
11
CLR
CS/LD
7
10
DOUT
CLK
8
SHIFT REGISTER
9
DIN
1660 BD
7
LTC1660 TI I G DIAGRA
CLK t9 DIN A3 A2 A1 X1 X0 t5 CS/LD t8 DOUT A3 A2 A1 X1 X0 A3
1660 TD
OPERATIO
Transfer Function The ideal transfer function for the LTC1660 is
VOUT(IDEAL) =
))
kV REF 1024
where k is the decimal equivalent of the binary DAC input code D9-D0 and VREF is the voltage at REF (Pin 6). Serial Interface Data on the DIN input is shifted into the 16-bit register (CS/LD must be held low) on the positive edge of CLK. The 4-bit DAC address, A3-A0, is loaded first (see Table 2), then the 10-bit input code, D9-D0, ordered MSB-to-LSB in each case. Two don't-care bits, X1 and X0, are loaded last. When the full 16-bit word has been shifted in, CS/LD is pulled high, loading the DAC register with the word and causing the addressed DAC output(s) to update (see Figure 2). The clock is disabled internally when CS/LD is high. Note: CLK must be low before CS/LD is pulled low. The buffered serial output of the shift register is available on the DOUT pin, which swings from GND to VCC. Data appears on DOUT 16 positive CLK edges after being applied to DIN. Multiple LTC1660's can be controlled from a single 3-wire serial port (i.e., CLK, DIN and CS/LD) by using the included "daisy-chain" facility. A series of m chips is configured by
8
W
t1 t2 t4 t3 t6 t7
U
UW
Figure 1
connecting each DOUT (except the last) to DIN of the next chip, forming a single 16m-bit shift register. The CLK and CS/LD signals are common to all chips in the chain. In use, CS/LD is held low while m 16-bit words are clocked to DIN of the first chip; CS/LD is then pulled high, updating all of them simultaneously. Sleep Mode DAC address 1110b is reserved for the special Sleep instruction (see Table 2). In this mode, internal bias currents are disabled while all digital circuitry stays fully active; static power consumption is thus virtually eliminated. The analog outputs are set in a high impedance state and all DAC settings are retained in memory so that when Sleep mode is exited, the outputs of DACs not updated by the Wake command are restored to their last active state. Sleep mode is initiated by performing a load sequence to address 1110b (the DAC input word D9-D0 is ignored). Once in Sleep mode, a load sequence to any other address (including "No Change" addresses 0000b and 1001-1101b) causes the LTC1660 to Wake. It is possible to keep one or more chips of a daisy chain in continuous Sleep mode by giving the Sleep instruction to these chips each time the active chips in the chain are updated.
LTC1660
OPERATIO
CLK
DIN
CS/LD
(ENABLE CLK)
DOUT
Table 1. LTC1660 Input Word
A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0
Address/Control
Voltage Outputs Each of the eight rail-to-rail output amplifiers contained in the LTC1660 can source or sink up to 5mA. The outputs swing to within a few millivolts of either supply rail when unloaded and have an equivalent output resistance of 85 when driving a load to the rails. The output amplifiers are stable driving capacitive loads up to 1000pF. A small resistor placed in series with the output can be used to achieve stability for any load capacitance. For example, a 0.1F load can be successfully driven by inserting a 110 resistor. The phase margin of the resulting circuit is 45, and increases monotonically from this point if larger values of resistance, capacitance or both are substituted for the values given.
U
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0 ADDRESS/CONTROL INPUT CODE INPUT WORD W0 (UPDATE OUTPUT) DON'T CARE A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0 A3 INPUT WORD W-1 INPUT WORD W0
1660 F02
Figure 2. Register Loading Sequence
Table 2. DAC Address/Control Functions
ADDRESS/CONTROL A3 Input Code Don't Care 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DAC STATUS No Change Load DAC A Load DAC B Load DAC C Load DAC D Load DAC E Load DAC F Load DAC G Load DAC H No Change No Change No Change No Change No Change No Change Load ALL DACs with Same 10-Bit Code SLEEP STATUS Wake Wake Wake Wake Wake Wake Wake Wake Wake Wake Wake Wake Wake Wake Sleep Wake
9
LTC1660
APPLICATIONS INFORMATION
Rail-to-Rail Output Considerations In any rail-to-rail DAC, the output swing is limited to voltages within the supply range. If the DAC offset is negative, the output for the lowest codes limits at 0V as shown in Figure 3b. Similarly, limiting can occur near full scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC as shown in Figure 3c. No full-scale limiting can occur if VREF is less than VCC - FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur.
OUTPUT VOLTAGE
0
OUTPUT VOLTAGE
0V NEGATIVE OFFSET INPUT CODE (b)
1660 F03
Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC
10
U
W
U
U
VREF = VCC
POSITIVE FSE
OUTPUT VOLTAGE
INPUT CODE (c) VREF = VCC
512 INPUT CODE (a)
1023
LTC1660
PACKAGE DESCRIPTION
0.007 - 0.0098 (0.178 - 0.249) 0.016 - 0.050 (0.406 - 1.270)
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.300 - 0.325 (7.620 - 8.255)
0.009 - 0.015 (0.229 - 0.381)
(
+0.035 0.325 -0.015 8.255 +0.889 -0.381
)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
Dimensions in inches (millimeters) unless otherwise noted. GN Package 16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.189 - 0.196* (4.801 - 4.978) 16 15 14 13 12 11 10 9 0.009 (0.229) REF
0.229 - 0.244 (5.817 - 6.198)
0.150 - 0.157** (3.810 - 3.988)
1 0.015 0.004 x 45 (0.38 0.10) 0 - 8 TYP 0.053 - 0.068 (1.351 - 1.727)
23
4
56
7
8 0.004 - 0.0098 (0.102 - 0.249)
0.008 - 0.012 (0.203 - 0.305)
0.025 (0.635) BSC
GN16 (SSOP) 0398
N Package 16-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.770* (19.558) MAX 16 15 14 13 12 11 10 9
0.255 0.015* (6.477 0.381)
1 0.130 0.005 (3.302 0.127) 0.020 (0.508) MIN
2
3
4
5
6
7
8
0.045 - 0.065 (1.143 - 1.651)
0.065 (1.651) TYP 0.125 (3.175) MIN 0.100 0.010 (2.540 0.254) 0.018 0.003 (0.457 0.076)
N16 1197
11
LTC1660
TYPICAL APPLICATION
4-Channel DAC with Increased Resolution
VCC GND R1 1k VOUT1 0.1F R2 255k VOUT B 3 10-BIT DAC B 10-BIT DAC G 14 VOUT G LTC1660 1 16 VCC
VOUT A
2
VOUT2
VOUT C
4
VOUT D
5
REF 4.096V CS/LD
6 CONTROL LOGIC ADDRESS DECODER
7
3-WIRE SERIAL INTERFACE
CLK
8
RELATED PARTS
PART NUMBER LTC1446/LTC1446L LTC1448 LTC1454/LTC1454L LTC1458/LTC1458L LTC1590 LTC1659 DESCRIPTION Dual 12-Bit VOUT DACs in SO-8 Package with Internal Reference Dual 12-Bit VOUT DAC in SO-8 Package Dual 12-Bit VOUT DACs in SO-16 Package with Added Functionality Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality Dual 12-Bit IOUT DAC in SO-16 Package Single Rail-to-Rail 12-Bit VOUT DAC in 8-Lead MSOP Package VCC: 2.7V to 5.5V COMMENTS LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V VCC = 2.7V to 5.5V, External Reference Can Be Tied to VCC LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V VCC = 4.5V to 5.5V, 4-Quadrant Multiplication Low Power Multiplying VOUT DAC. Output Swings from GND to REF. REF Input Can Be Tied to VCC
1660F LT/TP 0798 4K * PRINTED IN THE USA
12
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
U
10-BIT DAC A
10-BIT DAC H
15
VOUT H
VOUT4
10-BIT DAC C
10-BIT DAC F
13
VOUT F
VOUT3
10-BIT DAC D
10-BIT DAC E
12
VOUT E
11
CLR
10
DOUT DIN
SHIFT REGISTER
9
VOUT1 =
VREF 1024
))))
R2 R1 + R2 CODEA + R1 R1 + R2 255 256 CODEA + 1 256 CODEB
CODEB
=
4.096 1024
1660 TA01
(c) LINEAR TECHNOLOGY CORPORATION 1998

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