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| DRAM MODULE ABSOLUTE MAXIMUM RATINGS * Item Voltage on any pin relative VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol VIN, VOUT VCC Tstg PD IOS KMM372F80(8)3BK/BS Rating -0.5 to +4.6 -0.5 to +4.6 -55 to +125 9 50 Unit V V C W mA * Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70C) Item Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 3.0 0 2.0 -0.3*2 Typ 3.3 0 Max 3.6 0 VCC+0.3*1 0.8 Unit V V V V *1 : VCC+1.3V at pulse width15ns, which is measured at VCC. *2 : -1.3V at pulse width15ns, which is measured at VSS. DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted) Symbol ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 II(L) IO(L) VOH VOL Speedl -5 -6 Dont care -5 -6 -5 -6 Dont care -5 -6 Dont care Dont care KMM372F803BK/BS Min -- KMM372F883BK/BS Min -10 -5 2.4 Max 810 720 100 810 720 900 810 30 810 720 10 5 0.4 Max 1080 990 100 1080 990 990 900 30 1080 990 10 5 0.4 Unit mA mA mA mA mA mA mA mA mA mA uA uA V V -10 -5 2.4 - ICC1* : Operating Current * (RAS, CAS, Address cycling @tRC=min) ICC2 : Standby Current (RAS=CAS=W=VIH) ICC3* : RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min) ICC4* : Extended Data Out Mode Current * (RAS=VIL, CAS cycling : tHPC=min) ICC5 : Standby Current (RAS=CAS=W=Vcc-0.2V) ICC6* : CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min) I(IL) : Input Leakage Current (Any input 0VINVcc+0.3V, all other pins not under test=0 V) I(OL) : Output Leakage Current(Data Out is disabled, 0VVOUTVcc) VOH : Output High Voltage Level (IOH = -2mA) VOL : Output Low Voltage Level (IOL = 2mA) * NOTE : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one EDO mode cycle time, tHPC. DRAM MODULE CAPACITANCE (TA = 25C, f = 1MHz) Item Input capacitance[A0, B0, A1 - A12] Input capacitance[W0, W2, OE0, OE2] Input capacitance[RAS0, RAS2] Input capacitance[CAS0, CAS4] Input/Output capacitance[DQ0 - 71] Symbol CIN1 CIN2 CIN3 CIN4 CDQ Min - KMM372F80(8)3BK/BS Max 20 20 45 20 17 Unit pF pF pF pF pF AC CHARACTERISTICS (0CTA70C, VCC=3.3V0.3V. See notes 1,2.) Test condition : Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V, output loading CL=100pF Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z OE to output in Low-Z Output buffer turn-off delay from CAS Transition time(rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold referenced to CAS Read command hold referenced to RAS Write command set-up time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data set-up time Data hold time Refresh period(4K & 8K) CAS to W delay time RAS to W delay time Symbol Min -5 Max Min 104 153 50 18 30 8 8 8 1 30 50 13 36 8 15 10 10 5 5 0 7 30 0 0 -2 0 7 7 13 7 -2 13 64 33 68 38 82 10K 32 20 10K 18 50 8 8 8 1 40 60 15 38 10 18 13 10 5 8 0 10 35 0 0 -2 0 10 10 15 10 -2 15 64 10K 40 25 10K 18 50 60 20 35 84 128 -6 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns 7 7,13 9,13 9,13 13 8 8,13 7 13 4,13 10,13 13 13 13 13 13 3,4,10 3,4,5,13 3,10,13 3,13 3,13 6,11,13 2 Unit Note tRC tRWC tRAC tCAC tAA tCLZ tOLZ tCEZ tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCS tWCH tWP tRWL tCWL tDS tDH tREF tCWD tRWD DRAM MODULE AC CHARACTERISTICS (0CTA70C, VCC=3.3V0.3V. See notes 1,2.) Parameter Column address to W delay time CAS precharge time to W delay time CAS setup time(CAS-before-RAS refresh) CAS hold time(CAS-before-RAS refresh) RAS to CAS precharge time Access time from CAS precharge Hyper page cycle time Hyper page read-modify-write cycle time CAS precharge time(Hyper page cycle) RAS pulse width (Hyper page cycle) RAS hold time from CAS precharge W to RAS precharge time(C-B-R refresh) W to RAS hold time(C-B-R refresh) OE access time OE to data delay Output buffer turn off delay time from OE OE command hold time Output data hold time(C-B-R refresh) Output buffer turn off delay time from RAS Output buffer turn off delay time from W W to data delay OE to CAS hold time CAS hold time to OE OE precharge time W pulse width (Hyper page cycle) Present Detect Read Cycle PDE to Valid PD bit PDE to PD bit Inactive Symbol -5 Min 45 47 10 8 3 33 20 70 7 50 35 15 8 18 15 8 5 10 3 8 20 5 5 5 5 13 18 18 200K Max KMM372F80(8)3BK/BS -6 Min 53 58 10 8 3 40 25 77 10 60 40 15 8 20 18 8 5 10 3 8 20 5 5 5 5 13 18 18 200K Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 7 13 13 13 3,13 12 12 tAWD tCPWD tCSR tCHR tRPC tCPA tHPC tHPRWC tCP tRASP tRHCP tWRP tWRH tOEA tOED tOEZ tOEH tDOH tREZ tWEZ tWED tOCH tCHO tOEP tWPE 13 13 13 13 13 13 13 6,11 6,13 13 tPD tPDOFF 10 2 7 2 10 7 ns ns DRAM MODULE NOTES 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 1 TTL loads and 100pF. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. Assumes tha tRCDtRCD(max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 7. tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameter. They are included in the data sheet as electrical characteristics only. If tWCStWCS(min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. If tRWDtRWD(min), tCWDtCWD(min), tAWDtAWD(min) and tCPWDtCPWD(min). The cycle is a read-modify-write cycle and the data out will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of data out(at access time) is indeterminate. KMM372F80(8)3BK/BS 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are referenced to the CAS leading edge in early write cycles. 10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. 11. If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes high before RAS high going , the open circuit condition of the output is achieved by RAS going. 12. tASC 6ns. 13. The timing skew from the DRAM to the DIMM resulted from the addition of buffers. DRAM MODULE READ CYCLE KMM372F80(8)3BK/BS tRC tRAS RAS VIH VIL - tRP tCRP CAS VIH VIL - tCSH tRCD tRSH tCAS tCRP tRAD tASR A VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tRCS W VIH VIL - tRCH tRRH tWEZ tAA OE VIH VIL - tCEZ tOEZ tOEA DQ VOH VOL - tRAC OPEN tOLZ tCAC tCLZ tREZ DATA-OUT Dont care Undefined DRAM MODULE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN KMM372F80(8)3BK/BS tRC tRAS RAS VIH VIL - tRP tCSH tCRP CAS VIH VIL - tRCD tRAD tRSH tCAS tCRP tASR A VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tCWL tRWL tWCS W VIH VIL - tWCH tWP OE VIH VIL - tDS DQ VIH VIL - tDH DATA-IN Dont care Undefined DRAM MODULE WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN KMM372F80(8)3BK/BS tRC tRAS RAS VIH VIL - tRP tCRP CAS VIH VIL - tCSH tRCD tRSH tCAS tCRP tRAD tRAL tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tCWL tRWL W VIH VIL - tWP OE VIH VIL - tOED tDS tOEH tDH DATA-IN DQ VIH VIL - Dont care Undefined DRAM MODULE READ - MODIFY - WRITE CYCLE KMM372F80(8)3BK/BS tRAS RAS VIH VIL - tRWC tRP tCRP CAS VIH VIL - tRCD tRAD tRAH tRSH tCAS tASR VIH VIL - tASC tCAH tCSH A ROW ADDR COLUMN ADDRESS tAWD tCWD W VIH VIL - tRWL tCWL tWP tRWD OE VIH VIL - tOEA tOLZ tCLZ tCAC tAA tRAC VALID DATA-OUT tOED tOEZ tDS tDH VALID DATA-IN DQ VI/OH VI/OL - Dont care Undefined DRAM MODULE HYPER PAGE READ CYCLE KMM372F80(8)3BK/BS tRASP RAS VIH VIL o tRP tCSH tCRP CAS VIH VIL - tRHCP tHPC tCP tHPC tCAS tCP tHPC tCAS tCP tCAS tRCD tCAS tRAD tASR A VIH VIL - tRAH tASC tCAH tASC tCAH tASC tCAH COLUMN ADDR tASC tCAH tREZ ROW ADDR COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS tRRH tRCS W VIH VIL - tRCH tCPA tCAC tAA tCPA tCAC tOEA tCAC tAA tCPA tOCH tOEA tOEP tDOH VALID DATA-OUT tCAC tAA tCHO tOEP tAA OE VIH VIL - tCAC tRAC DQ VOH VOL - tOEA tOEZ VALID DATA-OUT VALID DATA-OUT tOEZ tOEZ tOLZ tCLZ VALID DATA-OUT Dont care Undefined DRAM MODULE HYPER PAGE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN KMM372F80(8)3BK/BS tRASP RAS VIH VIL o tRP tRHCP tCRP CAS VIH VIL - tHPC tRCD tCAS tRAD tCSH tASC tCP tCAS o tHPC tCP tRSH tCAS tASR A VIH VIL - tRAH tCAH tASC tCAH o tASC tCAH ROW ADDR. COLUMN ADDRESS COLUMN ADDRESS o COLUMN ADDRESS tWCS W VIH VIL - tWCH tWCS tWCH tWP tCWL o o o tWCS tWCH tWP tCWL tRWL tWP tCWL OE VIH VIL - tDS DQ VIH VIL - tDH VALID DATA-IN tDS tDH o VALID DATA-IN tDS tDH o VALID DATA-IN Dont care Undefined DRAM MODULE HYPER PAGE READ-MODIFY-WRITE CYCLE KMM372F80(8)3BK/BS RAS VIH VIL - tRASP tCSH tCRP tRSH tHPRWC tRCD tCAS tRAD tRAH tASR tASC COL. ADDR tRP tCP tCAS tRAL tASC COL. ADDR tCRP CAS VIH VIL - tCAH tCAH A VIH VIL - ROW ADDR tRCS W VIH VIL - tCWL tWP tCWD tAWD tCPWD tOEA tOED tRWL tCWL tWP tCWD tAWD tRWD tOEA tCAC tAA tRAC tCAC OE VIH VIL - tOED tDH tDS tAA tDH tOEZ tDS tOEZ DQ VI/OH VI/OL - tCLZ tOLZ VALID DATA-OUT tCLZ VALID DATA-IN tOLZ VALID DATA-OUT VALID DATA-IN Dont care Undefined DRAM MODULE HYPER PAGE READ AND WRITE MIXED CYCLE KMM372F80(8)3BK/BS tRASP RAS VIH VIL READ(tCAC) READ(tCPA) WRITE READ(tAA) tRP tHPC tCP CAS VIH VIL - tHPC tCP tCP tCAS tASC COL. ADDR tHPC tCAS tASC tCAH tRAD tASR tRAH tASC tCAS tCAH tCAS tCAH tCAH tASC COLUMN ADDRESS A VIH VIL - ROW ADDR COLUMN ADDRESS COL. ADDR tRCS W VIH VIL - tRCH tRCS tRCH tWCS tWCH tRCH tWPE tCLZ tCPA OE VIH VIL - tWED DQ VI/OH VI/OL - tOEA tCAC tAA tRAC tWEZ tDH tWEZ VALID DATA-OUT tDS VALID DATA-IN tAA VALID DATA-OUT tREZ VALID DATA-OUT Dont care Undefined DRAM MODULE RAS - ONLY REFRESH CYCLE* NOTE : W, OE, DIN = Dont care DOUT = OPEN tRC RAS VIH VIL - KMM372F80(8)3BK/BS tRP tRAS tCRP tRPC tCRP CAS VIH VIL - tASR A VIH VIL - tRAH ROW ADDR CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE , A = Dont care tRP RAS VIH VIL - tRC tRAS tRP tRPC tCP tCSR tCHR tRPC CAS VIH VIL - tWRP W VIH VIL - tWRH tCEZ DQ VOH VOL - OPEN Dont care Undefined * In RAS-only refresh cycle of 64Mb A-dile & B-die, when CAS signal transits from Low to High, the valid data may be cut off. DRAM MODULE HIDDEN REFRESH CYCLE ( READ ) KMM372F80(8)3BK/BS tRC RAS VIH VIL - tRP tRC tRAS tRP tRAS tCRP CAS VIH VIL - tRCD tRSH tCHR tRAD tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tRCS W VIH VIL - tRRH tWRH tWRP tAA OE VIH VIL - tOEA tOLZ tCAC tCLZ tRAC tOEZ DATA-OUT tCEZ tREZ tWEZ DQ VOH VOL - OPEN Dont care Undefined DRAM MODULE HIDDEN REFRESH CYCLE ( WRITE ) NOTE : DOUT = OPEN KMM372F80(8)3BK/BS tRC RAS VIH VIL - tRP tRC tRAS tRP tRAS tCRP tRCD tRSH tCHR CAS VIH VIL - tRAD tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tWRH tWCS W VIH VIL - tWRP tWCH tWP OE VIH VIL - tDS DQ VIH VIL - tDH DATA-IN Dont care Undefined DRAM MODULE CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE KMM372F80(8)3BK/BS tRP RAS VIH VIL VIH VIL - tRAS tCPT tCHR tRSH tCAS tRAL tASC tCAH tCSR CAS A VIH VIL - COLUMN ADDRESS READ CYCLE W OE VIH VIL VIH VIL - tWRP tWRH tAA tRCS tCAC tRRH tRCH DQ VOH VOL - tCLZ tOEA tOEZ DATA-OUT tCEZ tREZ tWEZ WRITE CYCLE W VIH VIL VIH VIL - tWRP tWRH tCWL tWCS tRWL tWCH tWP OE tDS DQ VIH VIL - tDH DATA-IN READ-MODIFY-WRITE tWRP W VIH VIL - tWRH tAWD tRCS tCAC tAA tOEA tCWD tWP tCWL tRWL OE VIH VIL - tOED tCLZ tOEZ tDS tDH DQ VI/OH VI/OL VALID DATA-OUT VALID DATA-IN Dont care Undefined NOTE : This timing diagram is applied to all devices besides 64M DRAM based modules. DRAM MODULE CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE, A = Dont care KMM372F80(8)3BK/BS tRP RAS VIH VIL - tRASS tRPS tRPC tCP tCHS tCSR tRPC CAS VIH VIL - tCEZ DQ VOH VOL - OPEN W VIH VIL - tWRP tWRH TEST MODE IN CYCLE NOTE : OE , A = Dont care tRC tRAS tRPC tCP CAS VIH VIL - tRP RAS VIH VIL - tRP tRPC tCSR tCHR tWTS W VIH VIL - tWTH tCEZ DQ VOH VOL - OPEN Dont care Undefined DRAM MODULE PACKAGE DIMENSIONS KMM372F80(8)3BK/BS Units : Inches (millimeters) 5.250 (133.350) 0.118 (3.000) 5.014 (127.350) 0.054 (1.372) R 0.079 (R 2.000) 0.1570.004 (4.0000.100) (31.75) 1.250 .118DIA.004 (3.000DIA.100) 0.350 (8.890) 0.250 (6.350) .450 (11.430) 1.450 (36.830) 4.550 (115.57) 0.250 (6.350) 2.150 (54.61) ( Front view ) 0.100Max (2.54Max) TSOPII 0.200Max (5.08Max) SOJ 0.165 Min (4.19 Min) (2.540Min) 0.100Min A B C (17.780) 0.0500.0039 (1.2700.10) 0.01Max (0.25 Max) 0.118 (3.000) ( Back view ) 0.250 (6.350) 0.250 (6.350) (2.540 Min) 0.100 Min 0.1230.0050 (3.125.125) 0.079.0040 (2.000.100) 0.1230.0050 (3.125.125) 0.079.0040 (2.000.100) 0.050 (1.270) Detail A Detail B Detail C Tolerances : .005(.13) unless otherwise specified The used device is 8Mx8 DRAM with EDO mode, SOJ or TSOPII. DRAM Part No. : KMM372F803BK/BS - KM48V8104BK, KM48V8104BS. KMM372F883BK/BS - KM48V8004BK, KM48V8004BS. 0.700 0.039.002 (1.000.050) |
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