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DN8667NS
8-Bit Shift Register Latch Constant Current Driver IC
s Overview
The DN8667NS is a semiconductor integrated circuit which incorporates a 8-bit shift register, a latch driver and a constant current driver to satisfy the demand for equalization of LED panel brightness. It also incorporates the serial-in and serial-out/parallel-out functions. It employs the Bi-CMOS process : The 8-step shift register block and latch block consist of CMOS while the 8-step parallel driver block is bipolar.
(0.4) 1 2 3 4 5 6 7 1.27 8 9 10 0.10.1 20 19 18 17 16 15 14 13 12 11
+ 0.1 0.2 - 0.05 0.90.25
Unit : mm
0.40.25
s Features
* Serial-in, serial-out/parallel-out * Cascade connection possible * Constant current output (0 to 100 mA able to be set by one external resistor) * Output-forced ON/OFF terminal attached (EN) * Input/Output CMOS compatible
7.60.3
(0.4)
20-pin SOP Package (SOP020-P-0300A)
s Application
* LED panel drive
s Block Diagram
1 2 8
Constant Current Output
Constant Current Output
Constant Current Output Current Set.
0.90.25
5.50.3
2.050.2
Gate Control Sig. Latch Control Sig. Data Input Shift Register Clock Input
Gate Latch Data Output Shift Register Shift Register
External Resistor
1
12.630.3
DN8667NS
s Absolute Maximum Rating (Ta = 25C)
Parameter Supply voltage Output voltage Output current Power dissipation* Operating ambient temperature Storage temperature Symbol VCC VO IO PD Topr Tstg Rating 0 to + 7.0 0 to + 14 150 1.28 -20 to + 85 -55 to + 150
Others
Unit V V mA W C C
* For printed board SM, it decreases with rate of 10.24 mW/C from Ta = 25 C.
s Recommended Operation Range (Ta=25 C)
Parameter Operating supply voltage Symbol VCC Range 4.5V to 5.5V
s Electrical Characteristics (VCC=5V,Ta=25 2C)
Parameter Positive direction Input voltage Negative direction Input current Output voltage (SOUT) Output current 1 (Qn) Output current 2 (Qn) Output current error between bits Output leak current Supply current Clock frequency Input pulse width Setting-up time Holding time Clock pulse rise time Clock pulse fall time Note) VCC= 5V unless otherwise specified. VT- IIH IIL VOH VOL IOI IOI DIO IOLK ICC1 ICC2 ICC3 fCLK tw tsu th tr tf Symbol VT+
{ {
Condition VSOUT = 0.1, VCC - 0.1V ISOUT = 20A IO (Qn) = -10A, 90mA VO (Qn) = 0.6V Iref = -2.5mA
min 0.35VCC 0.2VCC
typ
max 0.7VCC 0.55VCC 25
Unit V V A A V
V1H = 5.0V V1L = 0V IOH = - 0.4mA IOL = 1.6mA VO (Qn) = 0.5V VCC = 5.0V, Iref = -12mA VO (Qn) = 1.0V VO= 14V (Output OFF)
Total Driver Output
- 25 4.0 0.5 83 100 117 6 25 2 20 30 20 20 VCC=5.0V RL=50 CL=15pF 20 20 15 20 10 500 500
V mA mA % A mA mA mA MHZ ns ns ns ns ns ns ns ns
VCC=5.5V
Iref = 0mA Iref = -2.5mA Iref = -2.5mA
OFF ON
CLK CLK STB SIN STB SIN STB
Input Duty 40 to 60%
2
Others
s Pin Descriptions
Pin No. 1 2 3 4 5
7,8 10,11 13,14 16
DN8667NS
Symbol DGND SIN CLK STB
Pin name Digital ground Serial data input Clock input Strobe input Digital ground
Description It is the serial data input terminal for shift register. The value of shift register shifts at the rising edge of clock input. Setting the STB input to "H" forwards the data of shift register to the latch. When the STB input is set to "L" , even if the value of shift register changes, the value of latch is not changed. It outputs signals by using the polarity opposite to that of data taken into the latch. For example, when the value of serial input is "H" , the output becomes "L" level and the output is turned on. The output takes open collector form of NPN transistor. Output ground When the EN input is set to "H" , all the outputs are turned off, independent of condition of shift register or latch driver. It is the terminal which performs the serial-output of data inputted from the SIN. It connects the external resistor between RC and GND and sets the current of output block. * Output current calculation : ** RC terminal setting calculation :
Qn
Driver output
6
9,12 15
PGND EN SOUT
Output ground Enabling input Serial data output
17 18
19
RC
Constant current setting input
20 x VCC (V) IO (Qn) RRC () + 90 (A) 1 VCC (V) or RRC -180 IRC (A) 2 () Supply terminal
VCC (V) IRC 2 x RRC () +180 (A)
20
VCC
VCC
20 x 5 * Calculation example IO (Qn) 910 + 90 VCC = 5V RRC = 910 IO (Qn) 100mA
1 5 ** Calculation example RRC 2 0.0025 -180 VCC = 5V IRC = 0.0025A RRC 910 ()
3
DN8667NS
s Application Circuit
Others
DN8667NS LED Panel Block Diagram
SIN SOUT (18) VCC (20)
DN8667NS
SIN (2) CLK (3) ST B (4) EN (17)
DQ CP
DQ CP
DQ CP
DQ CP
DQ CP DGND (1)
Logic input
LD Q
LD Q
LD Q
LD Q
LD Q
PGND (6) (9) (12) (15) VLED RC (19) GND
LED
Current setting circuit
(5) Q0 (7) Q1 (8) Q2 (10) Q3 (16) Q7
LED
Scan input
GND
LED
s Function Table (Note)
Input Output
CLK
STB H L x x
EN L L H x
SIN Qn Qn Qn Qn
QO Qn nc H nc
Qm Qm-1 nc H nc
Q7 Q6 nc H nc
SOUT Q6 Q6 Q6 nc
(Note) H : High level, L : Low level, x : H or L Qm, Qn : H or L. However, for Qn, "H"= OFF, "L"= ON. : Shift from L to H, : Shift from H to L nc : No change
s Characteristics Curve PD -- Ta
1600
Power Dissipation PD (mW)
1400 1280 1200 1000 800 718 600 400 200 0
Glass epoxy printed board (50mm x 50mm x t0.8mm) Rthj-a=97.7C/W PD=1280 mW (25C)
Single unit Rthj-a=174.1C/W PD=718 mW (25C)
0
25
50
75
100
125
150
Ambient Temperature Ta (C)
4
Others
s Timing Chart
DN8667NS
1.Input timing 1/fCLK tWH (CLK) 5V 90% CLK 2.5V 10% 0V tr(CLK) 5V SIN tf(CLK) tsu(SIN) th(SIN) 90% 2.5V 10% 2.5V tWL(CLK)
2.Transmission delay time
5V CLK 2.5V 0V 2.5V
5V 2.5V 2.5V 2.5V 2.5V EN 2.5V 0V th(STB) VOH 2.5V 2.5V Qn VOL (VIL= 0V,VIH= 5.0V) tPLH 50% tPHL tPLH 50% 50% tPHL 50% 2.5V
0V 5V STB 0V
tsu(SIN)
th(SIN)
tsu(STB)
tw(STB) (VIL= 0V,VIH= 5.0V)
5
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2001 MAR

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