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ISP1581
Universal Serial Bus 2.0 high-speed interface device
Rev. 02 -- 23 October 2000 Objective specification
1. General description
The ISP1581 is a cost-optimized and feature-optimized Universal Serial Bus (USB) interface device, which fully complies with the Universal Serial Bus Specification Rev. 2.0. It provides high-speed USB communication capacity to systems based on a microcontroller or microprocessor. The ISP1581 communicates with the system's microcontroller/processor through a high-speed general-purpose parallel interface. The ISP1581 supports automatic detection of USB 2.0 system operation. The USB 1.1 fall-back mode allows the device to remain operational under full-speed conditions. It is designed as a generic USB interface device so that it can fit into all existing device classes, such as: Imaging Class, Mass Storage Devices, Communication Devices, Printing Devices and Human Interface Devices. The internal generic DMA block allows easy integration into data streaming applications. In addition, the various configurations of the DMA block are tailored for mass storage applications. The modular approach to implementing a USB interface device allows the designer to select the optimum system microcontroller from the wide variety available. The ability to re-use existing architecture and firmware investments shortens the development time, eliminates risk and reduces costs. The result is fast and efficient development of the most cost-effective USB peripheral solution. The ISP1581 is ideally suited for many types of peripherals, such as: printers; scanners; magneto-optical (MO), compact disc (CD), digital video disc (DVD) and Zip(R)/Jaz(R) drives; digital still cameras; USB-to-Ethernet links; cable and DSL modems. The low power consumption during `suspend' mode allows easy design of equipment that is compliant to the ACPITM, OnNowTM and USB power management requirements. The ISP1581 also incorporates features such as SoftConnectTM, a reduced frequency crystal oscillator and integrated termination resistors. These features allow significant cost savings in system design and easy implementation of advanced USB functionality into PC peripherals.
c c
Philips Semiconductors
ISP1581
USB 2.0 HS interface device
2. Features
s Complies fully with Universal Serial Bus Specification Rev. 2.0 s Complies with most Device Class specifications s High performance USB interface device with integrated Serial Interface Engine (SIE), FIFO memory, data transceiver and 3.3 V voltage regulators s Supports automatic USB 2.0 mode detection and USB 1.1 fall-back mode s High speed DMA interface s Fully autonomous and multi-configuration DMA operation s Up to 14 programmable USB endpoints with 2 fixed control IN/OUT endpoints s Integrated physical 8 kbyte of multi-configuration FIFO memory s Endpoints with double buffering to increase throughput and ease real-time data transfer s Bus independent interface with most microcontroller/microprocessors (16 Mbytes/s or 16 Mwords/s) s Bus-powered capability with low power consumption and low `suspend' current s 12 MHz crystal oscillator with integrated PLL for low EMI s Software controlled connection to the USB bus (SoftConnectTM) s Complies with the ACPITM, OnNowTM and USB power management requirements s Internal power-on and low-voltage reset circuit, also supporting a software reset s Operation over the extended USB bus voltage range (4.0 to 5.5 V) with 5 V tolerant I/O pads s Operating temperature range -40 to +85 C s 12 kV in-circuit ESD protection on human accessible pins such as D+ and D- s Full-scan design with high fault coverage (>99%) s Available in LQFP64 package.
3. Applications
s s s s s s Personal digital assistant (PDA) Mass storage device, e.g., Zip(R), Jaz(R), MO, CD, DVD drive Digital camera Communication device, e.g. router, modem Printer Scanner.
4. Ordering information
Table 1: Ordering information Package Name ISP1581BD LQFP64 Description Plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm Version SOT314-2 Type number
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5. Block diagram
Philips Semiconductors
to/from USB D+ D-
12 MHz
CS0, CS1, DA0*, DA1*, DA2 5 18, 17, 19, 20, 21 DMA HANDLER
DREQ, DACK, DIOR, DIOW 4 12, 13, 14, 15 11 16 EOT INTRQ IORDY*
XTAL1 6 5 60
XTAL2 59
3.3 V
40x PLL OSCILLATOR BIT CLOCK RECOVERY
1.5 k RPU 7 SoftConnect
DMA INTERFACE
22
40, 41, 44 to 57 MEMORY MANAGEMENT UNIT 19 DMA REGISTERS 20, 9
16 DATA0 to DATA15 BUS_CONF* 2 MODE0*, MODE1
RREF 8 12.2 k (0.1%)
USB 2.0 TRANSCEIVER
PHILIPS SIE 22 INTEGRATED RAM (8 KBYTE) MICROCONTROLLER HANDLER MICRO CONTROLLER INTERFACE 38, 39, 30 to 35 25, 29, 26, 27 8 AD0 to AD7 4 CS, ALE/A0, (R/W)/RD, DS/WR INT READY*
RESET
10
POWER-ON RESET
internal reset
VCC(5.0)
4
2, 37, 43, 64 5V
3.3 V VOLTAGE REGULATORS 3.3 V
digital supply analog supply
28 SYSTEM CONTROLLER
ISP1581
1, 36, 42, 61 4 DGND
3, 23 2 AGND
4
24, 58 2
63
62
MGT234
VCC(3.3) Vreg(3.3)
SUSPEND
WAKEUP
*Denotes shared pin usage
USB 2.0 HS interface device
(c) Philips Electronics N.V. 2000. All rights reserved.
ISP1581
The direction of pins DREQ, DACK, DIOR and DIOW is determined by bit MASTER (DMA Hardware register) and bit ATA_MODE (DMA Configuration register).
Fig 1. Block diagram.
Philips Semiconductors
ISP1581
USB 2.0 HS interface device
6. Pinning information
6.1 Pinning
62 WAKEUP 64 VCC(5.0) 58 VCC(3.3)
idth
63 SUSPEND
57 DATA15
56 DATA14
55 DATA13
54 DATA12
53 DATA11
52 DATA10
51 DATA9
50 DATA8
60 XTAL1
DGND 1 VCC(5.0) 2 AGND 3 Vreg(3.3) 4
D- D+
59 XTAL2
61 DGND
49 DATA7
48 DATA6 47 DATA5 46 DATA4 45 DATA3 44 DATA2 43 VCC(5.0) 42 DGND 41 DATA1
5 6
RPU 7 RREF 8
ISP1581BD
MODE1 9 RESET 10 EOT 11 DREQ 12 DACK 13 DIOR 14 DIOW 15 INTRQ 16 MODE0/DA1 20 DA2 21 READY/IORDY 22 AGND 23 VCC(3.3) 24 CS 25 (R/W)/RD 26 DS/ WR 27 INT 28 ALE/A0 29 AD0 30 AD1 31 CS1 17 CS0 18 BUS_CONF/DA0 19 AD2 32 40 DATA0 39 AD7 38 AD6 37 VCC(5.0) 36 DGND 35 AD5 34 AD4 33 AD3
MBL248
Fig 2. Pin configuration LQFP64.
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ISP1581
USB 2.0 HS interface device
6.2 Pin description
Table 2: Symbol [1] DGND VCC(5.0) AGND Vreg(3.3) Pin description for LQFP64 Pin 1 2 3 5 Type [2] Description digital ground supply voltage (3.3 or 5.0 V) analog ground regulated supply voltage (3.3 V 10%) from internal regulator; supplies internal analog circuits; used to connect decoupling capacitor and 1.5 k pull-up resistor on D+ line Remark: Cannot be used to supply external devices. D- D+ RPU RREF MODE1 5 6 7 8 9 AI/O AI/O AI AI I USB D- connection (analog) USB D+ connection (analog) connection for external pull-up resistor for USB D+ line; must be connected to Vreg(3.3) via a 1.5 k resistor connection for external bias resistor; must be connected to ground via a 12.2 k ( 0.1%) resistor selects function of pin ALE/A0 (in Split Bus mode only): 0 -- ALE function (address latch enable) 1 -- A0 function (address/data indicator). Remark: Connect to VCC(5.0) in Generic Processor mode. RESET 10 I reset input (Schmitt trigger); a LOW level produces an asynchronous reset; connect to VCC for power-on reset (internal POR circuit) End Of Transfer input (programmable polarity, see Table 37); used in DMA slave mode only DMA request (programmable polarity); direction depends on the bit MASTER in the DMA Hardware register (DMA master: input, DMA slave: output); see Table 37 DMA acknowledge (programmable polarity); direction of depends on bit MASTER in the DMA Hardware register (DMA slave: input, DMA master: output); see Table 37 DMA read strobe (programmable polarity); direction depends on bit MASTER in the DMA Hardware register (DMA slave: input, DMA master: output); see Table 37 DMA write strobe (programmable polarity); direction depends on bit MASTER in the DMA Hardware register (DMA slave: input, DMA master: output); see Table 37 interrupt request input from ATA/ATAPI peripheral chip select output for ATAPI device chip select output for ATAPI device during power-up: input to select the bus configuration 0 -- Split Bus mode; multiplexed 8-bit address/data bus on AD[7:0], separate 8/16-bit DMA data bus on DATA[15:0] 1 -- Generic Processor mode; separate 8-bit address on AD[7:0], 16-bit DMA data bus on DATA[15:0]. normal operation: address output to select the task file register of an ATAPI device
9397 750 07648 (c) Philips Electronics N.V. 2000. All rights reserved.
EOT DREQ
11 12
I I/O
DACK
13
I/O
DIOR
14
I/O
DIOW
15
I/O
INTRQ CS1 CS0 BUS_CONF/ DA0
16 17 18 19
I O O I/O
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ISP1581
USB 2.0 HS interface device
Pin description for LQFP64 ...continued Pin 20 Type [2] I/O Description during power-up: input to select the read/write strobe functionality in generic processor mode 0 -- Motorola style: pin 26 is R/W and pin 27 is DS 1 -- 8051 style: pin 26 is RD and pin 27 is WR normal operation: address output to select the task file register of an ATAPI device
Table 2: Symbol [1]
MODE0/DA1
DA2 READY/ IORDY
21 22
O I/O
address output to select the task file register of an ATAPI device Generic processor mode: ready signal (READY; output) A LOW level signals that ISP1581 is processing a previous command or data and is not ready for the next command or data transfer; a HIGH level signals that ISP1581 is ready for the next microprocessor read or write. Split Bus mode: DMA ready signal (IORDY; input); used for accessing ATAPI peripherals (PIO and UDMA modes only).
AGND VCC(3.3) CS (R/W)/RD
23 24 25 26
I I
analog ground supply voltage (3.3 V 10%); supplies internal digital circuits chip select input input; function is determined by input MODE0 at power-up: MODE0 = 0 -- pin functions as R/W (Motorola style) MODE0 = 1 -- pin functions as RD (8051 style).
DS/WR
27
I
input; function is determined by input MODE0 at power-up: MODE0 = 0 -- pin functions as DS (Motorola style) MODE0 = 1 -- pin functions as WR (8051 style).
INT ALE/A0
28 29
O I
interrupt output; programmable polarity (active HIGH or LOW) and signaling (edge or level triggered) input; function determined by input MODE1 during power-up: MODE1 = 0 -- address latch enable; a falling edge latches the address on the multiplexed address/data bus (AD[7:0]) MODE1 = 1 -- address/data selection on AD[7:0]; a logic 1 indicates that an address will be written at the next WR pulse; a logic 0 indicates that data will be written at the next WR pulse; used in Split Bus mode only.
AD0 AD1 AD2 AD3 AD4 AD5 DGND VCC(5.0) AD6
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30 31 32 33 34 35 36 37 38
I/O I/O I/O I/O I/O I/O I/O
bit 0 of multiplexed address/data bit 1 of multiplexed address/data bit 2 of multiplexed address/data bit 3 of multiplexed address/data bit 4 of multiplexed address/data bit 5 of multiplexed address/data digital ground supply voltage (3.3 or 5.0 V) bit 6 of multiplexed address/data
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ISP1581
USB 2.0 HS interface device
Pin description for LQFP64 ...continued Pin 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 Type [2] I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O Description bit 7 of multiplexed address/data bit 0 of bidirectional data bit 1 of bidirectional data digital ground supply voltage (3.3 or 5.0 V) bit 2 of bidirectional data bit 3 of bidirectional data bit 4 of bidirectional data bit 5 of bidirectional data bit 6 of bidirectional data bit 7 of bidirectional data bit 8 of bidirectional data bit 9 of bidirectional data bit 10 of bidirectional data bit 11 of bidirectional data bit 12 of bidirectional data bit 13 of bidirectional data bit 14 of bidirectional data bit 15 of bidirectional data supply voltage (3.3 V 10%); supplies internal digital circuits crystal oscillator output (12 MHz); connect a fundamental parallel-resonant crystal; leave this pin open when using an external clock source on pin XTAL1 crystal oscillator input (12 MHz); connect a fundamental parallel-resonant crystal or an external clock source (leaving pin XTAL2 unconnected) digital ground wake-up input (edge triggered); a LOW-to-HIGH transition generates a remote wake-up from `suspend' state 'suspend' state indicator output (4 mA); used as a power switch control output (active LOW) for powered-off application or as a resume signal to the CPU (active HIGH) for powered-on application supply voltage (3.3 or 5.0 V)
Table 2: Symbol [1] AD7 DATA0 DATA1 DGND VCC(5.0) DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 VCC(3.3) XTAL2
XTAL1
60
I
DGND WAKEUP SUSPEND
61 62 63
I O
VCC(5.0)
[1] [2]
64
-
Symbol names with an overscore (e.g. NAME) represent active LOW signals. All outputs and I/O pins can source 4 mA of current.
7. Functional description
The ISP1581 is a high-speed USB device controller. It implements the USB 2.0/1.1 physical layer, the packet protocol layer and maintains up to 16 USB endpoints concurrently (2 control, 14 configurable). USB Chapter 9 protocol handling is executed by means of external firmware.
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ISP1581
USB 2.0 HS interface device
The ISP1581 has a fast general-purpose interface for communication with most types of microcontrollers/processors. This Microcontroller Interface is configured by pins BUS_CONF, MODE1 and MODE0 to accommodate most interface types. Two bus configurations are available, selected via input BUS_CONF during power-up:
* Generic Processor mode (BUS_CONF = 1):
- AD[7:0]: 8-bit address bus (selects target register) - DATA[15:0]: 16-bit data bus (shared by processor and DMA) - Control signals: R/W and DS or RD and WR (selected via pin MODE0) - DMA interface (generic slave mode only): uses lines DATA[15:0] as data bus, DIOR and DIOW as dedicated read and write strobes.
* Split Bus mode (BUS_CONF = 0):
- AD[7:0]: 8-bit local microprocessor bus (multiplexed address/data) - DATA[15:0]: 16-bit DMA data bus - Control signals: CS, ALE or A0 (selected via pin MODE1), R/W and DS or RD and WR (selected via pin MODE0) - DMA interface (master or slave mode): uses DIOR and DIOW as dedicated read and write strobes. For high-bandwidth data transfer, the integrated DMA handler can be invoked to transfer data to/from external memory or devices. The DMA Interface can be configured by writing to the proper DMA registers (see Section 9.4). The ISP1581 supports high-speed USB 2.0 and full-speed USB 1.1 signaling. Detection of the USB signaling speed is done automatically. ISP1581 has 8 kbytes of internal FIFO memory, which is shared among the enabled USB endpoints. There are 14 configurable data endpoints and 2 control endpoints. Any of the 14 data endpoints can be separately enabled or disabled. The endpoint type (interrupt, isochronous or bulk) and packet size of these endpoints can be individually configured depending on the requirements of the application. Optional double buffering increases the data throughput of the data endpoints. The ISP1581 requires a single supply of 3.0 V or 5.0 V, depending on the I/O voltage. It has 5.0 V tolerant I/O pads and has an internal 3.3 V regulator for powering the analog transceiver. It supports bus-powered operation with a `suspend' current below 500 A. The ISP1581 operates on a 12 MHz crystal oscillator. An integrated 40x PLL clock multiplier generates the internal sampling clock of 480 MHz.
7.1 USB 2.0 transceiver
The analog transceiver interfaces directly to the USB cable via integrated termination resistors. The high-speed transceiver requires an external resistor (12.2 k 0.1%) between pin RREF and ground to ensure an accurate current mirror. A full-speed transceiver is integrated as well. This makes the ISP1581 compliant with USB 2.0
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ISP1581
USB 2.0 HS interface device
and USB 1.1, supporting both the high-speed and full-speed physical layer. After automatic speed detection, the Philips Serial Interface Engine sets the transceiver to use either high-speed or full-speed signaling.
7.2 Philips Serial Interface Engine (SIE)
The Philips SIE implements the full USB protocol layer. It is completely hardwired for speed and needs no firmware intervention. The functions of this block include: synchronization pattern recognition, parallel/serial conversion, bit (de-)stuffing, CRC checking/generation, Packet IDentifier (PID) verification/generation, address recognition, handshake evaluation/generation.
7.3 Voltage regulators
Two 5 V to 3.3 V voltage regulators are integrated on-chip to separately supply the analog transceiver and the internal logic. The analog supply voltage is available at pin Vreg(3.3) to supply an external 1.5 k pull-up resistor on the D+ line. Remark: Pin Vreg(3.3) cannot be used to supply external devices.
7.4 Memory Management Unit (MMU) and integrated RAM
The MMU and the integrated RAM provide the conversion between the USB speed (full speed: 12 Mbit/s, high speed: 480 Mbit/s) and the Microcontroller Handler or the DMA Handler. The data from the USB Bus is stored in the integrated RAM, which is cleared only when the microcontroller clears the endpoint buffer or when the DMA Handler has read/written all data from/to the endpoint buffer. A total of 8 kbytes RAM is available for buffering.
7.5 SoftConnect
The connection to the USB is established by pulling the D+ line (for high-speed devices) HIGH through a 1.5 k pull-up resistor. In the ISP1581 an external 1.5 k pull-up resistor must be connected between pins RPU and Vreg(3.3). The RPU pin connects the pull-up resistor to the D+ line, when bit SOFTCT in the Mode register is set (see Table 7). After a hardware reset the pull-up resistor is disconnected by default (SOFTCT = 0). Bit SOFTCT remains unchanged by a USB bus reset.
7.6 Bit clock recovery
The bit clock recovery circuit recovers the clock from the incoming USB data stream using 4x over-sampling principle. It is able to track the jitter and the frequency drift as specified by the USB specification.
7.7 Multiplying PLL oscillator
A 12 MHz to 480 MHz clock multiplier Phase-Locked Loop (PLL) is integrated on-chip. This allows the use of a low-cost 12 MHz crystal, which also minimizes EMI. No external components are needed for the operation of the PLL.
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ISP1581
USB 2.0 HS interface device
7.8 Microcontroller Interface and Microcontroller Handler
The Microcontroller Interface allows direct interfacing to most microcontrollers. The interface is configured at power-up via inputs BUS_CONF, MODE1 and MODE0. When BUS_CONF is set to logic 1, the Microcontroller Interface switches to the Generic Processor mode in which AD[7:0] is the 8-bit address bus and DATA[15:0] is the separate 16-bit data bus. If BUS_CONF is made logic 0, the interface is in the Split Bus mode, where AD[7:0] is the local microprocessor bus (multiplexed address/data) and DATA[15:0] is used as the DMA bus. If pin MODE0 is set to logic 1, pins RD and WR are the read and write strobes (8051 style). If pin MODE0 is logic 0, pins R/W and DS pins represent the direction and data strobe (Motorola style). When pin MODE1 is made logic 0, ALE is used to latch the multiplexed address on pins AD[7:0]. If pin MODE1 is set to logic 1, A0 is used to indicate address or data. Pin MODE1 is only used in Split Bus mode: in Generic Processor mode it must be tied to VCC(5.0) (logic 1). The Microcontroller Handler allows the external microcontroller to access the register set in the Philips SIE as well as the DMA Handler. The initialization of the DMA configuration is done via the Microcontroller Handler.
7.9 DMA Interface and DMA Handler
The DMA block can be subdivided into two blocks: the DMA Handler and the DMA Interface. The firmware writes to the DMA Command register to start a DMA transfer (see Table 30). The command opcode determines whether a generic DMA, PIO, MDMA or UDMA transfer will start. The Handler interfaces to the same FIFO (internal RAM) as used by the USB core. Upon receiving the DMA Command, the DMA Handler directs the data from the internal RAM to the external DMA device and vice versa. The DMA Interface configures the timings and how the DMA data is accessed. Data can be transferred either using DIOR and DIOW strobes or by the DACK and DREQ handshakes. The different DMA configurations are set up by writing to the DMA Configuration register (see Table 35). For an IDE-based storage interface, the applicable DMA modes are PIO (Parallel I/O), MDMA (Multiword DMA; ATA), and UDMA (Ultra DMA; ATA). For a generic DMA interface, the DMA modes that can be used are Generic DMA (Slave) and MDMA (Master).
7.10 System Controller
The System Controller implements the USB power-down capabilities of the ISP1581. Two modes are supported during `suspend' state: powered-on and powered-off. These modes are selected via bit PWROFF in the Mode register (see Table 7). Registers are protected against data corruption during wake-up following a `resume'.
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USB 2.0 HS interface device
8. Modes of operation
The ISP1581 has two bus configuration modes, selected via pin BUS_CONF/DA0 at power-up:
* Split Bus mode (BUS_CONF = 0): 8-bit multiplexed address/data bus and
separate 8-bit/16-bit DMA bus
* Generic Processor mode (BUS_CONF = 1); separate 8-bit address and 16-bit
data bus Details of the bus configurations for each mode are given in Table 3. Typical interface circuits for each mode are given in Section 13 "Application information".
Table 3: Bus configuration modes PIO width AD[7:0] A[7:0] D[15:0] DMA width DMAWD = 0 DMAWD = 1 0 1 D[7:0] D[7:0] D[15:0] D[15:0] Split Bus mode: multiplexed address/data on pins AD[7:0]; separate 8/16-bit DMA bus on pins DATA[15:0] Generic Processor mode: separate 8-bit address on pins AD[7:0]; 16-bit data (PIO and DMA) on pins DATA[15:0] Description
BUS_CONF
9. Register descriptions
Table 4: Name Initialization registers Address Mode Interrupt Configuration Interrupt Enable DMA Configuration DMA Hardware Data flow registers Endpoint Index Control Function Data Port Buffer Length Endpoint MaxPacketSize Endpoint Type Short Packet endpoints endpoint endpoint endpoint endpoint endpoint endpoint 2C 28 20 1C 04 08 24 endpoint selection, data flow direction endpoint buffer management data access to endpoint FIFO packet size counter maximum packet size selects endpoint type: control, isochronous, bulk or interrupt short packet received on OUT endpoint 1 1 2 2 2 2 2 device device device device DMA controller DMA controller 00 0C 10 14 38 3C USB device address + enable power-down options, global interrupt enable, SoftConnect interrupt sources, trigger mode, output polarity interrupt source enabling see DMA registers see DMA registers 1 1 1 4 2 1 Register summary Destination Address (Hex) Description Size (bytes)
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USB 2.0 HS interface device
Table 4: Name
Register summary...continued Destination Address (Hex) 30 34 38 (byte 0) 39 (byte 1) Description Size (bytes) 1 4
DMA registers DMA Command DMA Transfer Counter DMA Configuration DMA controller DMA controller DMA controller controls all DMA transfers sets byte count for DMA Transfer
sets GDMA configuration (counter enable, 1 burst length, data strobing, bus width) sets ATA configuration (IORDY enable, mode selection: ATA/UDMA/MDMA/PIO) 1
DMA Hardware 1F0 Task File 1F1Task File 1F2 Task File 1F3 Task File 1F4 Task File 1F5 Task File 1F6 Task File 1F7 Task File 3F6 Task File 3F7 Task File DMA Interrupt Reason DMA Interrupt Enable DMA Endpoint DMA Strobe Timing General registers Interrupt Chip ID Frame Number Scratch Unlock Device Test Mode
DMA controller ATAPI peripheral ATAPI peripheral ATAPI peripheral ATAPI peripheral ATAPI peripheral ATAPI peripheral ATAPI peripheral ATAPI peripheral ATAPI peripheral ATAPI peripheral DMA controller DMA controller DMA controller DMA controller device device device device device PHY
3C 40 48 49 4A 4B 4C 4D 44 4E 4F 50 (byte 0) 51 (byte 1) 54 (byte 0) 55 (byte 1) 58 60 18 70 74 78 7C 84
endian type, master/slave selection, signal 1 polarity for DACK, DREQ, DIOW, DIOR single address word register: byte 0 (lower 2 byte) is accessed first IDE device access IDE device access IDE device access IDE device access IDE device access IDE device access IDE device access (write only; reading returns 00H) IDE device access IDE device access shows reason (source) for DMA interrupt enables DMA interrupt sources selects endpoint FIFO, data flow direction strobe duration in UDMA/MDMA mode shows interrupt sources product ID code and hardware version last successfully received Start Of Frame: lower byte (byte 0) is accessed first allows save/restore of firmware status during `suspend' direct setting of D+, D- states, loopback mode, internal transceiver test (PHY) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 3 2 2
re-enables register access after `suspend' 2 1
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9.1 Register access
Register access depends on the bus width used:
* 8-bit bus: multi-byte registers are accessed lower byte (LSB) first. * 16-bit bus: for single-byte registers the upper byte (MSB) must be ignored.
Endpoint specific registers are indexed via the Endpoint Index register. The target endpoint must be selected first, before accessing the following registers:
* * * * * *
Buffer Length Control Function Data Port Endpoint MaxPacketsize Endpoint Type Short Packet.
9.2 Initialization registers
9.2.1 Address register (address: 00H) This register is used to set the USB assigned address and enable the USB device. Table 5 shows the Address register bit allocation. The DEVEN and DEVADDR bits will be cleared whenever a bus reset, a power-on reset or a soft reset occurs. In response to the standard USB request SET_ADDRESS, the firmware must write the (enabled) device address to the Address register, followed by sending an empty packet to the host. The new device address is activated when the host acknowledges the empty packet.
Table 5: Bit Symbol Reset Bus reset Access Address register: bit allocation 7 DEVEN 0 0 R/W Table 6: Bit 7 6 to 0 6 5 4 3 DEVADDR[6:0] 00H 00H R/W Endpoint Configuration register: bit description Symbol DEVEN DEVADDR[6:0] Description A logic 1 enables the device. This field specifies the USB device address. 2 1 0
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9.2.2
Mode register (address: 0CH) This register consists of 1 byte (bit allocation: see Table 7). In 16-bit bus mode the upper byte is ignored. The Mode register controls the resume, suspend and wake-up behaviour, interrupt activity, soft reset, clock signals and SoftConnect operation. This register also controls the Power Off mode during `suspend' state.
Table 7: Bit Symbol Reset
Mode register: bit allocation 7 CLKAON 0 0 R/W 6 SNDRSU 0 0 R/W Table 8: Bit 7 5 GOSUSP 0 0 R/W 4 SFRESET 0 0 R/W 3 GLINTENA 0 unchanged R/W 2 WKUPCS 0 0 R/W 1 PWROFF 0 unchanged R/W 0 SOFTCT 0 unchanged R/W
Bus reset Access
Mode register: bit description Symbol CLKAON Description Clock Always On: A logic 1 indicates that the internal clocks are always running even during `suspend' state. A logic 0 switches off the internal oscillator and PLL, when they are not needed. During `suspend' state, this bit must be set to logic 0 to meet the suspend current requirements. The clock is stopped after a delay of approximately 2 ms, following the setting of bit GOSUSP. Send Resume: Writing a logic 1 followed by a logic 0 will generate an upstream `resume' signal of 10 ms duration, after a 5 ms delay. Go Suspend: Writing a logic 1 followed by a logic 0 will activate `suspend' mode. Soft Reset: Writing a logic 1 followed by a logic 0 will enable a software-initiated reset to ISP1581. A soft reset is similar to a hardware-initiated reset (via the RESET pin). Global Interrupt Enable: A logic 1 enables all interrupts. Individual interrupts can be masked OFF by clearing the corresponding bits in the Interrupt Enable register. Bus reset value: unchanged. Wake-up on Chip Select: A logic 1 enables remote wake-up via a LOW level on input CS. Power Off mode: A logic 1 enables powering-off during `suspend' state. Output SUSPEND is configured as a power switch control signal for external devices (HIGH during `suspend'). Bus reset value: unchanged. SoftConnect: A logic 1 enables the connection of the 1.5 k pull-up resistor on pin RPU to the D+ line. Bus reset value: unchanged.
6
SNDRSU
5 4
GOSUSP SFRESET
3
GLINTENA
2 1
WKUPCS PWROFF
0
SOFTCT
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9.2.3
Interrupt Configuration register (address: 10H) This 1-byte register determines the behaviour and polarity of the INT output. The bit allocation is shown in Table 9. When the USB SIE receives or generates a ACK, NAK or STALL, it will generate interrupts depending on three Debug mode bit fields:
* CDBGMOD[1:0]: interrupts for the Control endpoint 0 * DDBGMODIN[1:0]: interrupts for the DATA IN endpoints 1 to 7 * DDBGMODOUT[1:0]: interrupts for the DATA OUT endpoints 1 to 7.
The Debug mode settings for CDBGMOD, DDBGMODIN and DDBGMODOUT allow the user to individually configure when the ISP1581 will send an interrupt to the external microprocessor. Table 11 lists the available combinations. Bit INTPOL controls the signal polarity of the INT output (active HIGH or LOW, rising or falling edge). For level-triggering bit INTLVL must be made logic 0. By setting INTLVL to logic 1 an interrupt will generate a pulse of 60 ns (edge-triggering).
Table 9: Bit Symbol Reset Bus reset Access Interrupt Configuration register: bit allocation 7 6 5 4 CDBGMOD[1:0] 03H 03H R/W DDBGMODIN[1:0] 03H 03H R/W
3 03H 03H R/W
2
1 INTLVL 0 unchanged R/W
0 INTPOL 0 unchanged R/W
DDBGMODOUT[1:0]
Table 10: Interrupt Configuration register: bit description Bit 7 to 6 5 to 4 3 to 2 1 Symbol CDBGMOD[1:0] DDBGMODIN[1:0] DDBGMODOUT[1:0] INTLVL Description Control 0 Debug Mode: values see Table 11 Data Debug Mode IN: values see Table 11 Data Debug Mode OUT: values see Table 11 Interrupt Level: selects the signaling mode on output INT (0 = level, 1 = pulsed). In pulsed mode an interrupt produces a 60 ns pulse. Bus reset value: unchanged. Interrupt Polarity: selects signal polarity on output INT (0 = active LOW, 1 = active HIGH). Bus reset value: unchanged.
0
INTPOL
Table 11: Debug mode settings Value 00H 01H 1XH
[1]
CDBGMOD Interrupt on all ACK, STALL and NAK Interrupt on all ACK and STALL Interrupt on all ACK, STALL and first NAK [1]
DDBGMODIN Interrupt on all ACK and NAK Interrupt on ACK Interrupt on all ACK and first NAK [1]
DDBGMODOUT Interrupt on all ACK, STALL, NYET and NAK Interrupt on ACK, STALL and NYET Interrupt on all ACK, STALL, NYET and first NAK [1]
First NAK: the first NAK on an IN or OUT token after a previous ACK response.
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9.2.4
Interrupt Enable register (address: 14H) This register enables/disables individual interrupt sources. The interrupt for each endpoint can be individually controlled via the associated IEPnRX or IEPnTX bits (`n' representing the endpoint number). All interrupts can be globally disabled via bit GLINTENA in the Mode Register (see Table 7). An interrupt is generated when the USB SIE receives or generates an ACK, NAK or STALL on the USB bus. The interrupt generation depends on the Debug mode settings of bit fields CDBGMOD, DDBGMODIN and DDBGMODOUT. All data IN transactions use the Transmit buffers (TX), which are handled by the DDBGMODIN bits. All data OUT transactions go via the Receive buffers (RX), which are handled by the DDBGMODOUT bits. Transactions on Control endpoint 0 (IN, OUT and SETUP) are handled by the CDBGMOD bits. Interrupts caused by events on the USB bus (SOF, Pseudo SOF, suspend, resume, bus reset, Setup and High Speed Status) can also be controlled individually. A bus reset disables all enabled interrupts except bit IEBRST (bus reset), which remains unchanged. The Interrupt Enable Register consists of 4 bytes. The bit allocation is given in Table 12.
Table 12: Interrupt Enable register: bit allocation Bit Symbol Reset Bus Reset Access Bit Symbol Reset Bus Reset Access Bit Symbol Reset Bus Reset Access Bit Symbol Reset Bus Reset Access 31 reserved 0 0 R/W 23 IEP6TX 0 0 R/W 15 IEP2TX 0 0 R/W 7 reserved 0 0 R/W 30 reserved 0 0 R/W 22 IEP6RX 0 0 R/W 14 IEP2RX 0 0 R/W 6 IEDMA 0 0 R/W 29 reserved 0 0 R/W 21 IEP5TX 0 0 R/W 13 IEP1TX 0 0 R/W 5 IEHS_STA 0 0 R/W 28 reserved 0 0 R/W 20 IEP5RX 0 0 R/W 12 IEP1RX 0 0 R/W 4 IERESM 0 0 R/W 27 reserved 0 0 R/W 19 IEP4TX 0 0 R/W 11 IEP0TX 0 0 R/W 3 IESUSP 0 0 R/W 26 reserved 0 0 R/W 18 IEP4RX 0 0 R/W 10 IEP0RX 0 0 R/W 2 IEPSOF 0 0 R/W 25 IEP7TX 0 0 R/W 17 IEP3TX 0 0 R/W 9 reserved 0 0 R/W 1 IESOF 0 0 R/W 24 IEP7RX 0 0 R/W 16 IEP3RX 0 0 R/W 8 IEP0SETUP 0 0 R/W 0 IEBRST 0 unchanged R/W
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Table 13: Interrupt Enable register: bit description Bit 31 to 26 25 to 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol IEP7TX to IEP1RX IEP0TX IEP0RX IEP0SETUP IEDMA IEHS_STA IERESM IESUSP IEPSOF IESOF IEBRST Description reserved; must write logic 0 A logic 1 enables interrupt from the indicated endpoint. A logic 1 enables interrupt from the Control IN endpoint 0. A logic 1 enables interrupt from the Control OUT endpoint 0. reserved A logic 1 enables the interrupt for the Setup data received on endpoint 0. reserved A logic 1 enables interrupt upon DMA status change detection. A logic 1 enables interrupt upon detection of a High Speed Status change. A logic 1 enables interrupt upon detection of a `resume' state. A logic 1 enables interrupt upon detection of a `suspend' state. A logic 1 enables interrupt upon detection of a Pseudo SOF. A logic 1 enables interrupt upon detection of an SOF. A logic 1 enables interrupt upon detection of a bus reset.
9.2.5
DMA Configuration register (address: 38H) See Section 9.4.3.
9.2.6
DMA Hardware register (address: 3CH) See Section 9.4.4.
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9.3 Data flow registers
9.3.1 Endpoint Index register (address: 2CH) The Endpoint Index register selects a target endpoint for register access by the microcontroller. The register consists of 1 byte and the bit allocation is shown in Table 14. The following registers are indexed:
* * * * * *
Endpoint MaxPacketsize Endpoint Type Buffer Length Data Port Short Packet Control Function.
For example, to access the OUT data buffer of endpoint 1 via the Data Port register, the Endpoint Index register has to be written first with 02H.
Table 14: Endpoint Index register: bit allocation Bit Symbol Reset Bus reset Access 7 reserved 0 0 R/W 6 reserved 0 0 R/W 5 EP0SETUP 0 0 R/W 4 3 00H 00H R/W 2 1 0 DIR 0 0 R/W ENDPIDX[3:0]
Table 15: Endpoint Index register: bit description Bit 7 to 6 5 Symbol EP0SETUP Description reserved Selects the SETUP buffer for Endpoint 0: 0 -- EP0 data buffer 1 -- SETUP buffer. Must be logic 0 for access to other endpoints than Endpoint 0. 4 to 1 ENDPIDX[3:0] Endpoint Index: Selects the target endpoint for register access of Buffer Length, Control Function, Data Port, Endpoint Type, MaxPacketSize and Short Packet. DIR Direction bit: Sets the target endpoint as IN or OUT endpoint: 0 -- target endpoint refers to OUT (RX) FIFO 1 -- target endpoint refers to IN (TX) FIFO. Table 16: Addressing of Endpoint 0 buffers Buffer name SETUP Data OUT Data IN EP0SETUP 1 0 0 ENDPIDX 00H 00H 00H DIR 0 0 1
0
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9.3.2
Control Function register (address: 28H) The Control Function register is used to perform the buffer management on the endpoints. It consists of 1 byte and the bit configuration is given in Table 17.The register bits can stall, clear or validate any enabled data endpoint. Before accessing this register, the Endpoint Index register must be written first to specify the target endpoint.
Table 17: Control Function register: bit allocation Bit Symbol Reset Bus reset Access
[1]
7 reserved 0 0 R/W
6 reserved 0 0 R/W
5 reserved 0 0 R/W
4 CLBUF 0 0 R/W
3 VENDP 0 0 R/W
2 reserved 0 0 R/W
1 STATUS [1] 0 0 R/W
0 STALL 0 0 R/W
Only applicable for Endpoint 0.
Table 18: Control Function register: bit description Bit 7 to 5 4 Symbol CLBUF Description reserved. Clear Buffer: A logic 1 clears the RX buffer of the indexed endpoint; the TX buffer is not affected. Before new data can be received, old data in the buffer must be cleared first. Validate Endpoint: A logic 1 validates the data in the TX FIFO of an IN endpoint for sending on the next IN token. The FIFO byte count is below or equal to the Endpoint MaxPacketSize. reserved Status Acknowledge: This bit controls the generation of ACK or NAK during the status stage of a SETUP packet. It is automatically cleared upon completion of the status stage and upon receiving a SETUP token. 0 -- sends NAK 1 -- sends empty packet following IN token (host-to-device) or ACK following OUT token (device-to-host). 0 STALL Stall Endpoint: A logic 1 stalls the indexed endpoint. This bit is not applicable for isochronous transfers.
3
VENDP
2 1
STATUS
9.3.3
Data Port register (address: 20H) This 2-byte register provides direct access for a microcontroller to the FIFO of the indexed endpoint. In case of an 8-bit bus the upper byte is not used. The bit allocation is shown in Table 19. Device to host (IN endpoint): After each write action an internal counter is auto-incremented (by 2 for a 16-bit access, by 1 for an 8-bit access) to the next location in the TX FIFO. When all bytes have been written, the buffer can be validated via the Control Function register (bit VENDP). The data packet will then be sent on the next IN token.
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Host to device (OUT endpoint): After each read action an internal counter is auto-decremented (by 2 for a 16-bit access, by 1 for an 8-bit access) to the next location in the RX FIFO. When all bytes have been read, the buffer contents can be cleared via the Control Function register (bit CLBUF). A new data packet can then be received on the next OUT token. Remark: The buffer can be validated or cleared automatically by using the Buffer Length register (see Table 21).
Table 19: Data Port register: bit allocation Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access 7 6 5 4 00H 00H R/W Table 20: Data Port register: bit description Bit 15 to 8 7 to 0 Symbol DATAPORT[15:8] DATAPORT[7:0] Description data (upper byte); not used in 8-bit bus mode data (lower byte) 15 14 13 12 00H 00H R/W 3 2 1 0 DATAPORT[7:0] 11 10 9 8 DATAPORT[15:8]
9.3.4
Buffer Length register (address: 1CH) This 2-byte register determines the current packet size (DATACOUNT) of the indexed endpoint FIFO. The bit allocation is given in Table 21. The Buffer Length register is automatically loaded with the FIFO size, when the Endpoint MaxPacketSize register is written (see Table 22). A smaller value can be written when required. After a bus reset the Buffer Length register is made zero. IN endpoint: When writing bytes into the TX FIFO, the buffer is automatically validated when DATACOUNT exceeds MaxPacketSize. During the subsequent packet transmission DATACOUNT is decremented with the number of bytes sent. This process is repeated until the number of remaining bytes is less than MaxPacketSize (case I) or zero (case II). In case I, the remaining bytes are automatically validated and a short packet is sent. In case II, a final empty packet will be appended if bit NOEMPKT in the Endpoint Type register is cleared (see Table 24). Otherwise (if bit NOEMPKT is set), data transfer is considered finished when the buffer is empty. OUT endpoint: The DATACOUNT value is automatically initialized to the number of data bytes sent by the host on each ACK. After reading DATACOUNT bytes from the RX buffer, the buffer is automatically cleared to allow the next packet to be received from the host. Remark: For a 16-bit bus, the last byte of an odd-sized packet is output as the lower byte (LSB).
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Table 21: Buffer Length register: bit allocation Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access 7 6 5 4 00H 00H R/W 15 14 13 12 00H 00H R/W 3 2 1 0 DATACOUNT[7:0] 11 10 9 8 DATACOUNT[15:8]
9.3.5
Endpoint MaxPacketSize register (address: 04H) This register determines the maximum packet size for all endpoints except Control 0. The register contains 2 bytes and the bit allocation is given in Table 22. Each time the register is written, the Buffer Length registers of all endpoints are re-initialized to the FFOSZ field value. The NTRANS bits control the number of transactions allowed in a single micro-frame (for high-speed operation only).
Table 22: Endpoint MaxPacketSize register: bit allocation Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access 15 reserved 0 0 R/W 7 14 reserved 0 0 R/W 6 13 reserved 0 0 R/W 5 4 FFOSZ[7:0] 00H 00H R/W Table 23: Endpoint MaxPacketSize register: bit description Bit 15 to 13 12 to 11 Symbol reserved NTRANS[1:0] Description reserved Number of Transactions (HS mode only): 0 -- 1 packet per microframe 1 -- 2 packets per microframe 2 -- 3 packets per microframe 3 -- reserved. 10 to 0 FFOSZ[10:0] FIFO Size: Sets the FIFO size in bytes for the indexed endpoint. Applies to both HS and FS operation. Remark: A FIFO size of zero will disable the endpoint. 12 00H 00H R/W 3 2 11 10 9 FFOSZ[10:8] 00H 00H R/W 1 0 8 NTRANS[1:0]
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9.3.6
Endpoint Type register (address: 08C) This register sets the Endpoint type of the indexed endpoint: control, isochronous, bulk or interrupt. It also serves to enable the endpoint and configure it for double buffering. Automatic generation of an empty packet for a zero length TX buffer can be disabled via bit NOEMPKT. The register contains 2 bytes and the bit allocation is shown in Table 24.
Table 24: Endpoint Type register: bit allocation Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access 7 reserved 0 0 R/W 6 reserved 0 0 R/W 5 reserved 0 0 R/W 4 NOEMPKT 0 0 R/W 15 14 13 12 reserved 00H 00H R/W 3 ENABLE 0 0 R/W 2 DBLBUF 0 0 R/W 1 00H 00H R/W 0 ENDPTYP[1:0] 11 10 9 8
Table 25: Endpoint Type register: bit description Bit 15 to 5 4 Symbol reserved NOEMPKT Description reserved. No Empty Packet: A logic 0 causes an empty packet to be appended to the next IN token of the USB data, if the Buffer Length register or the Endpoint MaxPacketSize register is zero. A logic 1 disables this function. Endpoint Enable: A logic 1 enables the FIFO of the indexed endpoint. The memory size is allocated as specified in the Endpoint MaxPacketSize register. A logic 0 disables the FIFO. Double Buffering: A logic 1 enables double buffering for the indexed endpoint. A logic 0 disables double buffering. Endpoint Type: These bits select the endpoint type as follows: 00H -- control 01H -- isochronous 02H -- bulk 03H -- interrupt.
3
ENABLE
2 1 to 0
DBLBUF ENDPTYP[1:0]
9.3.7
Short Packet register (address: 24H) This read-only register is applicable only for OUT endpoints. It contains 2 bytes and the bit allocation is shown in Table 26. If the number of bytes of a received packet is less than the value specified in the Endpoint MaxPacketSize register (see Table 22), the corresponding short packet status bit (OUTnSH) is set. The Short Packet register is updated on every successfully received new packet.
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Table 26: Short Packet register: bit allocation Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access 15 OUT7SH 0 0 R 7 reserved 0 0 R/W 14 OUT6SH 0 0 R 6 reserved 0 0 R/W 13 OUT5SH 0 0 R 5 reserved 0 0 R/W 12 OUT4SH 0 0 R 4 reserved 0 0 R/W 11 OUT3SH 0 0 R 3 reserved 0 0 R/W 10 OUT2SH 0 0 R 2 reserved 0 0 R/W 9 OUT1SH 0 0 R 1 reserved 0 0 R/W 8 OUT0SH 0 0 R 0 reserved 0 0 R/W
Table 27: Short Packet register: bit description Bit 15 14 13 12 11 10 9 8 7 to 0 Symbol OUT7SH OUT6SH OUT5SH OUT4SH OUT3SH OUT2SH OUT1SH OUT0SH Description A logic 1 indicates that a Short Packet was received on OUT endpoint 7. A logic 0 indicates that the buffer is full. A logic 1 indicates that a Short Packet was received on OUT endpoint 6. A logic 0 indicates that the buffer is full. A logic 1 indicates that a Short Packet was received on OUT endpoint 5. A logic 0 indicates that the buffer is full. A logic 1 indicates that a Short Packet was received on OUT endpoint 4. A logic 0 indicates that the buffer is full. A logic 1 indicates that a Short Packet was received on OUT endpoint 3. A logic 0 indicates that the buffer is full. A logic 1 indicates that a Short Packet was received on OUT endpoint 2. A logic 0 indicates that the buffer is full. A logic 1 indicates that a Short Packet was received on OUT endpoint 1. A logic 0 indicates that the buffer is full. A logic 1 indicates that a Short Packet was received on OUT endpoint 0. A logic 0 indicates that the buffer is full. reserved
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9.4 DMA registers
Two types of Generic DMA transfer and three types of IDE-specified transfer can be done by writing the proper opcode in the DMA Command Register. The control bits are given in Table 28 (Generic DMA transfers) and Table 29 (IDE-specified transfers). GDMA read/write (opcode = 00H/01H) -- Generic DMA Slave mode; the DIOR and DIOW strobe signals are driven by the external DMA Controller. MDMA (Master) read/write (opcode = 06H/07H) -- Generic DMA Master mode; the DIOR and DIOW strobe signals are driven by the ISP1581. PIO read/write (opcode = 04H/05H) -- PIO mode for IDE transfers; the specification of this mode can be obtained from the ATA Specification Rev. 4. DIOR and DIOW are used as data strobes, IORDY can be used by the device to extend the PIO cycle. MDMA read/write (opcode = 06H/07H) -- Multiword DMA mode for IDE transfers; the specification of this mode can be obtained from the ATA Specification Rev. 4. DIOR and DIOW are used as data strobes, while DREQ and DACK serve as handshake signals. UDMA read/write (opcode = 02H/03H) -- Ultra DMA mode for IDE transfers; the specification of this mode can be obtained from the ATA Specification Rev. 4. Pins DA0 to DA2, CS0 and CS1 are used to select a device register for access. Control signals are mapped as follows: DREQ (= DMARQ), DACK (= DMACK), DIOW (= STOP), DIOR (= HDMARDY or HSTROBE), IORDY (= DSTROBE or DDMARDY).
Table 28: Control bits for Generic DMA transfers Control bits Description GDMA read/write (opcode = 00H/01H) DMA Configuration register (see Table 35) BURST[2:0] MODE[1:0] WIDTH0 DIS_XFER_CNT ATA_MODE EOT_POL ACK_POL, DREQ_POL, WRITE_POL, READ_POL MASTER determines the number of DMA cycles during which pin DREQ is kept asserted determines the active data strobe(s) selects the DMA bus width: 8 or 16 bits disables the use of the DMA Transfer Counter set to logic 0 (non-ATA transfer) selects the polarity of the EOT signal select the polarity of the DMA handshake signals set to logic 0 (slave)
DMA Hardware register (see Table 37)
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Table 28: Control bits for Generic DMA transfers...continued Control bits Description MDMA (Master) read/write (opcode = 06H/07H) DMA Configuration register (see Table 35) UDMA_MODE[1:0] MODE[1:0] WIDTH DIS_XFER_CNT ATA_MODE EOT_POL ACK_POL, DREQ_POL, WRITE_POL, READ_POL MASTER determines the MDMA timings for the DIOR and DIOW strobes (value 03H is used for UDMA only) determines the active data strobe(s). selects the DMA bus width: 8 or 16 bits disables the use of the DMA Transfer Counter set to logic 1 (ATA transfer) input EOT is not used select the polarity of the DMA handshake signals set to logic 1 (master)
DMA Hardware register (see Table 37)
Table 29: Control bits for IDE-specified DMA transfers Control bits Description PIO read/write (opcode = 04H/05H) DMA Configuration register (see Table 35) PIO_MODE[2:0] ATA_MODE MASTER selects the PIO mode; timings are ATA(PI) compatible set to logic 1 (ATA transfer) set to logic 0
DMA Hardware register (see Table 37) MDMA read/write (opcode = 06H/07H) DMA Configuration register (see Table 35) MDMA_MODE[1:0] ATA_MODE MASTER selects the MDMA mode; timings are ATA(PI) compatible set to logic 1 (ATA transfer) set to logic 0
DMA Hardware register (see Table 37) UDMA Read/Write (opcode = 02H/03H) DMA Configuration register (see Table 35) UDMA_MODE[1:0] IGNORE_IORDY ATA_MODE MASTER selects the UDMA mode; timings are ATA(PI) compatible used to ignore the IORDY pin during transfer set to logic 1 (ATA transfer) set to logic 0
DMA Hardware register (see Table 37)
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9.4.1
DMA Command register (address: 30H) The DMA Command register is a 1-byte register that initiates all DMA transfer activity on the DMA Controller. The register is write-only: reading it will return FFH.
Table 30: DMA Command register: bit allocation Bit Symbol Reset Bus reset Access 7 6 5 4 FFH FFH W Table 31: DMA Command Register: bit description Bit 7:0 Symbol DMA_CMD[7:0] Description DMA command code, see Table 32. 3 2 1 0 DMA_CMD[7:0]
Table 32: DMA commands Code (Hex) 00 Name GDMA Read Description Generic DMA IN token transfer (slave mode only): Data is transferred from the external DMA bus to the internal buffer. Strobe: DIOW by external DMA Controller. Generic DMA OUT token transfer (slave mode only): Data is transferred from the internal buffer to the external DMA bus. Strobe: DIOR by external DMA Controller. UDMA Read command: Data is transferred from the external DMA to the internal DMA bus. UDMA Write command: Data is transferred in UDMA mode from the internal buffer to the external DMA bus. PIO Read command for ATAPI device: Data is transferred in PIO mode from the external DMA bus to the internal buffer. Data transfer starts when IORDY is asserted. Inputs DREQ and DACK are ignored. PIO Write command for ATAPI device: Data is transferred in PIO mode from the internal buffer to the external DMA bus. Data transfer starts when IORDY is asserted. Inputs DREQ and DACK are ignored. Multiword DMA Read: Data is transferred from the external DMA bus to the internal buffer. Multiword DMA Write: Data is transferred from the internal buffer to the external DMA bus. Read at address 01F0H: Initiates a PIO Read cycle from Task File 1F0. Before issuing this command the task file byte count should be programmed at address 1F4H (LSB) and 1F5H (MSB). Poll BSY status bit for ATAPI device: Starts repeated PIO Read commands to poll the BSY status bit of the ATAPI device. When BSY = 0, polling is terminated and an interrupt is generated.
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01
GDMA Write
02 03 04
UDMA Read UDMA Write PIO Read
05
PIO Write
06 07 0A
MDMA Read MDMA Write Read 1F0
0B
Poll BSY
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Table 32: DMA commands...continued Code (Hex) 0C Name Read Task Files Description Read Task Files: Reads all task file registers except 1F0H and 1F7H. When reading has been completed, an interrupt is generated. reserved Validate Buffer (for debugging only): Request from the microcontroller to validate the endpoint buffer following an ATA to USB data transfer. Clear Buffer: Request from the microcontroller to clear the endpoint buffer after a USB to ATA data transfer. Restart: Request from the microcontroller to move the buffer pointers to the beginning of the endpoint FIFO. Reset DMA: Initializes the DMA core to its power-on reset state. reserved
0D 0E
Validate Buffer
0F 10 11 12 to FF
Clear Buffer Restart Reset DMA -
9.4.2
DMA Transfer Counter register (address: 34H) This 4-byte register is used to set up the total byte count of a DMA transfer (DMACR). It indicates the remaining number of bytes left for transfer. The bit allocation is given in Table 33. The transfer counter is used in DMA modes: PIO (commands: 04H, 05H), UDMA (commands: 02H, 03H), MDMA (commands: 06H, 07H) and GDMA (commands: 00H, 01H). A new value is written into the register starting with the lower byte (DMACR1) or the lower word (MSB: DMACR2, LSB: DMACR1). Internally, the transfer counter is initialized only after the last byte (DMACR4) has been written. In the GDMA Slave mode only, the transfer counter can be disabled via bit DIS_XFER_CNT in the DMA Configuration Register (see Table 35). In this case, input EOT can be used to terminate the DMA transfer when data is transferred from the external device to the host via IN tokens. The last packet in the FIFO is validated when pin EOT is asserted. When the host sends data to an external device via OUT tokens, the EOT condition is ignored.
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Table 33: DMA Transfer Counter register: bit allocation Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access 7 6 5 4 00H 00H R/W Table 34: DMA Transfer Counter register: bit description Bit 31 to 24 23 to 16 15 to 8 7 to 0 Symbol DMACR4, DMACR[31:24] DMACR3, DMACR[23:16] DMACR2, DMACR[15:8] DMACR1, DMACR[7:0] Description DMA transfer counter byte 4 (MSB) DMA transfer counter byte 3 DMA transfer counter byte 2 DMA transfer counter byte 1 (LSB) 15 14 13 12 00H 00H R/W 3 2 1 0 DMACR1 = DMACR[7:0] 23 22 21 20 00H 00H R/W 11 10 9 8 DMACR2 = DMACR[15:8] 31 30 29 28 00H 00H R/W 19 18 17 16 DMACR3 = DMACR[23:16] 27 26 25 24 DMACR4 = DMACR[31:24]
9.4.3
DMA Configuration register (address: 38H) This register defines the DMA configuration for the Generic DMA (GDMA) and the Ultra-DMA (UDMA) modes. The DMA Configuration register consists of 2 bytes. The bit allocation is given in Table 35.
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Table 35: DMA Configuration register: bit allocation Bit Symbol Reset Bus Reset Access Bit Symbol 15 reserved 0 0 R/W 7 DIS_ XFER_ CNT 0 0 R/W 14 IGNORE_ IORDY 0 0 R/W 6 13 ATA_ MODE 0 0 R/W 5 BURST[2:0] 4 12 11 10 9 PIO_MODE[2:0] 00H 00H R/W 3 MODE[1:0] 2 1 reserved 0 WIDTH 8 DMA_MODE[1:0] 00H 00H R/W
Reset Bus Reset Access
00H 00H R/W
00H 00H R/W
0 0 R/W
1 1 R/W
Table 36: DMA Configuration register: bit description Bit 15 14 13 Symbol IGNORE_IORDY ATA_MODE Description reserved A logic 1 ignores the IORDY input signal (UDMA mode only). A logic 1 configures the DMA core for ATA or MDMA mode. Used when issuing DMA commands 02H to 07H, 0AH and 0CH; also used when directly accessing task file registers. A logic 0 configures the DMA core for non-ATA mode. Used when issuing DMA commands 00H and 01H. 12 to 11 UDMA_MODE[1:0] These bits affect the timing for UDMA and MDMA mode: 00H -- UDMA/MDMA mode 0: ATA(PI) compatible timings 01H -- UDMA/MDMA mode 1: ATA(PI) compatible timings 02H -- UDMA/MDMA mode 2: ATA(PI) compatible timings 03H -- UDMA mode 3: enables the DMA Strobe Timing register (see Table 39) for non-standard strobe durations; only used in UDMA mode. 10 to 8 PIO_MODE[2:0] These bits affect the PIO timing (see Table 84): 00H to 04H -- PIO mode 0 to 4: ATA(PI) compatible timings 05H to 07H -- reserved. 7 DIS_XFER_CNT A logic 1 disables the DMA Transfer Counter (see Table 33). The transfer counter can only be disabled in GDMA slave mode; in master mode the counter is always enabled.
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ISP1581
USB 2.0 HS interface device
Table 36: DMA Configuration register: bit description...continued Bit 6 to 4 Symbol BURST[2:0] Description These bits select the DMA burst length and the DREQ timing (GDMA Slave mode only): 00H -- DREQ is asserted until the last byte/word is transferred or until the FIFO becomes full or empty 01H -- DREQ is asserted and negated for each byte/word transferred [1] [2] 02H -- DREQ is asserted and negated for every 2 bytes/words transferred [1] [2] 03H -- DREQ is asserted and negated for every 4 bytes/words transferred [1] [2] 04H -- DREQ is asserted and negated for every 8 bytes/words transferred [1] [2] 05H -- DREQ is asserted and negated for every 12 bytes/words transferred [1] [2] 06H -- DREQ is asserted and negated for every 16 bytes/words transferred [1] [2] 07H -- DREQ is asserted and negated for every 32 bytes/words transferred [1] [2]. 3 to 2 MODE[1:0] These bits only affect the GDMA (slave) and MDMA (master) handshake signals: 00H -- DIOR (master) or DIOW (slave): strobes data from the DMA bus into the ISP1581; DIOW (master) or DIOR (slave): puts data from the ISP1581 on the DMA bus 01H -- DIOR (master) or DACK (slave) strobes the data from the DMA bus into the ISP1581; DACK (master) or DIOR (slave) puts the data from the ISP1581 on the DMA bus 02H -- DACK (master and slave) strobes the data from the DMA bus into the ISP1581 and also puts the data from the ISP1581 on the DMA bus 03H -- reserved. 1 0 WIDTH reserved This bit selects the DMA bus width for GDMA (slave) and MDMA (master): 0 -- 8-bit data bus 1 -- 16-bit data bus.
[1] [2] DREQ is asserted only if space (writing) or data (reading) is available in the FIFO. This process is stopped when the transfer FIFO becomes empty.
9.4.4
DMA Hardware register (address: 3CH) The DMA Hardware register consists of 1 byte. The bit allocation is shown in Table 37. This register determines the polarity of the bus control signals (EOT, DACK, DREQ, DIOR, DIOW) and the DMA mode (master or slave). It also controls whether the upper and lower parts of the data bus are swapped (bits ENDIAN[1:0]), for modes GDMA (slave) and MDMA (master) only.
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Table 37: DMA Hardware register: bit allocation (modes GDMA, MDMA (Master) and MDMA (ATA) only) Bit 7 6 5 4 3 2 1 Symbol Reset Bus reset Access ENDIAN[1:0] 00H 00H R/W EOT_ POL 0 0 R/W MASTER 0 0 R/W ACK_ POL 0 0 R/W DREQ_ POL 1 1 R/W WRITE_ POL 0 0 R/W
0 READ_ POL 0 0 R/W
Table 38: DMA Hardware register: bit description Bit 7 to 6 Symbol ENDIAN[1:0] Description These bits determine whether the data bus is swapped between internal RAM and the DMA bus: nibbles [1] (8-bit bus) or bytes (16-bit bus). This only applies for modes GDMA (slave) and MDMA (master). 00H -- normal data representation 8-bit bus: MSN on DATA[7:4], LSN on DATA[3:0]; 16-bit bus: MSB on DATA[15:8], LSB on DATA[7:0] 01H -- swapped data representation 8-bit bus: MSN on DATA[3:0], LSN on DATA[7:4]; 16-bit bus: MSB on DATA[7:0], LSB on DATA[15:8] 02H, 03H -- reserved. 5 EOT_POL Selects the polarity of the End Of Transfer input (used in GDMA slave mode only): 0 -- EOT is active LOW 1 -- EOT is active HIGH. 4 MASTER Selects the DMA master/slave mode: 0 -- GDMA slave mode. 1 -- MDMA master mode. 3 ACK_POL Selects the DMA acknowledgement polarity: 0 -- DACK is active LOW 1 -- DACK is active HIGH. 2 DREQ_POL Selects the DMA request polarity: 0 -- DREQ is active LOW 1 -- DREQ is active HIGH. 1 WRITE_POL Selects the DIOW strobe polarity. 0 -- DIOW is active LOW 1 -- DIOW is active HIGH. 0 READ_POL Selects the DIOR strobe polarity. 0 -- DIOR is active LOW 1 -- DIOR is active HIGH.
[1] Nibble = 4 bits. MSN: Most Significant Nibble, LSN: Least Significant Nibble.
9.4.5
DMA Strobe Timing register (address: 60H) This 1-byte register controls the strobe timings for UDMA and MDMA mode, when the UDMA_MODE bits in the DMA Configuration register have been set to 03H. The bit allocation is given in Table 39.
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Table 39: DMA Strobe Timing register: bit allocation Bit Symbol Reset Bus reset Access 7 reserved 0 0 R/W 6 reserved 0 0 R/W 5 reserved 0 0 R/W 4 3 2 DMA_STROBE_CNT[4:0] 1FH 1FH R/W 1 0
Table 40: DMA Strobe Timing register: bit description Bit 7 to 5 4 to 0 Symbol DMA_ STROBE_ CNT[4:0] Description reserved. These bits select the strobe duration for UDMA_MODE = 03H (see Table 35). The strobe duration is (N+1) cycles [1], with N representing the value of DMA_.STROBE_CNT.
[1]
The cycle duration for UDMA mode 3 is the same as for UDMA mode 2 (see Table 87).
9.4.6
Task File registers (addresses: 40H to 4FH) These registers allow direct access to the internal registers of an ATAPI peripheral using PIO mode. The supported Task File registers and their functions are shown in Table 41. The correct peripheral register is automatically addressed via pins CS1, CS0, DA2, DA1 and DA0 (see Table 42).
Table 41: Task File register functions Address (Hex) 1F0 1F1 1F2 1F3 1F4 1F5 1F6 1F7 3F6 3F7 ATA function data (16-bits) error/feature sector count sector number/LBA[7:0] cylinder low/LBA[15:8] cylinder high/LBA[23:16] drive/head/LBA[27:24] command alternate status/command drive address ATAPI function data (16-bits) error/feature interrupt reason reserved cylinder low cylinder high drive select status/command alternate status/command reserved
Table 42: ATAPI peripheral register addressing Task file 1F0 1F1 1F2 1F3 1F4 1F5 1F6 CS1 H H H H H H H CS0 L L L L L L L DA2 L L L L H H H DA1 L L H H L L H DA0 L H L H L H L
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Table 42: ATAPI peripheral register addressing...continued Task file 1F7 3F6 3F7 CS1 H L L CS0 L H H DA2 H H H DA1 H H H DA0 H L H
In 8-bit bus mode, the 16-bit Task File register 1F0 requires 2 consecutive write/read accesses before the proper PIO write/read is generated on the IDE interface. The first byte is always the lower byte (LSB). Other task file registers can be accessed directly. Writing to Task File registers can be done in any order except for Task File register 1F7, which must be written last.
Table 43: Task File register 1F0 (address: 40H): bit allocation CS1 = H, CS0 = L, DA2 = L, DA1 = L, DA0 = L. Bit Symbol Reset Bus reset Access Table 44: Task File register 1F1 (address: 48H): bit allocation CS1 = H, CS0 = L, DA2 = L, DA1 = L, DA0 = H. Bit Symbol Reset Bus reset Access Table 45: Task File register 1F2 (address: 49H): bit allocation CS1 = H, CS0 = L, DA2 = L, DA1 = H, DA0 = L. Bit Symbol Reset Bus reset Access Table 46: Task File register 1F3 (address: 4AH): bit allocation CS1 = H, CS0 = L, DA2 = L, DA1 = H, DA0 = H. Bit Symbol Reset Bus reset Access 7 6 5 4 00H 00H R/W 3 2 1 0 sector number/LBA[7:0] (ATA), reserved (ATAPI) 7 6 5 4 00H 00H R/W 3 2 1 0 sector count (ATA) or interrupt reason (ATAPI) 7 6 5 4 00H 00H R/W 3 2 1 0 error/feature (ATA or ATAPI) 7 6 5 4 00H 00H R/W 3 2 1 0 data (ATA or ATAPI)
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Table 47: Task File register 1F4 (address: 4BH): bit allocation CS1 = H, CS0 = L, DA2 = H, DA1 = L, DA0 = L. Bit Symbol Reset Bus reset Access Table 48: Task File register 1F5 (address: 4CH): bit allocation CS1 = H, CS0 = L, DA2 = H, DA1 = L, DA0 = H. Bit Symbol Reset Bus reset Access Table 49: Task File register 1F6 (address: 4DH): bit allocation CS1 = H, CS0 = L, DA2 = H, DA1 = H, DA0 = L. Bit Symbol Reset Bus reset Access Table 50: Task File register 1F7 (address: 44H): bit allocation CS1 = H, CS0 = L, DA2 = H, DA1 = H, DA0 = H. Bit Symbol Reset Bus reset Access
[1] Task File register 1F7 is a write-only register; a read will return 00H.
7
6
5
4 00H 00H R/W
3
2
1
0
cylinder low/LBA[15:8] (ATA) or cylinder low (ATAPI)
7
6
5
4 00H 00H R/W
3
2
1
0
cylinder high/LBA[23:16] (ATA) or cylinder high (ATAPI)
7
6
5
4 00H 00H R/W
3
2
1
0
drive/head/LBA[27:24] (ATA) or drive (ATAPI)
7
6
5
4 00H 00H W
3 status [1]/command
2 (ATAPI)
1
0
command (ATA) or
Table 51: Task File register 3F6 (address: 4EH): bit allocation CS1 = L, CS0 = H, DA2 = H, DA1 = H, DA0 = L. Bit Symbol Reset Bus reset Access 7 6 5 4 00H 00H R/W 3 2 1 0 alternate status/command (ATA or ATAPI)
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Table 52: Task File register 3F7 (address: 4FH): bit allocation CS1 = L, CS0 = H, DA2 = H, DA1 = H, DA0 = H. Bit Symbol Reset Bus reset Access 7 6 5 4 00H 00H R/W 3 2 1 0 drive address (ATA) or reserved (ATAPI)
9.4.7
DMA Interrupt Reason register (address: 50H) This 2-byte register shows the source(s) of a DMA interrupt. Each bit is refreshed after a DMA command has been executed. An interrupt source is cleared by writing a logic 1 to the corresponding bit. The bit allocation is given in Table 53.
Table 53: DMA Interrupt Reason register: bit allocation Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access 15 reserved 0 0 R/W 7 1F0_WF_E 0 0 R/W 14 reserved 0 0 R/W 6 1F0_WF_F 0 0 R/W 13 reserved 0 0 R/W 5 1F0_RF_E 0 0 R/W 12 reserved 0 0 R/W 4 READ_1F0 0 0 R/W 11 reserved 0 0 R/W 3 BSY_ DONE 0 0 R/W 10 reserved 0 0 R/W 2 TF_RD_ DONE 0 0 R/W 9 INTRQ_ PENDING 0 0 R/W 1 CMD_ INTRQ_OK 0 0 R/W 8 DMA_ XFER_OK 0 0 R/W 0 reserved 0 0 R/W
Table 54: DMA Interrupt Reason Register: bit description Bit 9 8 Symbol INTRQ_PENDING DMA_XFER_OK Description reserved A logic 1 indicates that a pending interrupt was detected on pin INTRQ. A logic 1 indicates that the DMA transfer has been completed (DMA Transfer Counter has become zero). This bit is only used in GDMA (slave) mode and MDMA (master) mode. A logic 1 indicates that the 1F0 write FIFO is empty and the microcontroller can start writing data. A logic 1 indicates that the 1F0 write FIFO is full and the microcontroller must stop writing data. A logic 1 indicates that 1F0 read FIFO is empty and the microcontroller must stop reading data. A logic 1 indicates that 1F0 FIFO contains unread data and the microcontroller can start reading data. A logic 1 indicates that the BSY status bit has become zero and polling has been stopped. 15 to 10 -
7 6 5 4 3
1F0_WF_E 1F0_WF_F 1F0_RF_E READ_1F0 BSY_DONE
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Table 54: DMA Interrupt Reason Register: bit description...continued Bit 2 1 Symbol TF_RD_DONE CMD_INTRQ_OK Description A logic 1 indicates that the Read Task Files command has been completed. A logic 1 indicates that all bytes from the FIFO have been transferred (DMA Transfer Count zero) and an interrupt on pin INTRQ was detected. reserved
0
-
9.4.8
DMA Interrupt Enable register (address: 54H) This 2-byte register controls the interrupt generation of the source bits in the DMA Interrupt Reason register (see Table 53). The bit allocation is given in Table 55. A logic 1 enables interrupt generation. The value after a (bus) reset is logic 0 (disabled).
Table 55: DMA Interrupt Enable register: bit allocation Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access 15 reserved 0 0 R/W 7 IE_1F0_ WF_E 0 0 R/W 14 reserved 0 0 R/W 6 IE_1F0_ WF_F 0 0 R/W 13 reserved 0 0 R/W 5 IE_1F0_ RF_E 0 0 R/W 12 reserved 0 0 R/W 4 IE_ READ_1F0 0 0 R/W 11 reserved 0 0 R/W 3 IE_BSY_ DONE 0 0 R/W 10 reserved 0 0 R/W 2 IE_TF_ RD_DONE 0 0 R/W 9 IE_INTRQ_ PENDING 0 0 R/W 1 IE_CMD_ INTRQ_OK 0 0 R/W 8 IE_DMA_ XFER_OK 0 0 R/W 0 reserved 0 0 R/W
9.4.9
DMA Endpoint register (address: 58H) This 1-byte register selects a USB endpoint FIFO as a source or destination for DMA transfers. The bit allocation is given in Table 56.
Table 56: DMA Endpoint register: bit allocation Bit Symbol Power Reset Bus Reset Access 7 reserved 0 0 R/W 6 reserved 0 0 R/W 5 reserved 0 0 R/W 4 reserved 0 0 R/W 0 0 R/W 3 2 EPIDX[2:0] 0 0 R/W 0 0 R/W 1 0 DMADIR 0 0 R/W
Table 57: DMA Endpoint register: bit description Bit 7 to 4 3 to 1 0 Symbol EPIDX[2:0] DMADIR Description reserved selects the indicated endpoint for DMA access 0 -- selects the RX/OUT FIFO for DMA read transfers 1 -- selects the TX/IN FIFO for DMA write transfers.
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9.5 General registers
9.5.1 Interrupt register (address: 18H) The Interrupt register consists of 4 bytes. The bit allocation is given in Table 58. When a bit is set in the Interrupt register, this indicates that the hardware condition for an interrupt has occurred. When the Interrupt register content is non-zero, the INT output will be asserted. Upon detecting the interrupt, the external microprocessor must read the Interrupt register to determine the source of the interrupt. Each endpoint buffer has a dedicated interrupt bit (EPnTX, EPnRX). In addition, various bus states can generate an interrupt: Resume, Suspend, Pseudo-SOF, SOF and Bus Reset. The DMA Controller only has one interrupt bit: the source for a DMA interrupt is shown in the DMA Interrupt Reason register (see Table 53). Each interrupt bit (except bit DMA) can be individually cleared by writing a logic 1. The DMA interrupt bit can be cleared by writing a logic 1 to the related interrupt source bit in the DMA Interrupt Reason register.
Table 58: Interrupt register: bit allocation Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access 31 reserved 0 0 R/W 23 EP6TX 0 0 R/W 15 EP2TX 0 0 R/W 7 reserved 0 0 R/W 30 reserved 0 0 R/W 22 EP6RX 0 0 R/W 14 EP2RX 0 0 R/W 6 DMA 0 0 R/W 29 reserved 0 0 R/W 21 EP5TX 0 0 R/W 13 EP1TX 0 0 R/W 5 HS_STAT 0 0 R/W 28 reserved 0 0 R/W 20 EP5RX 0 0 R/W 12 EP1RX 0 0 R/W 4 RESUME 0 0 R/W 27 reserved 0 0 R/W 19 EP4TX 0 0 R/W 11 EP0TX 0 0 R/W 3 SUSP 0 0 R/W 26 reserved 0 0 R/W 18 EP4RX 0 0 R/W 10 EP0RX 0 0 R/W 2 PSOF 0 0 R/W 25 EP7TX 0 0 R/W 17 EP3TX 0 0 R/W 9 reserved 0 0 R/W 1 SOF 0 0 R/W 24 EP7RX 0 0 R/W 16 EP3RX 0 0 R/W 8 EP0SETUP 0 0 R/W 0 BRESET 0 unchanged R/W
Table 59: Interrupt register: bit description Bit 31 to 26 25 24 23
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Symbol reserved EP7TX EP7RX EP6TX
Description reserved; must write logic 0 A logic 1 indicates the Endpoint 7 TX buffer as interrupt source. A logic 1 indicates the Endpoint 7 RX buffer as interrupt source. A logic 1 indicates the Endpoint 6 TX buffer as interrupt source.
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Table 59: Interrupt register: bit description...continued Bit 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 Symbol EP6RX EP5TX EP5RX EP4TX EP4RX EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX EP0RX reserved EP0SETUP reserved DMA HS_STAT Description A logic 1 indicates the Endpoint 6 RX buffer as interrupt source. A logic 1 indicates the Endpoint 5 TX buffer as interrupt source. A logic 1 indicates the Endpoint 5 RX buffer as interrupt source. A logic 1 indicates the Endpoint 4 TX buffer as interrupt source. A logic 1 indicates the Endpoint 4 RX buffer as interrupt source. A logic 1 indicates the Endpoint 3 TX buffer as interrupt source. A logic 1 indicates the Endpoint 3 RX buffer as interrupt source. A logic 1 indicates the Endpoint 2 TX buffer as interrupt source. A logic 1 indicates the Endpoint 2 RX buffer as interrupt source. A logic 1 indicates the Endpoint 1 TX buffer as interrupt source. A logic 1 indicates the Endpoint 1 RX buffer as interrupt source. A logic 1 indicates the Endpoint 0 data TX buffer as interrupt source. A logic 1 indicates the Endpoint 0 data RX buffer as interrupt source. reserved. A logic 1 indicates that a SETUP token was received on Endpoint 0. reserved. DMA status: A logic 1 indicates a change in the DMA Status register. High Speed Status:.A logic 1 indicates a change from FS to HS mode (HS connection). This bit is not set, when the system goes into a FS suspend. Resume status: A logic 1 indicates that a status change from `suspend' to `resume' (active) was detected. Suspend status: A logic 1 indicates that a status change from active to `suspend' was detected on the bus. Pseudo SOF interrupt: A logic 1 indicates that a Pseudo SOF or SOF was received. Pseudo SOF is an internally generated clock signal (FS: 1 ms period, HS: 125 s period) synchronized to the USB bus SOF/SOF. SOF interrupt: A logic 1 indicates that a SOF/SOF was received. Bus Reset: A logic 1 indicates that a USB bus reset was detected.
4 3 2
RESUME SUSP PSOF
1 0
SOF BRESET
9.5.2
Chip ID register (address: 70H) This read-only register contains the chip identification and the hardware version numbers. The firmware should check this information to determine the functions and features supported. The register contains 3 bytes and the bit allocation is shown in Table 60.
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Table 60: Chip ID register: bit allocation Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access 7 6 5 4 CHIPID[7:0] 81H 81H R Table 61: Chip ID Register: bit description Bit 23 to 16 Symbol VERSION Description Version number (01H). The version number will be incremented in case of a silicon revision with improved performance and functionality. Chip ID: upper byte (15H) Chip ID: lower byte (81H) 15 14 13 12 15H 15H R 3 2 1 0 23 22 21 20 01H 01H R 11 10 9 8 CHIPID[15:8] 19 18 17 16 VERSION[7:0]
15 to 8 7 to 0
CHIPID[15:8] CHIPID[7:0]
9.5.3
Frame Number register (address: 74H) This read-only register contains the frame number of the last successfully received Start Of Frame (SOF). The register contains 2 bytes and the bit allocation is given in Table 62. In case of 8-bit access the register content is returned lower byte first.
Table 62: Frame Number register: bit allocation Bit Symbol Power Reset Bus Reset Access Bit Symbol Power Reset Bus Reset Access 15 reserved 0 0 R 7 14 reserved 0 0 R 6 5 13 12 MICROSOF[2:0] 00H 00H R 4 SOFR[7:0] 00H 00H R 3 2 11 10 9 SOFR[10:8] 00H 00H R 1 0 8
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Table 63: Frame Number register: bit description Bit 13 to 11 10 to 0 Symbol MICROSOF[2:0] SOFR[10:0] Description microframe number frame number
9.5.4
Scratch register (address: 78H) This 16-bit register can be used by the firmware to save and restore information, e.g. the device status before it enters power-off mode during `suspend'. The content of this register will not be altered by a bus reset. The bit allocation is given in Table 64.
Table 64: Scratch Register: bit allocation Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access 7 6 5 4 SFIRL[7:0] 00H unchanged R/W Table 65: Scratch Information register: bit description Bit 15 to 8 7 to 0 Symbol SFIRH[7:0] SFIRL[7:0] Description scratch firmware information register (high byte) scratch firmware information register (low byte) 15 14 13 12 SFIRH[7:0] 00H unchanged R/W 3 2 1 0 11 10 9 8
9.5.5
Unlock Device register (address: 7CH) In `suspend' state all the internal registers are write-protected to prevent data corruption by external devices during a `resume'. Register access for reading is not blocked. To re-enable the ISP1581 registers from the write-protected mode, the firmware must write a 2-byte unlock code (AA37H) into this register. The bit allocation of the Unlock Device register is given in Table 66.
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Table 66: Unlock Device register: bit allocation Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access 7 6 5 4 15 14 13 12 11 10 9 8 ULCODE[15:8] = AAH not applicable not applicable W 3 2 1 0 ULCODE[7:0] = 37H not applicable not applicable W Table 67: Unlock Device register: bit description Bit 15 to 0 Symbol ULCODE[15:0] Description Writing data AA37H unlocks the internal registers and FIFOs for writing, following a `resume'.
9.5.6
Test Mode register (address: 84H) This 1-byte register allows the firmware to set the (D+, D-) lines to predetermined states for testing purposes. The bit allocation is given in Table 68. Remark: Only one bit can be set at a time.
Table 68: Test Mode register: bit allocation Bit Symbol Reset Bus reset Access 7 FORCEHS 0 0 R/W 6 PHYTEST 0 0 R/W 5 LPBK 0 0 R/W 4 FORCEFS 0 0 R/W 3 PRBS 0 0 R/W 2 KSTATE 0 0 R/W 1 JSTATE 0 0 R/W 0 SE0_NAK 0 0 R/W
Table 69: Test Mode Register: bit description Bit 7 6 5 4 3 2 1 0 Symbol FORCEHS PHYTEST LPBK FORCEFS PRBS KSTATE JSTATE SE0_NAK Description A logic 1 forces the hardware to high-speed mode only and disables the chirp detection logic. A logic 1 initiates an internal hardware test of the transceiver. After successful completion the PHYTEST bit reverts to logic 0. A logic 1 selects loop-back mode. All data written to TX/IN FIFO of endpoint 1 is copied into RX/OUT of endpoint 1. A logic 1 forces the physical layer to full-speed mode only and disables the chirp detection logic. A logic 1 sets the (D+, D-) lines to toggle in a pre-determined random pattern. Writing a logic 1 sets the (D+, D-) lines to the K state. Writing a logic 1 sets the (D+, D-) lines to the J state. Writing a logic 1 sets the (D+, D-) lines to a HS quiescent state. The device only responds to a valid HS IN token with a NAK.
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10. Limiting values
Table 70: Absolute maximum ratings In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC VI Ilatchup Vesd Tstg Ptot Parameter supply voltage input voltage latchup current electrostatic discharge voltage storage temperature total power dissipation VI < 0 or VI > VCC ILI < 15 A Conditions Min. -0.5 -0.5 -60 Max +6.0 VCC + 0.5 200 +150 Unit V V mA V C mW
Table 71: Recommended operating conditions Symbol VCC VI VI(AI/O) VO(od) Tamb Parameter supply voltage input voltage range input voltage on analog I/O pins (D+, D-) open-drain output pull-up voltage operating ambient temperature Conditions with voltage converter without voltage converter Min. 4.0 3.0 0 0 0 -40 Max 5.5 3.6 5.5 3.6 VCC +85 Unit V V V V V C
11. Static characteristics
Table 72: Static characteristics; supply pins VCC = 4.0 to 5.5 V; VGND = 0 V; Tamb = -40 to +85 C; unless otherwise specified. Symbol Vreg(3.3) ICC ICC(susp) Parameter regulated supply voltage operating supply current suspend supply current 1.5 k pull-up on pin D+ no pull-up on pin D+
[1] In `suspend' mode the minimum voltage is 3.0 V.
Conditions with voltage converter
Min. 3.0 [1] -
Typ 3.3 -
Max 3.6
Unit V mA A A
Table 73: Static characteristics: digital pins VCC = 4.0 to 5.5 V; VGND = 0 V; Tamb = -40 to +85 C; unless otherwise specified. Symbol Input levels VIL VIH LOW-level input voltage HIGH-level input voltage 2.0 0.8 V V Parameter Conditions Min. Typ Max Unit
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Table 73: Static characteristics: digital pins...continued VCC = 4.0 to 5.5 V; VGND = 0 V; Tamb = -40 to +85 C; unless otherwise specified. Symbol Vth(LH) Vth(HL) Vhys Output levels VOL VOH LOW-level output voltage (open drain outputs) HIGH-level output voltage (open drain outputs) IOL = rated drive IOL = 20 A IOH = rated drive IOH = 20 A 2.4 VCC-0.1 0.4 0.1 5 5 V V V V A A Parameter positive-going threshold voltage negative-going threshold voltage hysteresis voltage Conditions Min. 1.4 0.9 0.4 Typ Max 1.9 1.5 0.7 Unit V V V Schmitt trigger inputs
Leakage current ILI IOZ input leakage current OFF-state output current Open-drain outputs
Table 74: Static characteristics: analog I/O pins (D+, D-) [1] VCC = 4.0 to 5.5 V; VGND = 0 V; Tamb = -40 to +85 C; unless otherwise specified. Symbol Input levels VDI VCM VSE VIL VIH Output levels VOL VOH ILZ Capacitance CIN Resistance RPU ZDRV ZINP
[1] [2]
[2]
Parameter differential input sensitivity differential common mode voltage single ended receiver threshold LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level output voltage OFF-state leakage current transceiver capacitance pull-up resistance on D+ driver output impedance input impedance
Conditions |VI(D+) - VI(D-)| includes VDI range
Min. 0.2 0.8 0.8 2.0
Typ -
Max 2.5 2.0
Unit V V V V V V V A pF k M
-
0.8 0.3 3.6 10 20 1.9 44 -
RL = 1.5 k to +3.6V RL = 15 k to GND 0 < VI < 3.3 V pin to GND SoftConnect = ON steady-state drive
2.8 1.1 29 10
Leakage current
D+ is the USB positive data pin; D- is the USB negative data pin. Includes external resistors of 22 1% on both D+ and D-.
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12. Dynamic characteristics
Table 75: Dynamic characteristics VCC = 4.0 to 5.5 V; VGND = 0 V; Tamb = -40 to +85 C; unless otherwise specified. Symbol Reset tW(RESET) pulse width on input RESET crystal oscillator running crystal oscillator stopped Crystal oscillator fXTAL
[1]
Parameter
Conditions
Min. -
Typ [1] 12
Max -
Unit s ms MHz
crystal frequency
Dependent on the crystal oscillator start-up time.
Table 76: Dynamic characteristics: analog I/O pins (D+, D-) [1] VCC = 4.0 to 5.5 V; VGND = 0 V; Tamb = -40 to +85 C; CL = 50 pF; RPU = 1.5 k on D+ to VTERM.; unless otherwise specified. Symbol Parameter Conditions Min. Typ Max Unit Driver characteristics Full-speed mode tFR tFF FRFM VCRS tHSR tHSF rise time fall time differential rise/fall time matching (tFR/tFF) output signal crossover voltage high-speed differential rise time high-speed differential fall time with captive cable with captive cable CL = 50 pF; 10 to 90% of |VOH - VOL| CL = 50 pF; 90 to 10% of |VOH - VOL|
[2]
4 4 90 1.3 500 500
-
20 20 111.11 2.0 -
ns ns % V ps ps
[2] [3]
High-speed mode
Data source timing High-speed mode (Template 1, Universal Serial Bus Specification Rev. 2.0) driver waveform requirements eye patterns of Template 1 and Template 2; see Figure 7 and Figure 8 see Figure 3
[3]
see Table 77
Full-speed mode tFEOPT tFDEOP source EOP width
[3] [3]
160 -2
-
175 +5
ns ns
source differential data-to-EOP see Figure 3 transition skew
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Table 76: Dynamic characteristics: analog I/O pins (D+, D-) [1]...continued VCC = 4.0 to 5.5 V; VGND = 0 V; Tamb = -40 to +85 C; CL = 50 pF; RPU = 1.5 k on D+ to VTERM.; unless otherwise specified. Symbol Parameter Conditions Min. Typ Max Unit Receiver timing High-speed mode (Template 4, Universal Serial Bus Specification Rev. 2.0) data source jitter and receiver jitter tolerance eye patterns of Template 3 and Template 4; see Figure 9 and Figure 10 see Figure 4
[3]
see Table 80
Full-speed mode tJR1 tJR2 tFEOPR tFST receiver data jitter tolerance to next transition
[3]
-18.5 -9 82 -
-
+18.5 +9 14
ns ns ns ns
receiver data jitter tolerance for see Figure 4 paired transitions receiver SE0 width accepted as EOP; see Figure 3
[3]
[3]
width of SE0 during differential rejected as EOP; transition see Figure 5
Test circuit: see Figure 31. Excluding the first transition from Idle state. Characterized only, not tested. Limits guaranteed by design.
[3]
[1] [2] [3]
TPERIOD +3.3 V crossover point differential data lines crossover point extended
0V differential data to SE0/EOP skew N x TPERIOD + t DEOP source EOP width: t EOPT receiver EOP width: t EOPR
MGR776
TPERIOD is the bit duration corresponding with the USB data rate. Full-speed timing symbols have a subscript prefix `F', low-speed timings a prefix `L'.
Fig 3. Source differential data-to-EOP transition skew and EOP width.
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TPERIOD +3.3 V differential data lines
0V tJR consecutive transitions N x TPERIOD + t JR1 paired transitions N x TPERIOD + t JR2 tJR1 tJR2
MGR871
TPERIOD is the bit duration corresponding with the USB data rate.
Fig 4. Receiver differential data jitter.
tFST +3.3 V differential data lines VIH(min)
0V
MGR872
Fig 5. Receiver SE0 width tolerance.
12.1 High-speed signals
High-speed USB signals are characterized using eye patterns. For measuring the eye patterns 4 test points have been defined (see Figure 6). The Universal Serial Bus Specification Rev. 2.0 defines the eye patterns in several `templates'. For ISP1581 Templates 1, 2, 3 and 4 are relevant.
TP1
TP2
TP3
TP4
traces
USB cable
traces
transceiver
A connector
B connector
transceiver
hub circuit board
MBL205
device circuit board
Fig 6. Eye pattern measurement planes.
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12.1.1
Template 1 (transmit waveform; device without captive cable) The eye pattern in Figure 7 defines the transmit waveform requirements for a hub (measured at TP2) or a device without a captive1 cable (measured at TP3). The corresponding signal levels and timings are given in Table 77. Timings are given as a percentage of the unit interval (UI), which represents the nominal bit duration TPERIOD for a 480 Mbit/s transmission rate.
600 differential output 500 voltage 400 (mV) 300 200 100 0 -100 -200 -300 -400 -500 -600 0 relative duration (% of unit interval) point 5 point 6 point 1
MBL206
level 1 +400 mV point 3 point 4
point 2
0
-400 mV level 2 100
Fig 7.
Template 1 eye pattern (transmit waveform).
Table 77: Template 1 eye pattern definition Name Level 1 Level 2 Point 1 Point 2 Point 3 Point 4 Point 5 Point 6
[1] [2]
Differential voltage on DP, DM (mV) +525 [1] +475 [2] -525 [1] -475 [2] 0 0 +300 +300 -300 -300
Relative duration (% of unit interval) n.a. n.a. 7.5 92.5 37.5 62.5 37.5 62.5
In the unit interval following a transition. In all other cases.
1.
Captive cables have a vendor-specific connector to the peripheral (hardwired or detachable) and a USB "A" connector on the other side. For hot plugging, the vendor-specific connector must meet the same performance requirements as a USB "B" connector.
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12.1.2
Template 2 (transmit waveform; device with captive cable) The eye pattern in Figure 8 defines the transmit waveform requirements for a device with a captive cable (measured at TP2). The corresponding signal levels and timings are given in Table 78. Timings are given as a percentage of the unit interval (UI), which represents the nominal bit duration TPERIOD for a 480 Mbit/s transmission rate.
004aaa002
600 differential output 500 voltage 400 (mV) 300 200 100 0 -100 -200 -300 -400 -500 -600 0 relative duration (% of unit interval) point 5 point 6 point 1 point 2 point 3 point 4
level 1 +400 mV
0
-400 mV level 2 100
Fig 8.
Template 2 eye pattern (transmit waveform).
Table 78: Template 2 eye pattern definition Name Level 1 Level 2 Point 1 Point 2 Point 3 Point 4 Point 5 Point 6
[1] [2]
Differential voltage on DP, DM (mV) +525 [1] +475 [2] -525 [1] -475 [2] 0 0 +175 +175 -175 -175
Relative duration (% of unit interval) n.a. n.a. 12.5 87.5 35 65 35 65
In the unit interval following a transition. In all other cases.
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12.1.3
Template 3 (receive waveform; receiver sensitivity with captive cable) The eye pattern defined in Figure 9 defines the receiver sensitivity requirements for a device with a captive cable (signal applied at test point TP2). The corresponding signal levels and timings are given in Table 79. Timings are given as a percentage of the unit interval (UI), which represents the nominal bit duration TPERIOD for a 480 Mbit/s transmission rate.
600 differential 500 input voltage 400 (mV) 300 200 100 0 -100 -200 -300 -400 -500 -600 point 5 point 6 point 1 point 3 point 4
004aaa003
level 1
+400 mV
point 2
0
-400 mV
level 2 0 relative duration (% of unit interval) 100
Fig 9.
Template 3 eye pattern (receive waveform).
Table 79: Template 3 eye pattern definition Name Level 1 Level 2 Point 1 Point 2 Point 3 Point 4 Point 5 Point 6 Differential voltage on DP, DM (mV) +575 -575 0 0 +275 +275 -275 -275 Relative duration (% of unit interval) n.a. n.a. 10 90 40 60 40 60
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12.1.4
Template 4 (receive waveform; receiver sensitivity without captive cable) The eye pattern defined in Figure 10 defines the receiver sensitivity requirements for a hub (signal applied at test point TP2) or a device without a captive cable (signal applied at test point TP3). The corresponding signal levels and timings are given in Table 80. Timings are given as a percentage of the unit interval (UI), which represents the nominal bit duration TPERIOD for a 480 Mbit/s transmission rate.
MBL207
600 differential 500 input voltage 400 (mV) 300 200 100 0 -100 -200 -300 -400 -500 -600 point 5 point 6 point 1 point 2 point 3 point 4
level 1
+400 mV
0
-400 mV
level 2 0 relative duration (% of unit interval) 100
Fig 10. Template 4 eye pattern (receive waveform). Table 80: Template 4 eye pattern definition Name Level 1 Level 2 Point 1 Point 2 Point 3 Point 4 Point 5 Point 6 Differential voltage on DP, DM (mV) +575 -575 0 0 +150 +150 -150 -150 Relative duration (% of unit interval) n.a. n.a. 15 85 35 65 35 65
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12.2 Timing symbols
Table 81: Legend for timing characteristics Symbol Time symbols t T Signal names A C D E G I L P Q R address; DMA acknowledge (DACK) clock; command data input; data chip enable output enable instruction (program memory content); input (general) address latch enable (ALE) program store enable (PSEN, active LOW); propagation delay data output read signal (RD, active LOW); read (action); DMA request (DREQ) S W chip select write signal (WR, active LOW); write (action); pulse width U Y Logic levels H L P S V X Z logic HIGH logic LOW stop, not active (OFF) start, active (ON) valid logic level invalid logic level high-impedance (floating, three-state) undefined output (general) time cycle time (periodic signal) Description
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12.3 Parallel I/O timing
12.3.1 Generic Processor mode (BUS_CONF = 1)
Tcy(RW) t WHSH t RHSH CS t WHAX t RHAX AD [7:0] t RLDV (read) DATA [15:0] t AVRL RD t AVWL (write) DATA [15:0] t I1VI2L DS/WR (I2) read R/W (I1) write
MGT497
t RHDZ
t WHDZ
t DVWH
t I2HI1X
Fig 11. Parallel I/O timing: separate address and data buses. Table 82: Parallel I/O timing parameters: separate address and data buses Symbol Reading tAVRL tRHAX tRLDV tRHDZ tRHSH Writing tAVWL tWHAX tDVWH tWHDZ tWHSH address set-up time before WR LOW address hold time after WR HIGH data set-up time before WR HIGH data hold time after WR HIGH WR HIGH to CS HIGH delay 0 0 25 0 0 ns ns ns ns ns address set-up time before RD LOW address hold time after RD HIGH RD LOW to data valid delay RD HIGH to data outputs three-state delay RD HIGH to CS HIGH delay 0 0 0 0 35 20 ns ns ns ns ns Parameter Min Max Unit
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Table 82: Parallel I/O timing parameters: separate address and data buses...continued Symbol General Tcy(RW) tI1VI2L tI2HI1X read/write cycle time R/W set-up time before DS LOW R/W hold time after DS HIGH 60 5 5 ns ns ns Parameter Min Max Unit
12.3.2
Split Bus mode (BUS_CONF = 0)
Tcy(RW) t WHSH CS t RLDV (read) AD [7:0] address t LLRL RD t WHDZ (write) AD [7:0] address data t DVWH data t RHSH t RHDZ
t LLWL t LLI2L DS/WR (I2)
t I2HI1X R/W (I1) t AVLL t I1VLL ALE
MGT498
Fig 12. Parallel interface timing: multiplexed address/data bus. Table 83: Parallel I/O timing parameters: multiplexed address/data bus Symbol Reading tRLDV tRHDZ tRHSH tLLRL Writing tDVWH tLLWL tWHDZ tWHSH data set-up time before WR HIGH ALE LOW to WR LOW delay data hold time after WR HIGH WR HIGH to CS HIGH delay 25 5 0 0 ns ns ns ns RD LOW to data valid delay RD HIGH to data outputs three-state delay RD HIGH to CS HIGH delay ALE LOW set-up time before RD LOW 0 0 0 35 20 ns ns ns ns Parameter Min Max Unit
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Table 83: Parallel I/O timing parameters: multiplexed address/data bus...continued Symbol General Tcy(RW) tAVLL tI1VLL tLLI2L tI2HI1X read/write cycle time address set-up time before ALE LOW R/W set-up time before ALE LOW ALE LOW to DS LOW delay R/W hold time after DS HIGH 60 3 3 5 5 ns ns ns ns ns Parameter Min Max Unit
12.4 DMA timing
12.4.1 PIO mode
Tcy1 device (1) address valid
t su1
t h1
DIOR, DIOW (4) t w1 (write) DATA [7:0] (2) t su2 (read) DATA [7:0] (2) t su3 t h3(min) t d2 t h2 t w2
IORDY (3a)
HIGH
t su4 IORDY (3b) t su5 IORDY (3c) t su4 t w3
MGT499
(1) The device address consists of signals CS1, CS0, DA2, DA1 and DA0. (2) The data bus width depends on the PIO access command used. Task File register access uses 8 bits (DATA[7:0]), except for Task File register 1F0 which uses 16 bits (DATA[15:0]). DMA commands 04H and 05H also use a 16-bit data bus. (3) The device can negate IORDY to extend the PIO cycle with wait states. The host determines whether or not to extend the current cycle after tsu4 following the assertion of DIOR or DIOW. The following three cases are distinguished: a) Device keeps IORDY released (high-impedance): no wait state is generated. b) Device negates IORDY during tsu4, but re-asserts IORDY before tsu4 expires: no wait state is generated. c) Device negates IORDY during tsu4 and keeps IORDY negated for at least 5 ns after tsu4 expires: a wait state is generated. The cycle is completed as soon as IORDY is re-asserted. For extended read cycles (DIOR asserted), the read data on lines DATAn must be valid at td1 before IORDY is asserted. (4) DIOR and DIOW have a programmable polarity: shown here as active LOW signals.
Fig 13. PIO mode timing.
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Table 84: PIO mode timing parameters Symbol Tcy1(min) tsu1(min) tw1(min) tw2(min) tsu2(min) th2(min) tsu3(min) th3(min.) td2(max) th1(min) tsu4(min) tsu5(min) tw3(max)
[1]
Parameter read/write cycle time (minimum) address to DIOR/DIOW on set-up time (minimum) DIOR/DIOW pulse width (minimum) DIOR/DIOW recovery time (minimum) data set-up time before DIOW off (minimum) data hold time after DIOW off (minimum) data set-up time before DIOR on (minimum) data hold time after DIOR off (minimum) data to three-state delay after DIOR off (minimum) address hold time after DIOR/DIOW off (minimum) IORDY after DIOR/DIOW on set-up time (minimum) read data to IORDY HIGH set-up time (minimum) IORDY LOW pulse width (maximum)
[3] [2] [1] [1] [1]
Mode 0 600 70 165 60 30 50 5 30 20 35 0 1250
Mode 1 383 50 125 45 20 35 5 30 15 35 0 1250
Mode 2 240 30 100 30 15 20 5 30 10 35 0 1250
Mode 3 180 30 80 70 30 10 20 5 30 10 35 0 1250
Mode 4 120 25 70 25 20 10 20 5 30 10 35 0 1250
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
[3]
[2] [3]
Tcy1 is the total cycle time, consisting of the command active time tw1and is the command recovery (= inactive) time tw2: Tcy1 = tw1 + tw2. The minimum timing requirements for Tcy1, tw1 and tw2 must all be met. Since Tcy1(min) is greater than the sum of tw1(min) and tw2(min), a host implementation must lengthen tw1 and/or tw2 to ensure that Tcy1 is equal to or greater than the value reported in the IDENTIFY DEVICE data. A device implementation shall support any legal host implementation. td2 specifies the time after DIOR is negated, when the data bus is no longer driven by the device (three-state). If IORDY is LOW at tsu4, the host waits until IORDY is made HIGH before the PIO cycle is completed. In that case, tsu5 must be met for reading (tsu3 does not apply). When IORDY is HIGH at tsu4, tsu3 must be met for reading (tsu5 does not apply).
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12.4.2
GDMA slave mode
DREQ (2) t su1 DACK (1) t d2 DIOR/DIOW (1) t h2 (read) DATA [15:0] t su2 (write) DATA [15:0]
MGT500
t w1
Tcy1
t h1
t d1
DREQ is continuously asserted until the last transfer is done or the FIFO is full. Data strobes: DIOR (read), DIOW (write). (1) Programmable polarity: shown as active LOW. (2) Programmable polarity: shown as active HIGH.
Fig 14. GDMA slave mode timing (BURST = 00H, MODE = 00H).
DREQ (2) t su1 DACK (1) t d2 DIOR/DIOW (1) HIGH t h2 (read) DATA [15:0] t su2 (write) DATA [15:0]
MGT501
t w1
Tcy1
t h1
t d1
DREQ is continuously asserted until the last transfer is done or the FIFO is full. Data strobe: DACK (read/write). (1) Programmable polarity: shown as active LOW. (2) Programmable polarity: shown as active HIGH.
Fig 15. GDMA slave mode timing (BURST = 00H, MODE = 02H).
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DREQ (2) t su1 DACK (1) t d2 DIOR/DIOW (1) t h2 (read) DATA [15:0] t su2 (write) DATA [15:0]
MGT502
t w1
Tcy1
t d1
t h1
DREQ is asserted for every transfer. Data strobes: DIOR (read), DIOW (write). (1) Programmable polarity: shown as active LOW. (2) Programmable polarity: shown as active HIGH.
Fig 16. GDMA slave mode timing (BURST = 01H, MODE = 00H).
DREQ (2) t su1 DACK (1) t d2 DIOR/DIOW (1) HIGH t h2 (read) DATA [15:0] t su2 (write) DATA [15:0]
MGT503
t w1
Tcy1
t d1
t h1
DREQ is asserted for every transfer. Data strobe: DACK (read/write). (1) Programmable polarity: shown as active LOW. (2) Programmable polarity: shown as active HIGH.
Fig 17. GDMA slave mode timing (BURST = 01H, MODE = 02H).
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DREQ (2) t su1 DACK (1) t d2 DIOR/DIOW (1) t h2 (read) DATA [15:0] t su2 (write) DATA [15:0]
MGT504
t w1
t h1
Tcy1
t d1
DREQ is asserted once per N transfers (N is determined by the BURST value). Example shown here: N = 2. Data strobes: DIOR (read), DIOW (write). (1) Programmable polarity: shown as active LOW. (2) Programmable polarity: shown as active HIGH.
Fig 18. GDMA slave mode timing (BURST > 01H, MODE = 00H).
DREQ (2) t su1 DACK (1) t d2 DIOR/DIOW (1) HIGH t h2 (read) DATA [15:0] t su2 (write) DATA [15:0]
MGT505
t w1
t h1
Tcy1
t d1
DREQ is asserted once per N transfers (N is determined by the BURST value). Example shown here: N = 2. Data strobe: DACK (read/write). (1) Programmable polarity: shown as active LOW. (2) Programmable polarity: shown as active HIGH.
Fig 19. GDMA slave mode timing (BURST > 01H, MODE = 02H).
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Table 85: GMDA slave mode timing parameters Symbol Tcy1 tsu1 td1 th1 tw1 td2 th2 tsu2 Parameter read/write cycle time DREQ set-up time before first DACK on DREQ on delay after last strobe off DREQ hold time after last strobe on DIOR/DIOW pulse width read data valid delay after strobe on read data hold time after strobe off write data set-up time before strobe off Min 66.67 0 33.33 0 33.33 5 10 Max 33.33 10 Unit ns ns ns ns ns ns ns ns
12.4.3
MDMA mode
DREQ (2) Tcy1 DACK (1) t su1 DIOR/DIOW (1) t d1 (write) DATA [15:0] t h3 (read) DATA [15:0] t su2
MGT506
t w1
t w2
t d2
t h1
t d3
t su2
t h2
(1) Programmable polarity: shown as active LOW. (2) Programmable polarity: shown as active HIGH.
Fig 20. MDMA master mode timing. Table 86: MDMA mode timing parameters Symbol Tcy1(min) tw1(min) td1(max) th3(min) tsu2(min) th2(min) tsu1(min) th1(min) Parameter read/write cycle time (minimum) [1] DIOR/DIOW pulse width (minimum) [1] data valid delay after DIOR on (maximum) data hold time after DIOR off (minimum) data set-up time before DIOR/DIOW off (minimum) Mode 0 Mode 1 Mode 2 Unit 480 215 150 5 100 150 80 60 5 30 15 0 5 120 70 50 5 20 10 0 5 ns ns ns ns ns ns ns ns
data hold time after DIOW off (minimum) 20 DACK set-up time before DIOR/DIOW on 0 (minimum) DACK hold time after DIOR/DIOW off (minimum) 20
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Table 86: MDMA mode timing parameters...continued Symbol tw2(min) td2(max) td3(max) Parameter DIOR recovery time DIOW recovery time (minimum) [1] (minimum) [1] Mode 0 Mode 1 Mode 2 Unit 50 215 120 40 20 50 50 40 40 25 25 25 35 35 25 ns ns ns ns ns
DIOR on to DREQ off delay (maximum) DIOW on to DREQ off delay (maximum) DACK off to data lines three-state delay (maximum)
[1]
Tcy1 is the total cycle time, consisting of the command active time tw1and is the command recovery (= inactive) time tw2: Tcy1 = tw1 + tw2. The minimum timing requirements for Tcy1, tw1 and tw2 must all be met. Since Tcy1(min) is greater than the sum of tw1(min) and tw2(min), a host implementation must lengthen tw1 and/or tw2 to ensure that Tcy1 is equal to or greater than the value reported in the IDENTIFY DEVICE data. A device implementation shall support any legal host implementation.
12.4.4
UDMA mode
Tcy1 t su1 DIOR (1) (sender) t h1 DATA [15:0] (1) (sender) t h2 IORDY (1) (receiver) t su2 t h2 t h1
Tcy1 t su1
t h1
t su2
t h2
DATA [15:0] (1) (receiver)
MGT507
(1) DATA[15:0] and strobe signals at the receiver require some time to stabilize due to the settling time and propagation delay of the cable.
Fig 21. UDMA timing: sustained synchronous burst.
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DREQ (drive) t d1 DACK (1) (host) t su3 DIOW (host) t su3 DIOR (host) t d11 IORDY (drive) t d4 DATA [15:0] (drive) t su3 DA [2:0] and CS [1:0]
MGT508
t d6
t d13
t d6
t d13
t d5
t su1
t h1
(1) Programmable polarity: shown as active LOW.
Fig 22. UDMA timing: drive initiating a burst for a read command.
DREQ (drive) t d1 DACK (1) (host) t su3 DIOW (host) t d11 IORDY (drive) t su3 DIOR (host) t su1 DATA [15:0] (host) t su3 DA [2:0] and CS [1:0]
MGT509
t d6
t d2
t d1
t h1
(1) Programmable polarity: shown as active LOW.
Fig 23. UDMA timing: drive initiating a burst for a write command.
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t d7 DREQ (drive)
DACK (1) (host)
LOW t d7
DIOW (host) t d8 IORDY t d9 DIOR
DATA [15:0]
MGT510
(1) Programmable polarity: shown as active LOW.
Fig 24. UDMA timing: receiver pausing a burst.
DREQ (drive) t d3 DACK (1) (host) t d2 DIOW (host) t d2 DIOR (host) t d12 IORDY (drive) t d4 DATA [15:0] (drive) t d5 DA [2:0] and CS [1:0]
MGT511
t h3
t h3
t d2
t d10
t su1
t h1 CRC t h3
(1) Programmable polarity: shown as active LOW.
Fig 25. UDMA timing: drive terminating a burst during a read command.
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DREQ (drive) t h3 DACK (1) (host) t d2 DIOW (host) t d7 IORDY (drive) t d9 DIOR (host) t su1 DATA [15:0] (host) CRC t h3 DA [2:0] and CS [1:0]
MGT512
t d3
t d10
t d2
t d3
t h3
t h1
(1) Programmable polarity: shown as active LOW.
Fig 26. UDMA timing: drive terminating a burst during a write command.
t d2 DREQ (drive) t d3 DACK (1) (host) t d7 DIOW (host) t h3 DIOR (host) t d9 IORDY (drive) t su1 DATA [15:0] (drive) CRC t h3 DA [2:0] and CS [1:0]
MGT513
t d5 t d4 t h3
t d2
t d3 t d10
t h1
(1) Programmable polarity: shown as active LOW.
Fig 27. UDMA timing: host terminating a burst during a read command.
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ISP1581
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t d2 DREQ (drive) t d2 DACK (1) (host) t h3 DIOW (host) t d2 IORDY (drive) t d12 DIOR (host) t su1 DATA [15:0] (host) CRC t h3 DA [2:0] and CS [1:0]
MGT514
t d3
t d10
t h3
t h1
(1) Programmable polarity: shown as active LOW.
Fig 28. UDMA timing: host terminating a burst during a write command. Table 87: UDMA mode timing parameters Symbol Tcy1 tsu2 th2 tsu1 th1 td1 td2 td3 td4 td5 tsu3 th3 td6 td7 td8 td9
9397 750 07648
Parameter read/write cycle time (from strobe edge to strobe edge) data set-up time at receiver data hold time at receiver data set-up time at sender data hold time at sender unlimited interlock time [1] limited interlock time [1] minimum [1] limited interlock time with
Mode 0 Min 114 15 5 70 6 0 0 20 20 0 20 20 20 160 Max 150 10 70 50 75
Mode 1 Min 75 10 5 48 6 0 0 20 20 0 20 20 20 125 Max 150 10 70 30 60
Mode 2 Min 55 7 5 34 6 0 0 20 20 0 20 20 20 100 Max 150 10 70 20 50
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
data line drivers switch-off delay data line drivers switch-on delay (host) data line drivers switch-on delay (drive) control signal set-up time before DACK on control signal hold time after DACK off DACK on to control signal transition delay ready to paused delay strobe to ready delay to ensure a synchronous pause ready to final strobe edge delay
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Table 87: UDMA mode timing parameters...continued Symbol td10 td11 td12 td13
[1]
Parameter DACK off to IORDY high-Z delay DACK on to IORDY HIGH delay final strobe edge to DREQ off or DIOW on delay first strobe delay after control signal on 0
Mode 0 Min Max 20 230 0
Mode 1 Min Max 20 200 0
Mode 2 Min Max 20 170
Unit ns ns ns ns
50 0
50 0
50 0
Interlock time is the time allowed between an action by one agent and the following action by the other agent. An agent can be a sender or a receiver. Interlocking actions require a response signal from the other agent before processing can continue.
13. Application information
address 8 data CPU 16
ISP1581
AD7 to AD0 DATA15 to DATA0
read strobe write strobe chip select
(R/W)/RD DS/WR CS
MGT515
Fig 29. Typical interface connections for Generic Processor mode.
DATA [15:0] DREQ
ISP1581
DMA
DACK DIOW DIOR
ALE/A0 address latch enable ALE
INT
(R/W)/RD
DS/WR
AD7 to AD0 address/data 8
interrupt
read strobe
write strobe WR
INTn
RD
8051 MICROCONTROLLER
P0.7/AD7 to P0.0/AD0
MGT516
Fig 30. Typical interface connections for Split Bus mode.
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14. Test information
The dynamic characteristics of the analog I/O ports (D+, D-) as listed in Table 76, were determined using the circuit shown in Figure 31.
test point 22 D.U.T 15 k CL 50 pF
MGT495
In full-speed mode an internal 1.5 k pull-up resistor is connected to pin D+.
Fig 31. Load impedance for D+ and D- pins (full-speed mode).
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15. Package outline
LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2
c
y X A 48 49 33 32 ZE
e E HE wM bp 64 1 pin 1 index 16 ZD bp D HD wM B vM B vM A 17 detail X L Lp A A2 A1 (A 3)
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.60 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.5 HD HE L 1.0 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 1.45 1.05 1.45 1.05 7 0o
o
12.15 12.15 11.85 11.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT314-2 REFERENCES IEC 136E10 JEDEC MS-026 EIAJ EUROPEAN PROJECTION
ISSUE DATE 99-12-27 00-01-19
Fig 32. LQFP64 package outline.
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16. Soldering
16.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.
16.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C small/thin packages.
16.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
* Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.
* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle
to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners.
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During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
16.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
16.5 Package related soldering information
Table 88: Suitability of surface mount IC packages for wave and reflow soldering methods Package BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC [3], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO
[1]
Soldering method Wave not suitable not suitable [2] Reflow [1] suitable suitable suitable suitable suitable
suitable not recommended [3] [4] not recommended [5]
[2]
[3] [4] [5]
All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
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17. Revision history
Table 89: Revision history Rev Date 02 20001023 CPCN Description Objective specification; second version. Supersedes ISP1581-01 of 4 October 2000 (9397 750 07487). Package replaced by SOT314-2. 01 20001004 Objective specification; initial version. Not published.
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18. Data sheet status
Datasheet status Objective specification Preliminary specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Product specification
Production
[1]
Please consult the most recently issued data sheet before initiating or completing a design.
19. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
20. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
21. Trademarks
ACPI -- is an open industry specification for PC power management, co-developed by Intel Corp., Microsoft Corp. and Toshiba Jaz -- is a registered trademark of Iomega Corp. OnNow -- is a trademark of Microsoft Corp. SoftConnect -- is a trademark of Royal Philips Electronics Zip -- is a registered trademark of Iomega Corp.
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Internet: http://www.semiconductors.philips.com
(SCA70)
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Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 8 9 9.1 9.2 9.2.1 9.2.2 9.2.3 9.2.4 9.2.5 9.2.6 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.3.7 9.4 9.4.1 9.4.2 9.4.3 9.4.4 9.4.5 9.4.6 9.4.7 9.4.8 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 7 USB 2.0 transceiver . . . . . . . . . . . . . . . . . . . . . 8 Philips Serial Interface Engine (SIE). . . . . . . . . 9 Voltage regulators. . . . . . . . . . . . . . . . . . . . . . . 9 Memory Management Unit (MMU) and integrated RAM . . . . . . . . . . . . . . . . . . . . . . . . 9 SoftConnect . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bit clock recovery . . . . . . . . . . . . . . . . . . . . . . . 9 Multiplying PLL oscillator . . . . . . . . . . . . . . . . . 9 Microcontroller Interface and Microcontroller Handler . . . . . . . . . . . . . . . . . 10 DMA Interface and DMA Handler . . . . . . . . . . 10 System Controller . . . . . . . . . . . . . . . . . . . . . . 10 Modes of operation . . . . . . . . . . . . . . . . . . . . . 11 Register descriptions . . . . . . . . . . . . . . . . . . . 11 Register access . . . . . . . . . . . . . . . . . . . . . . . 13 Initialization registers . . . . . . . . . . . . . . . . . . . 13 Address register (address: 00H). . . . . . . . . . . 13 Mode register (address: 0CH) . . . . . . . . . . . . 14 Interrupt Configuration register (address: 10H) 15 Interrupt Enable register (address: 14H) . . . . 16 DMA Configuration register (address: 38H) . . 17 DMA Hardware register (address: 3CH). . . . . 17 Data flow registers . . . . . . . . . . . . . . . . . . . . . 18 Endpoint Index register (address: 2CH) . . . . . 18 Control Function register (address: 28H) . . . . 19 Data Port register (address: 20H). . . . . . . . . . 19 Buffer Length register (address: 1CH) . . . . . . 20 Endpoint MaxPacketSize register (address: 04H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Endpoint Type register (address: 08C). . . . . . 22 Short Packet register (address: 24H) . . . . . . . 22 DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . 24 DMA Command register (address: 30H) . . . . 26 DMA Transfer Counter register (address: 34H) 27 DMA Configuration register (address: 38H) . . 28 DMA Hardware register (address: 3CH). . . . . 30 DMA Strobe Timing register (address: 60H). . 31 Task File registers (addresses: 40H to 4FH) . 32 DMA Interrupt Reason register (address: 50H) 35 DMA Interrupt Enable register (address: 54H) 36 9.4.9 DMA Endpoint register (address: 58H) . . . . . . 9.5 General registers . . . . . . . . . . . . . . . . . . . . . . 9.5.1 Interrupt register (address: 18H). . . . . . . . . . . 9.5.2 Chip ID register (address: 70H) . . . . . . . . . . . 9.5.3 Frame Number register (address: 74H) . . . . . 9.5.4 Scratch register (address: 78H) . . . . . . . . . . . 9.5.5 Unlock Device register (address: 7CH). . . . . . 9.5.6 Test Mode register (address: 84H) . . . . . . . . . 10 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 11 Static characteristics . . . . . . . . . . . . . . . . . . . . 12 Dynamic characteristics . . . . . . . . . . . . . . . . . 12.1 High-speed signals . . . . . . . . . . . . . . . . . . . . . 12.1.1 Template 1 (transmit waveform; device without captive cable) . . . . . . . . . . . . . . . . . . 12.1.2 Template 2 (transmit waveform; device with captive cable) . . . . . . . . . . . . . . . . . . . . 12.1.3 Template 3 (receive waveform; receiver sensitivity with captive cable). . . . . . . . . . . . . 12.1.4 Template 4 (receive waveform; receiver sensitivity without captive cable) . . . . . . . . . . 12.2 Timing symbols . . . . . . . . . . . . . . . . . . . . . . . . 12.3 Parallel I/O timing . . . . . . . . . . . . . . . . . . . . . . 12.3.1 Generic Processor mode (BUS_CONF = 1) . . 12.3.2 Split Bus mode (BUS_CONF = 0). . . . . . . . . . 12.4 DMA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4.1 PIO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4.2 GDMA slave mode . . . . . . . . . . . . . . . . . . . . . 12.4.3 MDMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4.4 UDMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Application information. . . . . . . . . . . . . . . . . . 14 Test information . . . . . . . . . . . . . . . . . . . . . . . . 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 Soldering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.1 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 16.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 16.4 Manual soldering. . . . . . . . . . . . . . . . . . . . . . . 16.5 Package related soldering information . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 19 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 37 37 38 39 40 40 41 42 42 44 46 47 48 49 50 51 52 52 53 54 54 56 59 60 65 66 67 68 68 68 68 69 69 70 71 71 71 71
(c) Philips Electronics N.V. 2000.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 23 October 2000 Document order number: 9397 750 07648

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