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Ordering number : ENN*6495
CMOS IC
LC898093
40x Playback/12x Write CD-R/RW Encoder/Decoder IC with Built-in ATAPI Interface
Preliminary Functions
* * * * * * * * CD-ROM decoder/encoder functions CD decoder/encoder functions Pit and wobble CLV servo CAV audio functions ATAPI interface (include the register block) Subcode encoder/decoder functions ATIP demodulator/ATIP decoder Write strategy function (CD-R/RW) * From 1 to 64 Mbits of buffer RAM can be used. (16-bit data bus EDO DRAM) * The user can freely set up the CD main channel, C2 flag, and subcode areas in buffer RAM. * Batch transfer function (Function for transferring the CD main channel, C2 flag, subcode, and other data in a single operation) * Multi-transfer function (Function for automatically transferring multiple block to the host in a single operation) * CAV audio functions * Supports Ultra DMA modes 0, 1, and 2.
Features
* ECC and EDC correction/addition (decoding/encoding) for CD-ROM data. * ECC error correction/addition (decoding/encoding) for subcode data * Servo control implemented in a digital servo system (decoding/encoding) * CLV servo control using ATIP data (encoding) * ATIP decoding function and CRC check function (decoding/encoding) * CIRC code generation and addition and EFM modulation (encoding) * CAV audio functions * Provides high-precision CD-R/RW write strategy signal output * Built-in ATAPI interface (with Ultra DMA 33 support) * Supports 40x decoding and 12x encoding. Clock frequency: 33.8688 MHz * Transfer rates: Up to 16.6 MB/s (when 32x IORDY used), up to 33 MB/s when Ultra DMA used. These values apply when 16-bit 45 ns EDO DRAM is used.
"BURN-Proof" stands for Proof against Buffer Under RuN error, not for proof against burning. "BURN-Proof" is a trademark of SANYO Electric Co., Ltd.
Package Dimensions
unit: mm 3210-SQFP208
[LC898093]
0.5 30.6 28.0
156 157
105 104
208 1
(1.25) (3.2) (0.5) 0.2
53 52
0.15
3.8max
0.35
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
83100RM (OT) No. 6495-1/14
28.0
SANYO: SQFP208
30.6
LC898093
Specifications
Absolute Maximum Ratings at VSS = 0 V
Parameter Supply voltage Symbol VDD5 max VDD3 max VI5, VO5 VI3, VO3 Pd max Topr Tstg 10 seconds Ta 25C Ta 25C Ta 25C Ta 25C Ta 70C Conditions Ratings -0.3 to +6.0 -0.3 to +4.6 -0.3 to VDD5 + 0.3 -0.3 to VDD3 + 0.3 750 -30 to +70 -55 to +125 260 Unit V V V V mW C C C
I/O voltages Allowable power dissipation Operating temperature Storage temperature Soldering conditions (pins only)
Allowable Operating Ranges at Ta = -30 to +70C, VSS = 0 V
Parameter [I/O cells, 5.0 V power supply] Supply voltage Input voltage range [Internal cells, 3.3 V power supply] Supply voltage Input voltage range VDD3 VIN 3.0 0 3.3 3.6 VDD3 V V VDD5 VIN 4.5 0 5.0 5.5 VDD5 V V Symbol Conditions Ratings min typ max Unit
Electrical Characteristics at Ta = -30 to +70C, VSS = 0 V, VDD = 4.5 to 5.5 V
Parameter High-level input voltage Low-level input voltage High-level input voltage Low-level input voltage High-level input voltage Low-level input voltage High-level input voltage Low-level input voltage High-level input voltage Low-level input voltage Analog input voltage High-level output voltage Low-level output voltage High-level output voltage Low-level output voltage Low-level output voltage High-level output voltage Low-level output voltage Input leakage current Output leakage current Pull-up resistance Pull-up resistance Pull-up resistance Pull-up resistance Symbol VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VANI VOH VOL VOH VOL VOL VOH VOL IIL IOZ RUP RUP RUP RUP Conditions Ratings min 2.2 0.8 2.2 0.8 2.4 0.8 2.4 0.8 0.7 VDD 0.3 VDD 1/4 VDD VDD - 2.1 0.4 VDD - 2.1 0.4 0.4 VDD - 2.1 0.4 -10 -10 50 40 7 7 100 80 10 10 +10 +10 200 160 13 13 3/4 VDD typ max Unit V V V V V V V V V V V V V V V V V V A A k k k k
TTL level inputs: (1)
TTL level inputs with built-in pull-up resistors: (4)
TTL level Schmitt trigger inputs: (0), (7) TTL level Schmitt trigger inputs Built-in pull-up resistors: (9), (14) CMOS level inputs with built-in pull-up resistors: (10) (11) IOH = -8 mA: (3), (8) IOL = 8 mA: (3), (8) IOH = -2 mA: (2), (4), (6) IOL = 2 mA: (2), (4), (6) IOL = 2 mA: (5) IOH = -8 mA: (7), (12), (14), (15) IOL = 24 mA: (7), (12), (14), (15) VI = VSS, VDD: (0), (1), (7), (9) In the high-impedance output state: (2), (7), (8), (12), (13) (14), (15) (10) (4), (5) (9), (13), (14) (15)
The applicable pin groups are listed on the following page.
No. 6495-2/14
LC898093 Applicable Pins [INPUT] (0) * * * * * * CS, RD, WR, WRITE, SUA0 to SUA7, RESET, WOBBLE, CS1FX, CS3FX, DIOR, DIOW, HRST (9) * * * * * * DMACK (1) * * * * * * TEST0 to TEST4 (10) * * * * * FG (11) * * * * * AD0, AD1, RREC, FE, TE, VREF, AD2, TES [OUTPUT] (2) * * * * * * PDS1 to PDS3, DSLB (3) * * * * * * RA0 to RA9, CAS0 and CAS1, RAS0 to RAS2, LWE, UWE, OE, SSP2/1, RAPC, WAPC, H11T0, LDH, ATEST3/1, WDAT, NWDAT, EFMG, SHOCK, LOCK, EFMO, ATIPSYNC, ACRCNG, PCK2 (6) * * * * * * LDON (12) * * * * * INTRQ, IOCS16 (13) * * * * * IORDY (15) * * * * * DMARQ [INOUT] (4) * * * * * * D0 to D7, IO0 to IO15 (5) * * * * * * INT0 and INT1, SWAIT (7) * * * * * * DD0 to DD15 (8) * * * * * * BIDATA, BICLK (14) * * * * * DASP, PDIAG Note: The XTAL0 pin is not specified in the DC characteristics. The pull-up and pull-down resistors on pins (9), (13), (14), and (15) are disabled after a reset.
No. 6495-3/14
LC898093 External Circuit for the PLL Circuit 1. Internal Reference Clock Oscillator Block
PD R2 R3 VCNT C2 R1 R C1
Symbol R1 R2 R3 C1 C2 Value (typ) 5.6 k 10 k 200 0.1 0.1 Unit F F
A13192
2. Write Strategy Block
C5 MDC1
Symbol R4 Value (typ) 5.6 k 15 k 220 0.1 0.1 0.1 Unit F F F
R5 PD1
R5 R6 C3 C4
R6 VCNT1
C3
C5
C4 R4 R1
A13193
The analog VDD and VSS pins (pins 52, 53, 90, and 91) must be completely isolated from the logic system power supply and must not be influenced by fluctuations in the logic system power supply.
No. 6495-4/14
LC898093 Block Diagram
Data bus[0:7] Write Strategy & Link-position ATIP/CLV servo ATIPSYNC Sub-code I/F de-interleve/interleve Digital Servo & CIRC EnDec Address generator Sub-code ECC Address generator
LC898093
RAM Data bus[0:15] Address bus[0:21]
*12
*11 *10
*1
CAV-Audio
DAC
*13
CD-DSP I/F & SYNC Detector
De-scramble & Buffering Address generator
ECC & EDC Address generator HOST *3 *4 *5 INT0, INT1 *6 Micro controller *7 ZSWAIT XTALCK0 XTAL0 PLL & Clock generator Each Block Each Block Register R0-R255 decoder Address generator
Each Block Bus control signal External Bus Arbiter & DRAM controller *8 *9 Buffer
IDE I/F Block based HISIDE
DRAM Data output input I/F
Microcontroller RAM access Address generator
*1 *3 *4 *5 *6 *7 *8 *9 *10 *11 *12 *13 **1
DSLB (pin96) to SUBSYNC (pin145), SHOCK (pin147) to PCK2 (pin155) DD0 to DD15, DASP, PDIAG CS1FX, CS3FX, DA0 to DA2, DIOR, DIOW, DMACK DMARQ, HINTRQ, IOCS16, IORDY RD, WR, SUA0 to SUA7, CS D0 to D7 IO0 to IO15 RA0 to RA9, RAS0, RAS1, RAS2, CAS0, CAS1, OE, UWE, LWE WOBBLE ATIPSYNC, BIDATA, BICLK WRITE, SSP2/1, RAPC, WAPC, H11T0, LDH, ATEST3, ATEST1, WDAT, NWDAT, EFMG LOUT, ROUT HISIDE (WD25C32) is made by WESTERN DIGITAL.
A13194
No. 6495-5/14
LC898093 Pin Functions
Pin type I O Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Pin name VSS RA4 RA5 RA6 RA7 RA8 RA9 VDD VSS IO0 IO1 IO2 IO3 IO4 IO5 VDD VSS IO6 IO7 IO8 IO9 IO10 VSS VDD IO11 IO12 IO13 IO14 IO15 ATIPSYNC BIDATA BICLK WOBBLE VDD VSS ACRCNG WRITE SSP2 SSP1 RAPC WAPC H11T0 Type P O O O O O O P P B B B B B B P P B B B B B P P B B B B B O B B I P P O I O O O O O Digital system power supply (5 V) Digital system ground (VSS) ATIP CRC result output signal Write strategy signal control input Servo sampling pulse output Servo sampling pulse output Laser control sampling pulse output Laser control sampling pulse output Running OPC sampling pulse ATIP demodulator signals ATIP SYNC detection signal CD-ROM encoder/decoder buffer RAM data lines These pins have built-in pull-up resistors. Digital system ground (VSS) Digital system power supply (5 V) CD-ROM encoder/decoder buffer RAM data lines These pins have built-in pull-up resistors. Digital system power supply (3.3 V) Digital system ground (VSS) CD-ROM encoder/decoder buffer RAM data lines These pins have built-in pull-up resistors. Digital system power supply (5 V) Digital system ground (VSS) CD-ROM encoder/decoder DRAM address lines Digital system ground (VSS) Input Output Pin function B P Bidirectional pin Power supply NC A Not connected Analog pin
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No. 6495-6/14
LC898093
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Pin No. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 Pin name LDH VDD VSS ATEST3 ATEST1 WDAT NWDAT VDD VSS VDD VSS R1 VCNT1 MDC1 PD1 SWAIT INT0 INT1 D0 D1 D2 D3 D4 D5 D6 VDD VSS D7 SUA0 SUA1 SUA2 SUA3 SUA4 SUA5 SUA6 SUA7 CS RD WR TEST0 VCNT R PD VDD VSS TEST1 RESET XTALCK0 Type O P P O O O O P P P P I I O O O O O B B B B B B B P P B I I I I I I I I I I I I I I O P P I I I Chip select signal input from the microcontroller Data read signal input from the microcontroller Data write signal input from the microcontroller Test pin. This pin must be tied to VSS. VCO control voltage VCO bias resistor connection Charge pump output Analog system power supply (3.3 V) Analog system ground (VSS) Test pin. This pin must be tied to VSS. Reset input Crystal oscillator circuit input (33.8688 MHz) Command register selection address Digital system power supply (5 V) Digital system ground (VSS) Microcontroller data signal line Microcontroller data signal lines These pins have built-in pull-up resistors. Wait signal to the microcontroller Interrupt request signal outputs to the microcontroller These are open-drain outputs with built-in pull-up resistors. Write strategy analog signals Recording laser diode control signal output Analog system power supply (3.3 V) Analog system ground (VSS) RW output Internal monitor test output Recording laser diode control signal output Recording laser diode control signal output (WDAT inverted) Analog system power supply (3.3 V) Analog system ground (VSS) Digital system power supply (5 V) Digital system ground (VSS) Pin function
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No. 6495-7/14
LC898093
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Pin No. 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 Pin name XTAL0 ROUT VSS VDD LOUT DSLB SLCIST1 SLCIST2 VSS VDD SLCO0 SLCO1 SLCO2 VDD VSS SLCO3 EFMIN EFMIN2 JITIN JITC RPO OPP PCKISTF PCKISTP VSS VDD PDO PDS1 PDS2 VDD VSS PDS3 FR TEST2 TEST3 TEST4 AD0 RREC FE TE VREF AD1 VSS DA0 DA1 DA2 TDO Type O O P P O O I I P P O O O P P O I I I O O I I I P P O O O P P O I I I I I I I I I I P O O O O Digital system power supply (5 V) Digital system ground (VSS) EFM slice level output EFM input Jitter discrimination input Jitter output P/N balance adjustment Frequency comparator charge pump Phase comparator charge pump Analog system ground (VSS) Analog system power supply (3.3 V) Charge pump filter Charge pump selection Digital system power supply (3.3 V) Digital system ground (VSS) Charge pump selection VCO frequency setting Test pin. This pin must be tied to VSS. Test pin. This pin must be tied to VSS. Test pin. This pin must be tied to VSS. AD input Optical signal discrimination input FE input TE input VREF input AD input Analog system ground (VSS) DA output DA output DA output Tracking output EFM slice level output Crystal oscillator circuit output D/A converter output Analog system ground (VSS) Analog system power supply (5 V) D/A converter output SLC PWM output EFM slice level setting input Analog system ground (VSS) Analog system power supply (3.3 V) Pin function
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No. 6495-8/14
LC898093
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Pin No. 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Pin name VDD VSS FDO SLDO SPDO VSS VDD SUBSYNC EFMG SHOCK LOCK DEF HFL TES EFMO LDON FG PCK2 VDD VSS HRST DASP CS3FX CS1FX DA2 DA0 PDIAG DAI IOCS16 INTRQ DMACK IORDY DIOR DIOW VDD VSS DMARQ DD15 DD0 DD14 DD1 DD13 DD2 VSS DD12 DD3 DD11 Type P P O O O P P O O O O I I I O O I O P P I B I I I I B I O O I O I I P P O B B B B B B P B B B IDE interface signals Digital system ground (VSS) IDE interface signals Digital system power supply (5 V) Digital system ground (VSS) IDE interface signals Analog system power supply (5 V) Analog system ground (VSS) Focus output Sled output Spindle output Digital system ground (VSS) Digital system power supply (3.3 V) Subcode SYNC signal Write gate signal Shock detection signal PLL lock state output Defect detection signal input Mirror detection signal input Tracking zero cross signal input Post-binarization EFM signal output Laser control FG input PCK output Digital system power supply (5 V) Digital system ground (VSS) Pin function
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No. 6495-9/14
LC898093
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Pin No. 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Pin name DD4 DD10 DD5 DD9 DD6 VDD VSS DD8 DD7 RAS0 RAS1 RAS2 LWE VDD VSS UWE CAS0 CAS1 OE RA0 RA1 RA2 RA3 VDD Type B B B B B P P B B O O O O P P O O O O O O O O P Digital system power supply (5 V) CD-ROM encoder/decoder DRAM address lines DRAM lower write enable Digital system power supply (5 V) Digital system ground (VSS) DRAM upper write enable DRAM CAS signal output DRAM output enable DRAM RAS signal outputs Digital system power supply (3.3 V) Digital system ground (VSS) IDE interface signals IDE interface signals Pin function
Pin Functions CS1FX (input) Chip select signal that selects the command block register. CS3FX (input) Chip select signal that selects the control block register. DA0 to DA2 (input) Address for accessing the ATAPI interface registers. DASP (input/output) Drive 1 is output and drive 0 is input. Signal used to indicate to drive 0 that drive 1 exists. DD0 to DD15 (input/output) 16-bit data bus. This interface supports both 8-bit and 16-bit transfers. DIOR (input) Read strobe from the host. DIOW (input) Write strobe from the host. DMACK (input) Acknowledge signal from the host used during DMA transfers. Corresponds to the DMARQ request signal from the drive. DMARQ (input) Drive request signal used during DMA transfers. HINTRQ (output) Drive interrupt request signal to the host. IOCS16 (output) Signal asserted by the drive when the drive supports 16-bit transfers. This signal is not asserted during DMA transfers.
No. 6495-10/14
LC898093 IORDY (output) Indicates that the drive is ready to respond. Used during data transfers. This signal will be low when the drive is not ready. PDIAG (input/output) Signal asserted by drive 1 to indicate to drive 0 that diagnostics have completed. HRST (input) Reset signal from the host. The IDE interface is reset by a low-level input to this pin. CS (input) Chip select signal from the microcontroller. The microcontroller interface is active when this pin is low. RD, WR (input) Connect the microcontroller read and write lines to these inputs. SWAIT (input) Wait signal output to the microcontroller. When accessing buffer RAM, the microcontroller must wait if this pin is low. SUA0 to SUA7 (input) Internal register address lines D0 to D7 (input/output) Microcontroller data bus. These pins have built-in pull-up resistors. INT0, INT1 (output) Interrupt request signals output to the microcontroller. INT1 can be set to output the ATAPI interrupt by setting INT1EN (Conf-R11 bit 7) These are open drain outputs with built-in 80 k (at room temperature, 5 V) pull-up resistors. I/O0 to I/O15 (input/output) Buffer RAM data bus. These pins have built-in pull-up resistors. RA0 to RA9 (output) Buffer RAM address lines. RAS0, RAS1, RAS2 (output) Buffer DRAM RAS outputs. Normally, RAS0 is used. However, if two 16-Mbit DRAMs are used, connect the RAS0 and RAS1 lines to the RAS pins on the DRAMs. If four 16-Mbit DRAMs are used, connect the RAS0, RAS1, RAS2, and LWE lines to the RAS pins on the DRAMs. CAS0, CAS1 (output) Buffer DRAM CAS outputs. Normally, CAS0 is used. However, if two 16-Mbit DRAMs are used, connect the CAS0 output to the CAS pins on the DRAMs. If 2-CAS type DRAMs are used, connect CAS0 to UCAS and CAS1 to LCAS. OE (output) Buffer RAM read output. UWE, LWE (output) Buffer RAM write outputs. Connect these to the corresponding pins. If 2-CAS type DRAMs are used, UWE must be connected. (Leave LWE open.) 1. Analog Interface Pins RREC (input) Optical discrimination input. FE (input) Focus error signal input. TE (input) Tracking error signal input. VREF (input) Input for the servo system reference voltage.
No. 6495-11/14
LC898093 AD0, AD1 (input) A/D converter auxiliary inputs. DA0, DA1, DA2 (input) D/A converter auxiliary inputs. TES (input) TES comparator input. TDO (output) Tracking control signal output. FDO (output) Focus control signal output. SLDO (output) Sled control signal output. SPDO (output) Spindle control signal output. 2. EFM Input Block Pins EFMIN (input) EFM signal input. The high-frequency components of the RF signal acquired from the RF amplifier are cut with a capacitor, and this pin inputs that signal biased by the value of the SLCO0 to SLCO3 outputs passed through a low-pass filter. EFMIN2 (input) Used to change the time constant of the low-pass filter. SLCIST1, SLCIST2 (input) Slice level controller charge pump bias resistor connection. SLCO0, SLCO1, SLCO2, SLCO3 (output) Slice level controller charge pump outputs. These levels bias the RF signal input to the EFMIN pin after being passed through a low-pass filter. DSLB (output) Slice level control PWM output. EFMO (output) Post-binarization EFM signal output. (For monitoring) 3. EFM Clock Generation Block Pins FR (input) EFM reproduction PLL VCO bias resistor connection. PDO, PDS1, PDS2, PDS3 (output) EFM reproduction PLL lag-lead filter connection. PCKISTF (input) EFM reproduction PLL frequency comparator charge pump bias resistor connection. PCKISTP (input) EFM reproduction PLL phase comparator charge pump bias resistor connection. RPO (output) P/N balance adjustment. OPP (input) P/N balance adjustment. PCK2 (output) EFM reproduction bit clock output. 4. Jitter Discrimination Pins JITIN (input) Jitter discrimination input. JITC (output) Jitter output.
No. 6495-12/14
LC898093 5. Spindle Speed Detection Pins FG (input) Input for the speed monitor signal from the spindle driver. 6. Audio Interface Pins LOUT, ROUT (output) Left and right channel audio signal outputs. 7. RF Amplifier Interface Pins LDON (output) RF amplifier interface. 8. Write Strategy Pins WRITE, SSP2/1, RAPC, WAPC, H11T0, LDH, ATEST3, 1, WDAT, NWDAT (I/O) Write strategy signal connections. 9. ATIP Decoder Related Pins ATIPSYNC (output) ATIP synchronization detection signal. (For monitoring) BIDATA, BICLK (I/O) Input mode: Input for the biphase data and biphase clock when an external ATIP demodulator is used. Output mode: Output of the biphase data and biphase clock when the internal ATIP demodulator is used. (For monitoring) WOBBLE (input) Wobble signal input when the internal ATIP demodulator is used. ACRCNG (output) Outputs the result of the ATIP decoder CRC check. (For monitoring) RESET (input) The LC898093 reset input. A low level input resets the LC898093. This pin must be held low for at least 1 s when power is first applied. TEST4 to TEST0 (input) Test inputs. These pins must be connected to ground. XTALCK0 (input), XTAL0 (output) Drive these pins at 33.8688 MHz. This signal is used, without modification, as main clock for the CD-ROM encoder and decoder blocks, including the DRAM interface. Consult the manufacturer of the oscillator element concerning the design of the oscillator circuit. R, VCNT, PDO, R1, VCNT1, PD1, MDC1 (I/O) Clock reproduction PLL circuit pins. SUBSYNC (output) Subcode SYNC output signal from the CIRC encoder during encoding. (For monitoring) EFMG (output) Outputs a high-level signal (5 V) during write operations. SHOCK (output) Outputs a high level (5 V) when a mechanical shock is detected during decodeing. LOCK (output) Outputs a high level (5 V) when the PLL circuit is locked. DEF (input) Inputs the defect detection signal. HFL (input) Inputs the mirror detection signal.
No. 6495-13/14
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