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Standard ICs
Driver for segmented LCD module with key input function
BU9768AK / BU9768AKV
The BU9768AK / BU9768AKV are man-machine interface ICs with key input, designed for portable multimedia terminals and other devices. They can be used as drivers for operation mode display LCD panels on portable terminals, household products, car stereos, and other appliances. Up to 126 cells can be displayed, and up to 30 keys can be input. Also, a maximum of four outputs are possible using expansion pins. (The number of outputs for each pin can be changed using control codes.)
*Applications terminals, POS terminals, wireless radios, telephones, cameras, VCRs, movie projectors, car Portable multi-media
stereos, others
*Features up to 42 segment outputs, three common 1) Drive of
outputs, and up to 126 cells is possible. 2) Up to 30 keys can be input. 3) A maximum of four pins can be used as output pins for expansion.
4) 1 / 3 duty drive. 5) A bias of 1 / 2 or 1 / 3 can be selected for the LCD display power supply.
*Block diagram
Kl1 Kl2 Kl3 Kl4 Kl5 KO1 (S41) KO2 (S42) KO3 KO4 KO5 KO6 DO Key scan buffer Key scan control
CS Dl CK VDD Command decoder
Control decoder
Control register VDD1 VDD2 VSS OSC RST O.S.C LCD Power Shift register
Divider
Data latch for LCD
Segment and common driver
*** COM1 *** COM3 S1 (EP1)
*** *** S4 (EP4) S5
*** *** S40
1
Standard ICs
BU9768AK / BU9768AKV
*Pin assignments
KO2(S42) KO1(S41) COM3 COM2 COM1 KO5 KO4 KO3 S40 S39 S38 S37 S36 S35 S34 34 48 47 46 45 44 43 42 41 40 39 38 37 36 35 33 KO6 49 Kl1 50 Kl2 51 Kl3 52 Kl4 53 Kl5 54 RST 55 VDD 56 VDD1 57 VDD2 58 VSS 59 OSC 60 DO 61 CS 62 CK 63 DI 64 S33 32 S32 31 S31 30 S30 29 S29 28 S28 27 S27 26 S26 25 S25 24 S24 23 S23 22 S22 21 S21 20 S20 19 S19 18 S18 17 S17 16 S16
1 S1(EP1)
2 S2(EP2)
3 S3(EP3)
4 S4(EP4)
5 S5
6 S6
7 S7
8 S8
9 S9
10 S10
11 S11
12 S12
13 S13
14 S14
15 S15
Fig.1
2
Standard ICs
BU9768AK / BU9768AKV
*Pin descriptions
Pin No. Pin name I/O Function Output pins for switching between segment output and expansion pin output. Switched using control codes P0 and P1. When expansion pins are used, these output set data (1 or 0). Segment output pins. These output waveforms correspond to serial data input from DI. Common output pins Output pins for switching between key scan output and segment output. Switching is enabled using control codes K0 and K1. Key scan output pins Key scan input pins Reset input pin for Low Active state. Segment and common outputs are fixed at LOW level while RST is LOW, and all displays disappear. Data for LCD displays is not reset. All data in the key scan buffer is cleared. Internal reference voltage for LCD. When using in the 1 / 2 bias mode, this should be connected to VDD2. Internal reference voltage for LCD. When using in the 1 / 2 bias mode, this should be connected to VDD1. Oscillator pin for segment / common alternating waveforms Key buffer data output pin. After a key scan has been completed, if key input existed, this changes to LOW. Also, if the key data communications command is input, the contents of the key buffer are output as serial data. Since this is open drain output, it should be used with a pull-up resistor. Chip select input pin Synchronous clock input pin for data transmission Data input pin for LCD display Processing if not used 1~4 S1 (EP1) ~ S4 (EP4) O OPEN
5 ~ 40 41 ~ 43 44, 45 46 ~ 49 50 ~ 54
S5 ~ S40 COM1 ~ COM3 KO1 (S41), KO2 (S42) KO3 ~ KO6 KI1 ~ KI5
O O O O I
OPEN OPEN OPEN OPEN OPEN
55
RST
I
VDD
57 58 60
VDD1 VDD2 OSC
-- -- --
-- -- --
61
DO
O
OPEN
62 63 64
CS CK DI
I I I
VSS VSS VSS
*Absolute maximum ratings (Ta = 25C)
Parameter Power supply voltage Input voltage Output voltage Symbol VDD VIN VOUT IOUT (1) Output current IOUT (2) IOUT (3) IOUT (4) Power dissipation BU9768AKV Storage temperature BU9768AK Pd Tstg VDD Pin Limits - 0.3 ~ + 7.0 Unit V V V mA mA RST, OSC, CS, CK, DI, KI1 ~ KI5 - 0.3 ~ VDD + 0.3 OSC, DO, KO1 ~ KO6, EP1 ~ EP4 - 0.3 ~ VDD + 0.3 COM1 ~ COM3 EP1 ~ EP4 S1 ~ S40 KO1 ~ KO6 -- -- 3 5 300 1 800 750 - 55 ~ + 125 C
A
mA mW
This is the maximum voltage which may be applied to the VSS pin.
Reduced by 8.0mW (AK) or 7.5mW (AKV) for each increase in Ta of 1C over 25C.
3
Standard ICs
BU9768AK / BU9768AKV
*Recommended operating conditions (Ta = 25C)
Parameter Power supply voltage Operating temperature Symbol VDD Topr Pin VDD -- Min. + 4.5 - 40 Typ. -- -- Max. + 6.0 + 85 Unit V C
*Electrical characteristics (unless otherwise noted, VDD = 4.5V to 6.0V, Ta = 25C)
Parameter Input high level voltage Input low level voltage Input high level current Input low level current Input floating voltage Pull-down resistance Output off leakage current Symbol VIH (1) VIH (2) VIL (1) VIL (2) IIH IIL VIF RPD IOFFH VOH (1) Output high level voltage VOH (2) VOH (3) VOH (4) VOL (1) Output low level voltage VOL (2) VOL (3) VOL (4) VOL (5) VMID (1) Output intermediate level voltage VMID (2) VMID (3) VMID (4) VMID (5) Power supply current IDD1 IDD2 Pin RST, CS, CK, DI KI1 ~ KI5 RST, CS ,CK, DI KI1 ~ KI5 RST, CS, CK, DI RST, CS, CK, DI KI1 ~ KI5 KI1 ~ KI5 DO KO1 ~ KO6 EP1 ~ EP4 S1 ~ S42 COM1 ~ COM3 KO1 ~ KO6 EP1 ~ EP4 S1 ~ S42 COM1 ~ COM3 DO Min. 0.8VDD 0.6VDD 0 0 -- -- -- 50 -- VDD - 2.0 VDD - 1.5 -- -- 0.5 -- -- -- -- Typ. -- -- -- -- -- -- -- 100 -- VDD - 1.0 -- VDD - 1.0 VDD - 1.0 1.0 -- 1.0 1.0 0.2 (200) -- -- -- -- -- 30 200 Max. VDD VDD 0.2VDD 0.2VDD 6.0 6.0 0.05VDD 200 6.0 VDD - 0.5 -- -- -- 2.0 1.0 -- -- 0.5 (500) 1 / 2VDD + 1.0 2 / 3VDD + 1.0 2 / 3VDD + 1.0 1 / 3VDD + 1.0 1 / 3VDD + 1.0 70 500 Unit V V V V A A V k A V V V V V V V V V V V V V V A A VDD = 5.0V VO = VDD IO = - 1mA IO = - 300A IO = - 20A IO = - 100A IO = 50A IO = 300A IO = 20A IO = 100A IO = 1mA 1 / 2bias 1 / 3bias 1 / 3bias 1 / 3bias 1 / 3bias In sleep mode fOSC = 38kHz V1 = VDD V1 = VSS Conditions
COM1 ~ COM3 1 / 2VDD - 1.0 S1 ~ S42 2 / 3VDD - 1.0
COM1 ~ COM3 2 / 3VDD - 1.0 S1 ~ S42 1 / 3VDD - 1.0
COM1 ~ COM3 1 / 3VDD - 1.0 -- -- -- --
Not designed for radiation resistance.
4
Standard ICs
BU9768AK / BU9768AKV
*AC timing characteristics (VDD = 4.5V to 6.0V, Ta = 25C)
Parameter Rise time Fall time Data setup time Data hold time CS wait time CS setup time CS hold time CK HIGH level time CK LOW level time D0 output delay time Oscillation guaranteed range Symbol tu td ts (1) th (1) tCW ts (2) th (2) tH tL tdl Pin CS, CK, DI CS, CK, DI CK, DI CK, DI CS, CK CS, CK CS, CK CK CK DO Min. -- -- 100 100 100 100 100 100 100 -- Typ. -- -- -- -- -- -- -- -- -- -- Max. 300 300 -- -- -- -- -- -- -- 200 (Note 1) fOSC OSC 19 38 76 kHz (Note 2) Unit ns ns ns ns ns ns ns ns ns ns
(Note 1) Since DO is open drain output, the output delay time varies depending on the pull-up resistance. (Note 2) Values measured for attachments of R = 47k, C = 1000pF.
example *Applicationmode) (1 / 2 bias
LCD panel
C2
R2 OSC S1 (EP1) * * * * * * * * * * * * S40 VDD
R1 RST C1 VDD1 -COM R3 C3 GND CS CK DI DO KI1 VDD2 KO1 KO2 KO3 KO4 KO5 KO6 KI2 KI3 KI4 KI5 COM1 COM2 COM3
R1, C1 : Constants should be set to match data communications. R2 : 47k (fosc = 38kHz) C2 : 1000pF (fosc = 38kHz) C3 : 0.047F R3 : 1k ~ 10k
Key matrix (30 maximum)
The pull-up resistor value should be set to a value so that the waveform is not destroyed by the wiring capacitance or other factors.
5
Fig. 2
Standard ICs
(1 / 3 bias mode)
BU9768AK / BU9768AKV
LCD panel
C2
R2 OSC S1 (EP1) * * * * * * * * * * * * S40 VDD
R1 RST C1 VDD1 -COM R3 C3 C3 GND CS CK DI DO KI1 VDD2 KO1 KO2 KO3 KO4 KO5 KO6 KI2 KI3 KI4 KI5 COM1 COM2 COM3
R1, C1 : Constants should be set to match data communications. R2 : 47k (fosc = 38kHz) C2 : 1000pF (fosc = 38kHz) C3 : 0.047F R3 : 1k ~ 10k
Key matrix (30 maximum)
Fig. 3
(1 / 2 bias mode)
LCD panel
C2
R2 OSC S1 (EP1) * * * * * * * * * * * * S40 VDD
R1 RST R3 C1 VDD1 -COM R4 C3 R3 GND CS CK DI DO KI1 VDD2 KO1 KO2 KO3 KO4 KO5 KO6 KI2 KI3 KI4 KI5 COM1 COM2 COM3
R1, C1 : Constants should be set to match data communications. R2 : 47k (fosc = 38kHz) C2 : 1000pF (fosc = 38kHz) R3 : The constant should be set to match the panel, through testing or other means. C3 : 0.047F R4 : 1k ~ 10k
Key matrix (30 maximum)
Fig. 4
The pull-up resistor value should be set to a value so that the waveform is not destroyed by the wiring capacitance
or other factors.
6
Standard ICs
(1 / 3 bias mode)
BU9768AK / BU9768AKV
LCD panel
C2
R2 OSC S1 (EP1) * * * * * * * * * * * * S40 VDD
R1 RST R3 R3 VDD2 R4 C3 C3 R3 GND CS CK DI DO KI1 KO1 KO2 KO3 KO4 KO5 KO6 KI2 KI3 KI4 KI5 C1 VDD1 -COM COM1 COM2 COM3
R1, C1 : Constants should be set to match data communications. R2 : 47k (fosc = 38kHz) C2 : 1000pF (fosc = 38kHz) R3 : The constant should be set to match the panel, through testing or other means. C3 : 0.047F R4 : 1k ~ 10k
Key matrix (30 maximum)
Fig. 5
The pull-up resistor value should be set to a value so that the waveform is not destroyed by the wiring capacitance
or other factors.
7
Standard ICs
operation *Circuit communications (1) Data
BU9768AK / BU9768AKV
The BU9768AK / BU9768AKV are able to receive LCD display data output from the controller, as well as the results of key scans. 1) LCD display data output (from controller) When LCD data is output, the command code "42" must be output at the beginning of the data. Fig. 6 shows an example of LCD display data output.
CS
CK
LSB DI 0 1 0 0 0 0 1
MSB 0 D1 D2 D3 D4 D5 D6 D7 D8
Command code: 42 1 byte (8 bits)
LCD display data 1 byte (8 bits)
CS
CK
DI
D121
D122
D123
D124
D125
D126
0
0
DP
S0
S1
K0
K1
P0
P1
SC
LCD display data 1 byte (8 bits) A value of 0 LOW must always be input for the 2 bits following D126.
Control code 1 byte (8 bits)
Fig. 6 Example of LCD display data transmission
q During the time that CS is LOW, the command code "42" is input synchronized to the CK clock, and CS is then set to HIGH before the rise of the next CK clock. w The LCD data is sent, and 0 (LOW level) is input for the two bits following D126. e An 8-bit control code is input, and CS is set to LOW.
8
Standard ICs
Segment data correspondence table
COM3 S1 (EP1) S2 (EP2) S3 (EP3) S4 (EP4) S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 D1 (EP1) D4 (EP2) D7 (EP3) D10 (EP4) D13 D16 D19 D22 D25 D28 D31 D34 D37 D40 D43 D46 D49 D52 D55 D58 D61 COM2 D2 D5 D8 D11 D14 D17 D20 D23 D26 D29 D32 D35 D38 D41 D44 D47 D50 D53 D56 D59 D62 COM1 D3 D6 D9 D12 D15 D18 D21 D24 D27 D30 D33 D36 D39 D42 D45 D48 D51 D54 D57 D60 D63 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 KO1 (S41) KO2 (S42) COM3 D64 D67 D70 D73 D76 D79 D82 D85 D88 D91 D94 D97 D100 D103 D106 D109 D112 D115 D118 D121 D124
BU9768AK / BU9768AKV
COM2 D65 D68 D71 D74 D77 D80 D83 D86 D89 D92 D95 D98 D101 D104 D107 D110 D113 D116 D119 D122 D125
COM1 D66 D69 D72 D75 D78 D81 D84 D87 D90 D93 D96 D99 D102 D105 D108 D111 D114 D117 D120 D123 D126
9
Standard ICs
BU9768AK / BU9768AKV
1. If there is an unused segment output If there is segment output that is not used, depending on the panel, the transmission of the LCD display data can be simplified by deciding the pin or pins to be used starting from S40 (S42 if pins 44 and 45 are used as segment output, and S41 if only pin 44 is used as segment output).
CS
CK
LSB DI 0 1 0 0 0 0 1
MSB 0 D25 D26 D27 D28 D29 D30 D31 D32
Command code: 42 1 byte (8 bits)
LCD display data 1 byte (8 bits)
CS
CK
DI
D121
D122
D123
D124
D125
D126
0
0
DP
S0
S1
K0
K1
P0
P1
SC
LCD display data 1 byte (8 bits) A value of 0 LOW must always be input for the 2 bits following D126.
Control code 1 byte (8 bits)
Fig. 7 Simplified data communication
This figure shows an example in which the 30 segment outputs from S11 to S40 are used, and assumes that communication is done in units of eight bits (one byte). For this reason, the data of S9 and S10 (from D25 to D30), which are not used, is input as dummy data. If the unit is not eight bits, this dummy data can be omitted, in which case the data should be input after the command code, starting from the data of D31. However, even if Pins 44 and 45 are used as key scan output and not as segment output, the data for D121 to D126 cannot be omitted. 2. Control codes The BU9768AK is designed to support various applications, depending on the combination of control codes used. * DP: Display mode control Depending on the type of display, either 1 / 2 bias drive or 1 / 3 bias drive may be selected. 1: 1 / 2 bias drive 0: 1 / 3 bias drive * S0 and S1: Sleep mode control In the sleep modes, all displays are turned off, and the oscillation of the OSC pin is stopped, enabling a lower power consumption. In sleep modes, although all of the displays are turned off, key scans are enabled. For information on key scans in the sleep modes, please refer to pages 15 to 22. Various sleep modes can be selected, depending on the application.
10
Standard ICs
Control code S0 0 0 1 1 S1 0 1 0 1 Segment / common output Output OSC pin Key scan output KO1 KO2 KO3 KO4 KO5 KO6 H L L H H L L H H L L H H L H H H H H H
BU9768AK / BU9768AKV
Mode Normal Sleep Sleep Sleep
Oscillating H L L H
Fixed at LOW Stopped Fixed at LOW Stopped Fixed at LOW Stopped
In the Sleep modes, oscillation of the OSC pin stops, but if a button is pressed while the key scan output is on the HIGH line, oscillation begins and a key scan is carried out. When the key scan has been completed, oscillation stops again. * K0, K1: Control that switches between key scan and segment output * P0, P1: Control that switches between segment and expansion pin output The output can be switched to match a variety of applications, depending on the combination of the four bits.
Control code K0 0 0 0 0 0 0 0 0 1 1 1 1 K1 0 0 0 0 1 1 1 P0 0 0 1 1 0 0 1 1 0 0 1 1 P1 0 1 0 1 0 1 0 1 0 1 0 1
Key scan / segment 44pin KO1 KO1 KO1 KO1 S41 S41 S41 S41 S41 S41 S41 S41 45pin KO2 KO2 KO2 KO2 KO2 KO2 KO2 KO2 S42 S42 S42 S42 1pin S1 EP1 EP1 EP1 S1 EP1 EP1 EP1 S1 EP1 EP1 EP1
Segment / expansion pin 2pin S2 EP2 EP2 EP2 S2 EP2 EP2 EP2 S2 EP2 EP2 EP2 3pin S3 S3 EP3 EP3 S3 S3 EP3 EP3 S3 S3 EP3 EP3 4pin S4 S4 S4 EP4 S4 S4 S4 EP4 S4 S4 S4 EP4
Max. no. of display segments 120 114 111 108 123 117 114 111 126 120 117 114
Max. key input 30 30 30 30 25 25 25 25 20 20 20 20
Don't Care
* SC: Control switching the LCD display on and off Switching the LCD display on and off can be done regardless of the input data. 1: Display off 0: Display on (when displayed, displays can be obtained in accordance with the input data.) Note: When the power supply is turned on, the following settings are in effect for control codes. These initial settings for control codes should be changed to match the mode being used. When the power supply is turned on: (DP, S0, S1, K0, K1, P0, P1, SC) = (0, 0, 0, 1, 1, 0, 0, 0)

1
11
Standard ICs
BU9768AK / BU9768AKV
2) Transmission of key data A command code of "43" should be input in order to output the results of a key scan to the BU9768AK / BU9768AKV.
CS
CK
LSB DI 1 1 0 0 0 0 1
MSB 0 Don't Care
Command code: 43 1 byte (8 bits) DO If there is data in the key buffer, DO will be LOW. 32 bits D0 D1 D2 D29 D30 SA
Fig. 8 Transmission of key data
If CS is changed to HIGH level after the command code is input, the data in the key buffer is output synchronized to the rise of CK.
Key data correspondence table
KI1 KO1 (S41) KO2 (S42) KO3 KO4 KO5 KO6 D1 D6 D11 D16 D21 D26 KI2 D2 D7 D12 D17 D22 D27 KI3 D3 D8 D13 D18 D23 D28 KI4 D4 D9 D14 D19 D24 D29 KI5 D5 D10 D15 D20 D25 D30
* The data D0, which is output synchronized to the rise of CS, is unstable and should not be used. * The output SA of the 32nd bit is a state acknowledge signal and outputs the current BU9768AK / BU9768AKV mode. SA: State acknowledge signal In normal modes: SA = LOW In sleep modes : SA = HIGH
12
Standard ICs
(2) Key scan operation With the BU9768AK / BU9768AKV, up to 30 key inputs can be received.
KEY ON 15ms
BU9768AK / BU9768AKV
KO1
KO2 KO3
KO4 When the key scan is completed without problems, DO changes from HIGH to LOW.
KO5
KO6
DO
Fig. 9 Key scan operation
One key scan requires 15ms (if fOSC = 38kHz, 582 / fOSC (sec)). Key scans which are shorter than this time cannot be received. Also, in order to prevent chattering, the key scan waveform (KO output) reaches the HIGH level twice during one key scan. After scanning has been carried out twice, the data from the two scans is compared, and if the data for all of the keys does not match, an error occurs. 1) Key scans and key data communications With the BU9768AK / BU9768AKV, if normal key input is received, DO changes from HIGH to LOW, so if DO is connected to the interrupt input pin of the controller, interrupt processing can be carried out based on the key input. Also, after DO changes to LOW following completion of a key scan, a new key scan cannot be carried out until all of the key data has been read. If multiple keys are pressed at once, multiple key data is set for the various key inputs to be distinguished.
New key scan cannot be carried out until all data has been read. Key scan Key scan
Key1 Key2 Key3 Key scan Key data reading DO Data corresponding to one key scan
Fig. 10 Relationship between key scan and data communications
13
Standard ICs
BU9768AK / BU9768AKV
2) Key scans in sleep modes In sleep modes, depending on the mode, the key scan standby state of the KO pin is restricted.
Standby state in sleep mode
(L) KO1
KEY1
KEY2
KEY3
KEY4
KEY5
(L)KO2
KEY6
KEY7
KEY8
KEY9
KEY10 Enlarged view of one key
(L)KO3
KEY11
KEY12
KEY13
KEY14
KEY15
(L)KO4
KEY16
KEY17
KEY18
KEY19
KEY20
(L)KO5
KEY21
KEY22
KEY23
KEY24
KEY25
Key input received
(H)KO6
KEY26
KEY27
KEY28
KEY29
KEY30
Kl1
Kl2
Kl3
Kl4
Kl5
Fig. 11 Example of key matrix configuration (The diodes installed on each key are to prevent erroneous recognition if multiple keys are pressed.)
The figure above assumes that the control codes S0 and S1 have been set to 0 and 1, respectively. In this case, if any key between key 26 and key 30 is pressed, an HIGH level is input on the KIn line, oscillation begins, and a key scan is carried out. If any key between key 1 and key 25 is pressed, all of the KIn lines remain at LOW level, and no key scan is carried out. Oscillation resumes when the key scan has been completed. If key input in a sleep mode is to be used and interrupt processing carried out, a key on a KOn = HIGH line should be used.
14
Standard ICs
3) Operation flow in a key scan The flow of operations taking place during a key scan is shown below.
BU9768AK / BU9768AKV
Waiting for key input
Has key been input?
No
Yes
Key input (key scan starts)
Was key scan successful?
No
Yes DO LOW
Waiting for input of key data read code
Fig. 12 Key scan flow
The "successful" judgment of the key scan shown in the illustration is based on the data from the two key scans matching for all of the keys, as described on page 13. If an error occurs, the key scan is carried out once again after the first key scan has been completed if a key has remained pressed, and continues to be carried out as long as the key is pressed, until it is successfully completed. After a key scan has been successfully completed, no new key scans can be carried out until reading of the key data has been completed.
15
Standard ICs
(3) Output waveforms 1) 1 / 2 bias mode (frame frequency = fOSC / 384)
1 frame VDD
BU9768AK / BU9768AKV
COM1
1 / 2VDD
VSS VDD
COM2
1 / 2VDD
VSS VDD
COM3
1 / 2VDD
VSS VDD When Sn (D3n-2, D3n-1, D3n) = (0, 0, 0): 1 / 2VDD Out for all COMs
VSS VDD When Sn (D3n-2, D3n-1, D3n) = (0, 0, 1): 1 / 2VDD Lights between COM1 and Sn only
VSS Sn VDD When Sn (D3n-2, D3n-1, D3n) = (1, 0, 1): 1 / 2VDD Out between COM2 and Sn only
VSS VDD When Sn (D3n-2, D3n-1, D3n) = (1, 1, 1): 1 / 2VDD Lights for all COMs
VSS
16
Standard ICs
2) 1 / 3 bias mode (frame frequency = fOSC / 384)
1 frame VDD 2 / 3VDD COM1 1 / 3VDD VSS VDD 2 / 3VDD COM2 1 / 3VDD VSS VDD 2 / 3VDD COM3 1 / 3VDD VSS VDD 2 / 3VDD 1 / 3VDD VSS VDD 2 / 3VDD 1 / 3VDD VSS Sn VDD 2 / 3VDD 1 / 3VDD VSS VDD 2 / 3VDD 1 / 3VDD VSS
BU9768AK / BU9768AKV
When Sn (D3n-2, D3n-1, D3n) = (0, 0, 0): Out for all COMs
When Sn (D3n-2, D3n-1, D3n) = (0, 0, 1): Lights between COM1 and Sn only
When Sn (D3n-2, D3n-1, D3n) = (1, 0, 1): Out between COM2 and Sn only
When Sn (D3n-2, D3n-1, D3n) = (1, 1, 1): Lights for all COMs
17
Standard ICs
BU9768AK / BU9768AKV
(4) RST and display control After the power supply has been turned on, because the internal data of the BU9768AK / BU9768AKV (D1 to D126) is unstable, RST goes LOW at the same time that the power supply is turned on. While RST is LOW, data is transmitted using the microcomputer, and when data transmission has been completed, RST can be set to HIGH to prevent meaningless displays. (For the states of control codes when the power supply is turned on, see page 11.)
VDD
RST VIL t1 t2 CS Display and control data
Internal data
Unstable
Assured
Display
Display t1: Communication time t2: 10s min.
Fig. 13 Communication, display and RST timing
VDD R RST C GND
Fig. 14 Example of RST pin processing
In the circuit example shown above, the value of t1 is determined by the value of the capacitor and resistor. The value should be set in such a way that the constant determined by the capacitor and resistor is the initialized communication time + t2.
18
Standard ICs
BU9768AK / BU9768AKV
*Operation notes with the synchronous clock stopped (1) Using the product
If the synchronous clock is to be stopped during the period that data is not being transmitted, program the product so that the rise of CK is input at least twice after the fall of CS.
CS
CK CK rises at least twice
Fig. 15 When CK is stopped at HIGH
CS
CK CK rises at least twice
Fig. 16 When CK is stopped at LOW
(2) Precautions concerning key scans when the power supply is turned on To carry out a key scan immediately after the power supply is turned on, without transmitting data, the parameters must be set so that the following conditions are met. 1) The rise of the synchronous clock pulse is input to the CK pin at least twice. 2) Since input can only be received from keys on the KO3 to KO6 line, other keys should not be used for functions such as interrupts. (For information on the status when the power supply is turned on, please see page 11.)
If data is being transferred before a key scan is carried out, after the power supply is turned on, these precautions
do not apply.
19
Standard ICs
BU9768AK / BU9768AKV
Make sure of the following when resetting when the power is on. * When using the external reset terminal, make RST = "L" at 1ms or more with VDD at 4.5V or more. * When not using the external reset terminal, VDD has to satisfy the following conditions.
Instruction receipt possible VDD 4.5V tWAIT 1ms VDD < 0.3V 0 < tON < 10ms
*External dimensions (Units: mm)
BU9768AK BU9768AKV
16.4 0.3 14.0 0.2 48 33 16.4 0.3 14.0 0.2 49 32 12.0 0.3 10.0 0.2 49
12.0 0.3 10.0 0.2 48 33 32
64 1 16
17
2.7 0.1
1 0.05
16 0.35 0.1
0.10
0.8
1.4 0.1
0.15 0.1
0.125 0.1
0.5
0.15
0.2 0.1 0.1
QFP-A64
VQFP64
20
0.5
64
17
0.5

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