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MT88V32
8 x 4 High Performance Video Switch Array Preliminary Information
Features
* * * * * * * * * * * 32 bidirectional CMOS "T" switches in an 8x4 non-blocking array Break-before-make switching configuration Fast setup & hold times for switch programming 3dB bandwidth of 200MHz Low feedthrough and crosstalk, better than -80dB at 5MHz Very low differential gain and phase errors 12Vpp bipolar signal capability On-state resistance 75 (max) for V DD=+5V, V EE=-7V Switch control through 2-stage latches Orthogonal Xi and Yi pin connections for optimized PCB layout Latch readback capability for monitoring
ISSUE 1
August 1993
Ordering Information MT88V32AP 44 Pin PLCC -40 to 85C Each of the 32 nodes of the switching matrix has a Tswitch, see Fig.1. This grounds the nodes of all open connections, which greatly reduces feedthrough noise. In order to reduce crosstalk, individual analog signal lines are isolated by interleaving them with ground lines. The two stage programmable latch system allows the state of all switching nodes to be updated simultaneously. The next state of the switch is written into the first stage of the latches through individual write cycles. These changes will not affect the current state of the switch. The STROBE2 control input is used to load the state of all first stage latches to the second stage latches, which updates the complete matrix. Therefore, all 32 switching nodes are updated simultaneously. The MT88V32 supports separate analog (VEE) and digital (V DD) voltage references. This allows the user to select an optimum analog signal bias point.
Applications
* * * * High-end video routing and switching Medical instrumentation Automatic test equipment (ATE) Multi-media communication
Description
The MT88V32 is a digitally programmable (TTL levels) 8x4 crosspoint switch that is designed to control wideband analog (video) signal.
Y0-Y7 VDD VEE VSS X0 X1 X2 X3 Yi STROBE2 2nd Stage Latches I/O Control Logic R/W DATA CS T-Switch Configuration Address Decode GND Xi
GND MR
8x4 "T" Switch Array
STROBE1
1st Stage Latches
AX0-AX1
AY0-AY2
Figure 1 - Functional Block Diagram
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MT88V32
GND Y0 GND GND X0 GND X1 GND X2 GND X3
Preliminary Information
Y1 GND Y2 GND Y3 GND Y4 GND Y5 GND Y6
6 5 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 29 17 18 19 20 21 22 23 24 25 26 27 28 GND Y7 GND VEE IC* VDD VSS AX1 AX0 AY2 NC
GND NC MR STROBE2 STROBE1 R/W CS DATA AY0 AY1 NC
* Connects toVEE
Figure 2 - Pin Connections
Pin Description
Pin #* 1, 3, 4, 6, 8, 10, 12, 14, 16, 18, 20, 39, 41, 43 2, 44, 42, 40 5, 7, 9, 11, 13, 15, 17, 19 21 22 23 24 25, 26 27, 30,31 28, 29 32 Name GND Description Analog Ground. Connect to system ground for crosstalk noise isolation. Pins 3 and 39 are not bonded internally.
X0, X1, X2, X3 Y0, Y1, Y2, Y3 Y4, Y5, Y6, Y7 VEE IC VDD VSS AX1,AX0 AY2-AY0 NC DATA
Analog Lines (input/output). Analog Lines (input/output).
Negative Analog Power Supply. Internal Connection. Positive Power Supply. Digital Ground Reference. X0-X3 I/O Address Select (inputs). Y0-Y7 I/O Address Select (inputs). No Connection. DATA (input/output). When input, a logic high will close the selected switch and a logic low will open the selected switch. When output, a logic high indicates a closed switch and a logic low indicates an opened switch. Chip Select (input). Active low. READ/WRITE Control (input). When high the DATA pin is an output (for reading from second stage latch); when low the DATA pin is an input (for writing to first stage latch).
33 34 35
CS R/W
STROBE1 STROBE 1 (input). Modifies memory content of first stage latch as determined by the addess and data lines, but does not change the switch array configuration of entire switch array. Active low. STROBE2 STROBE 2 (input). Transfers memory content of first stage latch to the second stage latch and hence, changes the configuration of entire switch array. Active low. MR NC MASTER RESET (input). Used to reset the first and second stage latches. Active low. No Connection.
36 37 38
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Preliminary Information
Functional Description
The state of the MT88V32 8 X 4 switching matrix is updated through a simple parallel processor interface. This interface provides access to 32 two stage latches, which determines the state (open/ close) of each switching array node. Each latch (or node) is addressed by the AX0-AX1 and AY0-AY2 inputs as per Table 2, and the DATA input will determine if the connection is to be made (DATA=1) or opened (DATA=0). The second stage of the two stage latches controls the current state of each switching node. The value held in the first stage is the input to the second stage. This allows the device to be programmed in two ways. That is, individual switching nodes may be updated one at a time, or all nodes may be updated at once. To update one node at a time the STROBE2 input should be held low. This makes the second stage latches transparent and the matrix immediately reflects the state of the first stage latches. A write cycle example follows: 1) 2) 3) 4) 5) STROBE2 is low, CS and R/W are low, MR is high, AX0-AX1 and AY0-AY2 as per Table 2, DATA input high to close or low to open, and STROBE1 toggled from high-to-low-to-high.
MT88V32
These steps (one write cycle) may be repeated for each switch state change. This can also be accomplished by holding STROBE1 low and toggling STROBE2. See Figure 14 for timing. To update all nodes simultaneously all switch state changes must be written into the first stage latches. This is accomplished by holding STROBE2 high and performing steps 2) through 5) above for each switching node that is to be changed. Writing to the first stage latches only will not affect the switching state of the matrix. When the changes have been made all the switches of the matrix may be updated simultaneously by toggling the STROBE2 input from high-to-low-to high. When STROBE2 is used to update the state of the MT88V32 all switch "breaks" are completed before any switch "makes" occur. There is approximately 10ns delay between "breaks" and "makes". Both the first and second stage latches will be cleared when the master reset (MR) is taken from high-to-low. This will open all the switch nodes. The operation of MR is independent of CS, AX0-AX1, AY0-AY2 and R/W. The status of each switching array node (second stage latch) can be read through the bidirectional DATA pin. A read cycle example follows: 1) CS is low, R/W and MR are high, 2) AX0-AX1 and AY0-AY2 as per Table 2, and 3) DATA output high for closed or low for open.
STROBE2 DATA
MR
R/W
CS
DATA
STROBE1
1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1
1 0 0 0 0 x x 0 0
0 1 0 1 0 1 1 x x x 0
1 0 1 0 0 0 0 1 1 1 0 x
1 1 1 1 1 1 0 01 0 x
No Change to 1st stage latch. 1st stage latch is loaded with data. 1st stage latch is transparent. Selected latch is cleared and set again (i.e., output follows input). 1st stage latch output is frozen. Output of 1st stage latch is transferred to output of 2nd stage latches. 2nd stage latch output is frozen. Both 1st stage and 2nd stage latches are transparent. DATA becomes an output and reflects the contents of the 2nd stage latch addressed by AX0-AX1 and AY0-AY2. All crosspoints opened (data in 1st and 2nd stage latches are cleared).
0
1
1
1
1
1
Table 1 - Truth Tables
Note: x = don't care, 0 = logic "0" state, 1 = logic "1" state A logic 1 on DATA input closes a connection. A logic 0 on DATA input opens a connection. 3-53
MT88V32
AX1 AX0 AY2 AY1 AY0
Preliminary Information
Switch Connections
0 0 0 0 0 0 0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 0 1 1 0 0 1 1
0 0 0 0 1 1 1 1 0 1 0 1 0 1
0 0 1 1 0 0 1 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
to to to to to to to to
X0 X0 X0 X0 X0 X0 X0 X0
Y0 to X1 Y7 to X1 Y0 to X2 Y7 to X2 Y0 to X3 Y7 to X3
Table 2 - Address Decode Truth Table It should be noted that the STROBE1 function is disabled during a read cycle. See Fig. 15 for timing. The MT88V32 can operate from a dual rail power supply (V DD and V EE) or a single rail power supply (V SS=VEE=0V) as per the recommended operating conditions. For minimum on-state resistance the supply voltages should be VDD=5.0 V DC, V SS=0 V DC and V EE=-7 VDC. The analog input signal should be biased at -2.0 V DC to achieve minimum differential phase and gain error (see AC Electrical Characteristics - Crosspoint Performance). ground (R) should be present between the switches. Selection of R is based on the following compromise: 1) as R is decreased to approach the source and terminating resistance values signal loss will increase and crosstalk will decrease, and 2) as R increases signal loss will decrease and crosstalk will increase. It is recommended that the power supply rails of the MT88V32 be decoupled with 0.1F ceramic Z5U and 10F dipped tantalum capacitors. These capacitors should be as close to the device as possible. The signal pins of the MT88V32 are interleaved with analog ground lines. This allows the circuit designer to run ground tracks on both sides of each signal line to improve crosstalk immunity. The 8x4 bidirectional CMOS T-switch configuration is a modular switching element in a convenient package size. The inherent flexibility of this device permits the designer to build large switching matrices, see analog switch application notes.
A5 A4 A3 A2 A1 A0 D0 Function
Applications
Figure 3 illustrates examples of how to connect the signal lines of the MT88V32 to various interfaces. Input buffers allow the incoming signals to be scaled and biased to the optimum operating range of the MT88V32 (i.e., differential phase error, differential gain error and RON). Buffers will also allow a more precise input impedance to be implemented. For low grade video applications, signal lines may be connected directly, as long as the ultimate source and terminating impedances are matched. Output buffers may be used to provide signal gain and impedance matching for external connections. Additionally, they may be used to isolate parasitic device capacitance in multiple stage switching applications where high frequency roll-off is critical. Crosstalk, as well as differential phase and gain error can be minimized by designing a low source impedance (e.g., 10 ohms), and a high terminating impedance (e.g., 10k) at each stage. If successive switching stages are not buffered, then a resistor to
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0
0
0
0
0
0
1/0
Y0 to X0

0 1 1
1 X X
1 X X
1 X X
1 X X
1 0 1
1/0 X X
Y7 to X3 MR STB2
Table 3 - Address Decoding for the Processor Interfaces
Note: x = undefined, 1/0 -1 = make, 0 = break
Preliminary Information
MT88V32
Wideband Output Buffers 75 10k Wideband Input Buffers 10k 75 75
MT88V32
X0 X1 X2 X3 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 10k
75
75
Wideband Output Buffers
75
10k Control Interface 10k
To next switching stage
10k
R
Figure 3 - High Frequency Switching Applications
Figures 4, 5 and 6 show methods of interfacing the MT88V32 to Motorola and Intel microcontrollers. The address decoding for these configurations is in Table 3. Video Signal Terminology 1) Component Video - separate red (R), blue (B), green (G), and synchronization signals. 2) Composite Video contains luminance (brightness), chrominance (colour), and synchronization signal components in a single waveform. 3) Synchronization signal - horizontal sync pulses are negative going excursions of the composite video signal that occur every 63.5 sec. Their function is to align the horizontal sweep.
Vertical synchronization is achieved during the vertical blanking interval, which is about 1200 sec or 20 horizontal scan intervals long. It consists of a number of vertical synchronization and equalization pulses. 4) Luminance - is the black to white brightness component of a composite video signal. Its range is from reference white (maximum amplitude) to reference black (minimum amplitude). 5) Chrominance - rides on the luminance signal and determines the hue (phase) and brightness (amplitude) of the colour component of a composite video signal. 6) Colour burst - is about 9 (minimum 8) cycles of a 3.578545 MHz reference signal, which is transmitted with every horizontal sweep of the composite video signal. A phase comparison
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MT88V32
MC6800/ 6802/6809 2 VMA
A5 + A0 + VMA 11
Preliminary Information
MT88V32
STB1 STB2
A5-A 15
A0
MR
A5 + A0 + VMA A5 +VMA
CS AY0-AY1 AX0-AX2 DATA R/W
A0-A4 D0 R/W
5
Notes: for the MC6802 2 will be E. for the MC6809 2 will be E and VMA will be the OR'ed product of Q and E.
Figure 4 - Motorola Non-multiplexed Processor Interface
MC6801/ 6803/68HC11 (PC) AD0-AD4
AD0 5
MT88V32
74HCT574 DATA AY0 AY1 AY2 AX0 AX1 CS STB2 D1 D2 D3 D4 D5 D6 D7 D8 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
AD0
3
(PC) AD5-AD7
A5 A5 + A0
(PB) A8-A15 AS E
8
CLK OC
A5 + A0
MR STB1 R/W
R/W
Figure 5 - Motorola Multiplexed Processor Interface
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Preliminary Information
MT88V32
8031/8051 8085 (P0) AD0-AD4
AD0 5
MT88V32
74HCT574 DATA AY0 AY1 AY2 AX0 AX1 CS STB2 D1 D2 D3 D4 D5 D6 D7 D8 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
AD0
3
(P0) AD5-AD7
A5 A5 + A0
(P2) A8-A15 ALE
8
CLK OC
A5 + A0
MR WR STB1 R/W
RD
Figure 6 - Intel Processor Interface
Figure 7 - Typical On-state Resistance (R ON) vs. DC Bias (Vdc) @ VDD=+5V, V EE=-7V
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MT88V32
Preliminary Information
Figure 8 - Single Channel Feedthrough (all crosspoints open)
Figure 9 - Single Channel Crosstalk (one crosspoint closed)
Figure 10 - All Channel Crosstalk (all crosspoints closed)
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Preliminary Information
MT88V32
Figure 11 - 3dB Frequency Response
between this reference signal and chrominance signal determines colour hue.
the
7) Differential Phase Error - (measured in degrees) is a phase change in the chrominance signal due to a change in luminance amplitude. 8) Differential Gain Error - (measured in percentage) is a change in amplitude of the chrominance signal due to a change in luminance amplitude.
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MT88V32
Preliminary Information
Figure 12 - Typical Differential Phase vs. Ramp Voltage
Figure 13 - Typical Differential Gain vs. Ramp Voltage
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Preliminary Information
Absolute Maximum Ratings*- Voltages are with respect to VSS unless otherwise stated.
Parameter 1 Supply Voltage VDD to VSS VDD to VEE VSS to VEE GND to VSS VIN VIND Symbol Min -0.3 -0.3 -0.3 VEE -0.3 VEE-0.3 VSS-0.3 -65 -40
MT88V32
Max 15 15 15 VDD+0.3 VDD+0.3 VDD+0.3 15 +150 +85 600 Units V V V V V V mA C C mW
2 3 4 5 6 7
Analog Input Voltage Digital Input Voltage Continuous Current (any analog I/O terminal) Storage Temperature Operating Temperature Package Power Dissipation
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to 0V unless otherwise stated.
Characteristics 1 Supply Voltage VDD-VEE VEE-VSS VDD VEE 2 3 4 Analog Input Voltage Digital Input Voltage Analog Ground VIN VIND GND Sym Min 4.5 -8.5 4.5 -8.5 VEE VSS VEE 0 Typ 12 5.0 -7.0 Max 13.2 0 13.2 0 VDD VDD VDD Units V V V V V V V Test Conditions
VEE=VSS=0V VDD=4.5V, VSS=0V
DC Electrical Characteristics- Analog Switch Characteristics
Voltages are with respect to VDD=+5V, VEE =-7V, VSS=0V unless otherwise stated.
25C Characteristics 1 On-state Resistance VEE=-7V VEE=-5V VEE=0V 2 3 4 Difference in on-state resistance between switches Off-state leakage current On-state leakage current RON IOFF ION Sym RON 50 60 140 6 10 10 65 75 185 10 Typ Max
85C Max 75 85 220 10 200 200 Units nA nA
Test Conditions VIN=VDC=(VDD+VEE)/2 IVXi-VYjI = 0.4V See Figure 7. IVXi-VYjI = 0.4V VIN=VDC=(VDD+VEE)/2 VIN=VDD or VEE VIN=VDD or VEE
DC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
DC Electrical Characteristics- Power Supplies - Voltages are with respect to VDD=+5V, VEE =-7V, VSS=0V,
MR = 0.8V unless otherwise stated.
Characteristics 1 Positive Supply Current
Sym IDD
Min
Typ 1 0.4 5 1 1 1
Max 100 1.5 15 100 100 100
Units A mA mA A A A
Test Conditions VIND=VDD or VSS VIND=2.4V VDD=12V, VSS=VEE=0V, VIND=3.4V VIND=VDD or VSS VIND=2.4V VDD=12V, VSS=VEE=0V, VIND=3.4V
2
Negative Supply Current
IEE
DC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing. 3-61
MT88V32
DC Electrical Characteristics - Digital Input/Output
Voltages are with respect to VDD=5V, VEE=-7V, VSS=0V, unless otherwise stated.
Preliminary Information
Characteristics 1 2 3 4 5 6 7 Input logic "1" level Input logic "0" level Input leakage (digital pins) Data output high voltage Data output high current Data output low voltage Data output low current
Sym VIH VIH VIL VIL ILEAK VOH IOH VOL IOL
Min 2 3.3
Typ
Max
Units V V
Test Conditions
VEE=VSS=0, VDD=12V VEE=VSS=0, VDD=12V VIND=VDD or VSS IOH=7mA@VOH=2.4V source VOH=2.4V IOL=2mA@VOL=0.4V sink VOL=0.4V
0.8 0.8 1 2.4 7 VSS 2 5 20 0.4 10 VDD
V V A V mA V mA
1 10 A VO=0 to VDD 8 Data high impedance leakage IOZ DC Electrical Characteristics are over recommended temperature range and recommended power supply voltages. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing. Algebraic convention is adopted in this data sheet where the most negative value is a minimum and the most positive value is a maximum.
AC Electrical Characteristics - Crosspoint Performance- Voltages are with respect to VDD=+5V, VDC=0,
VEE=-7V, VSS=0V, unlesss otherwise stated. Also applicable for VEE=VSS=0, VDD=+12V, VDC =(VDD+VEE)/2.
Characteristics 1 2 3 4 5 6 On-state Xi capacitanceQ On-state Yi capacitanceR Off-state Xi capacitanceR Off-state Yi capacitanceR Break-before-Make interval Single channel feedthrough (all crosspoints open) (see Fig. 8) Single channel feedthrough (all crosspoints closed) (See Fig. 9)
Sym CXi (on) CYi (on) CXi (off) CYi (off) topen FDT
Min
Typ
Max 56 56 30 15
Units pF pF pF pF ns dB dB dB dB dB dB dB
Test Conditions 1 Xi to 1 Yi 1 Yi to 1 Xi
10 -80 -62
RS= RL=75 VIN=0.6Vpp @ 5MHz VIN=0.6Vpp @ 15MHz RIN= 10, RL= 10k VIN=0.6Vpp @ 5MHz VIN=0.6Vpp @ 15MHz RIN= 75, RL= 10k VIN=0.6Vpp @ 5MHz VIN=0.6Vpp @ 15MHz RIN= 10, RL= 10k VIN=0.6Vpp @ 5MHz RS= RL=50 See NoteQ, RS= 50, RL= 75 See NoteQ, RS= 50, RL= 75
7
Xtalk (sc) Xtalk (sc)
-85 -68 -70 -50 -55
8
All channel crosstalk (all crosspoints closed) (See Fig. 10) Frequency Response (see Fig.11) Differential Phase Error Differential Gain Error
Xtalk (ac) f3dB DP DG
9 10 11
200 0.05 0.11
MHz
o
%
Timing is over recommended temperature range. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing. Notes: Valid for VEE=-7V, VDD=+5V and VDC=-2.0V. Error will increase slightly if input is biased differently. Input test signal: 700mV ramp biased @ -2.0Vdc with a superimposed video signal of 285Vrms @ 3.58 MHz. Guaranteed by design and characterization and not subject to production testing.
Q R
3-62
Preliminary Information
MT88V32
VEE=-7V,
AC Electrical Characteristics - Timing Characteristics- Voltages are with respect to VDD=+5V,
VSS=0V, RL=1k, CL=50pF unlesss otherwise stated. Also applicable for VEE=VSS=0, VDD =+12V.
Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 DATA to STROBE1 setup DATA to STROBE1 hold CS to STROBE1 setup CS to STROBE1 hold ADDRESS to STROBE1 setup ADDRESS to STROBE1 hold STROBE1 pulse width STROBE2 pulse width R/W to STROBE1 setup R/W to STROBE1 hold RESET pulse width CS to High Z CS to DATA output valid STROBE2 to STROBE1 setup STROBE1 to STROBE2 setup MR to switch OPEN delay 50% MR to10% Output R/W to DATA output valid Address to DATA output valid R/W to High Z Address to High Z STROBE2 to switch status delay 50% strobe to10% output change tstrobe2(on) tstrobe2(off)
Sym tds1 tdh1 tcss1 tcsh1 tass1 tash1 tspw1 tspw2 trwss1 trwsh1 trpw trpw tcsov ts2s1 ts1s2 trst trwov taov trwz taz
Min 20 10 20 20 20 20 75 75 20 10 75 10
Typ
Max
Units ns ns ns ns ns ns ns ns ns ns ns ns
Test Conditions
200 0 0 300 150 200 10 10
ns ns ns ns ns ns ns ns
tson tsoff
100 100
300 300
ns ns
Timing is over recommended temperature range with VIH=5V, VIL=0V, VOH=2.4V, VOL=0.8V, RL=3k (DATA) and RL=1k (analog). Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
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MT88V32
CS
Preliminary Information
trpw MR tcss1 tspw1 tcsh1
STROBE1 tass1 tash1
ADDRESS
DATA tds1 trwss1 R/W ts2s1 STROBE2 tspw2 on SWITCH STATUS off tson tsoff trst ts1s2 tdh1 trwsh1
Figure 14 - Write Cycle Timing Diagram
tcsov CS trwov trwz
R/W
taov
taz
ADDRESS tcsz DATA
High Z Data Valid High Z
Note: STROBE1 is disabled when R/W is at logic "1".
Figure 15 - Read Cycle Timing Diagram
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