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ASAHI KASEI
[AK4112B]
AK4112B
High Feature 96kHz 24bit DIR
GENERAL DESCRIPTION The AK4112B is a digital audio receiver (DIR) compatible with 96kHz, 24bits. The channel status decoding supports both consumer and professional modes. The AK4112B can automatically detect a Non-PCM bit stream. When combined with an AK4527B multi channel codec, the two chips provide a system solution for AC-3 applications. The dedicated pins or a serial P I/F can control the mode setting. The small package, 28pin VSOP saves the board space. *AC-3 is a trademark of Dolby Laboratories. FEATURES Supports AES/EBU, IEC958, S/PDIF, EIAJ CP1201 Low jitter Analog PLL PLL Lock Range: 22k~108kHz Clock Source: PLL or X'tal 4 channel Receivers input and 1 through transmission output Auxiliary digital input De-emphasis for 32kHz, 44.1kHz, 48kHz and 96kHz Dedicated Detect Pins - Non-PCM Bit Stream Detect Pin - Validity Flag Detect Pin - 96kHz Sampling Detect Pin - Unlock & Parity Error Detect Pin Supports up to 24bit Audio Data Format Audio I/F: Master or Slave Mode 32bits Channel Status Buffer Burst Preamble bit Pc, Pd Buffer for Non-PCM bit stream Serial P I/F Two Master Clock Outputs: 128fs/256fs/512fs Operating Voltage: 2.7 to 3.6V with 5V tolerance Small Package: 28pin VSOP Ta: -40~85C
MS0078-E-02 -1-
2004/04
ASAHI KASEI
[AK4112B]
AVSS
AVDD
R
MCKO1
MCKO2
XTI
XTO
RX1 RX2 RX3 RX4 Input Selector
Clock Recovery
Clock Generator
X'tal Oscillator
96kHz Detect V/TX DAIF DEM DVDD DVSS Decoder Audio I/F
FS96 DAUX LRCK BICK SDTO
TVDD System PDN Control AC-3/MPEG Detect Error Detect p I/F CSN CCLK CDTO CDTI
AUTO
ERF
P/S="L"
Serial Control Mode
AVSS AVDD R MCKO1 MCKO2 XTI XTO
RX1
Clock Recovery
Clock Generator
X'tal Oscillator
96kHz Detect
FS96 DAUX LRCK
V DVDD DVSS OCKS0 OCKS1 CM0 CM1 PDN Control System
DAIF DEM Decoder Audio 4 I/F
BICK SDTO DIF0 DIF1 DIF2 TVDD OCKS0
AC-3/MPEG Detect
Error Detect
OCKS1 CM0 CM1
AUTO
ERF
P/S="H"
Parallel Control Mode
MS0078-E-02 -2-
2004/04
ASAHI KASEI
[AK4112B]
Ordering Guide
AK4112BVF -40 ~ +85 C 28pin VSOP (0.65mm pitch)
Pin Layout
DVDD DVSS TVDD V/TX XTI XTO PDN R AVDD AVSS RX1 RX2/DIF0 RX3/DIF1 RX4/DIF2
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24
CM0/CDTO CM1/CDTI OCKS1/CCLK OCKS0/CSN MCKO1 MCKO2 DAUX BICK SDTO LRCK ERF FS96 P/SN AUTO
Top View
23 22 21 20 19 18 17 16 15
MS0078-E-02 -3-
2004/04
ASAHI KASEI
[AK4112B]
PIN/FUNCTION
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Name DVDD DVSS TVDD V TX XTI XTO PDN R AVDD AVSS RX1 DIF0 RX2 DIF1 RX3 DIF2 RX4 AUTO P/S FS96 ERF LRCK SDTO BICK DAUX MCK02 MCK01 OCKS0 CSN OCKS1 CCLK CM1 CDTI CM0 I/O O O I O I I I I I I I I O I O O I/O O I/O I O O I I I I I I I Function Digital Power Supply Pin, 3.3V Digital Ground Pin Input Buffer Power Supply Pin, 3.3V or 5V Validity Flag Output Pin in Parallel Mode Transmit channel (through data) Output Pin in Serial Mode X'tal Input Pin X'tal Output Pin Power-Down Mode Pin When "L", the AK4112B is powered-down and reset. External Resistor Pin 18k +/-1% resistor to AVSS externally. Analog Power Supply Pin Analog Ground Pin Receiver Channel 1 This channel is selected in Parallel Mode or default of Serial Mode. Audio Data Interface Format 0 Pin in Parallel Mode Receiver Channel 2 in Serial Mode Audio Data Interface Format 1 Pin in Parallel Mode Receiver Channel 3 in Serial Mode Audio Data Interface Format 2 Pin in Parallel Mode Receiver Channel 4 in Serial Mode Non-PCM Detect Pin "L": No detect, "H": Detect Parallel/Serial Select Pin "L": Serial Mode, "H": Parallel Mode 96kHz Sampling Detect Pin (RX Mode) "H": fs=88.2kHz or more, "L": fs=54kHz or less. (X'tal Mode) "H": XFS96=1, "L": XFS96=0. Unlock & Parity Error Output Pin "L": No Error, "H": Error Output Channel Clock Pin Audio Serial Data Output Pin Audio Serial Data Clock Pin Auxiliary Audio Data Input Pin Master Clock #2 Output Pin Master Clock #1 Output Pin Output Clock Select 0 Pin in Parallel Mode Chip Select Pin in Serial Mode Output Clock Select 1 Pin in Parallel Mode Control Data Clock Pin in Serial Mode Master Clock Operation Mode Pin0 in Parallel Mode Control Data Input Pin in Serial Mode Master Clock Operation Mode Pin1 in Parallel Mode
CDTO O Control Data Output Pin in Serial Mode Note 1: All input pins except internal pull-down pins should not be left floating.
MS0078-E-02 -4-
2004/04
ASAHI KASEI
[AK4112B]
ABSOLUTE MAXIMUM RATINGS
(AVSS, DVSS=0V; Note 2) Parameter Power Supplies: Analog Digital Input Buffer |AVSS-DVSS| (Note 3) Input Current, Any Pin Except Supplies Input Voltage (Except XTI pin) Input Voltage (XTI pin) Symbol AVDD DVDD TVDD GND IIN VIN VINX min -0.3 -0.3 -0.3 -0.3 -0.3 max 4.6 4.6 6.0 0.3 10 TVDD+0.3 DVDD+0.3 Units V V V V mA V V C C
Ambient Temperature (power applied) Ta -40 85 Storage Temperature Tstg -65 150 Note 2: All voltages with respect to ground. Note 3: AVSS and DVSS must be connected to the same ground. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, DVSS=0V;Note 2) Parameter Analog Digital Input Buffer Note 2: All voltages with respect to ground. Power Supplies: Symbol AVDD DVDD TVDD min 2.7 2.7 DVDD typ 3.3 3.3 3.3 max 3.6 AVDD 5.5 Units V V V
S/PDIF RECEIVER CHARACTERISTICS
(Ta=25C; AVDD, DVDD=2.7~3.6V;TVDD=2.7~5.5V) Parameter Input Resistance Input Voltage Input Hysteresis Input Sample Frequency Symbol Zin VTH VHY fs 350 22 min typ 10 130 max Units k mVpp mV kHz
108
DC CHARACTERISTICS
(Ta=25C; AVDD, DVDD=2.7~3.6V;TVDD=2.7~5.5V; unless otherwise specified) Parameter Symbol min typ 20 10 max 40 100 TVDD DVDD 30%DVDD 0.4 10 Units mA A V V V V V A Power Supply Current Normal operation : PDN = "H" (Note 4) Power down: PDN = "L" (Note 5) High-Level Input Voltage (Except XTI pin) VIH 70%DVDD High-Level Input Voltage (XTI pin) VIH 70%DVDD Low-Level Input Voltage VIL DVSS-0.3 High-Level Output Voltage (Iout=-400A) VOH DVDD-0.4 Low-Level Output Voltage (Iout=400A) VOL Input Leakage Current Iin Note 4: AVDD, DVDD=3.3V, TVDD=5.0V, CL=20pF, fs=96kHz, X'tal=12.288MHz, Clock Operation Mode 2, OCKS1=1, OCKS0=0. AVDD=8mA(typ), DVDD=12mA(typ), TVDD=10A(typ) Note 5: RX inputs are open and all digital input pins are held DVDD or DVSS.
MS0078-E-02 -5-
2004/04
ASAHI KASEI
[AK4112B]
SWITCHING CHARACTERISTICS
(Ta=25C; DVDD, AVDD2.7~3.6V, TVDD=2.7~5.5V; CL=20pF) Parameter Master Clock Timing Crystal Resonator External Clock MCKO1 Output MCKO2 output Frequency Frequency Duty Frequency Duty Frequency Duty fXTAL fECLK dECLK fMCK1 dMCK1 fMCK2 dMCK2 fpll fs dLCK 11.2896 11.2896 40 5.632 40 2.816 40 22 22 45 50 50 50 48 24.576 24.576 60 27.648 60 27.648 60 108 108 55 MHz MHz % MHz % MHz % kHz kHz % Symbol min typ max Units
PLL Clock Recover Frequency (RX1-4) LRCK Frequency Duty Cycle Audio Interface Timing Slave Mode BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK "" (Note 6) BICK "" to LRCK Edge (Note 6) LRCK to SDTO (MSB) BICK "" to SDTO DAUX Hold Time DAUX Setup Time Master Mode BICK Frequency BICK Duty BICK "" to LRCK BICK "" to SDTO DAUX Hold Time DAUX Setup Time Control Interface Timing CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN "H" Time CSN "" to CCLK "" CCLK "" to CSN "" CDTO Delay CSN "" to CDTO Hi-Z
tBCK tBCKL tBCKH tLRB tBLR tLRM tBSD tDXH tDXS fBCK dBCK tMBLR tBSD tDXH tDXS tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH tDCD tCCZ
140 60 60 30 30 35 35 20 20 64fs 50 -20 20 20 200 80 80 50 50 150 50 50 45 70 20 40
ns ns ns ns ns ns ns ns ns Hz % ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Reset Timing PDN Pulse Width tPW 150 Note 6: BICK rising edge must not occur at the same time as LRCK edge.
MS0078-E-02 -6-
2004/04
ASAHI KASEI
[AK4112B]
Timing Diagram
LRCK 50%DVDD
tBLR
tLRB
tBCKL
tBCKH
BICK
50%DVDD
tLRM
tBSD 50%DVDD
SDTO tDXS tDXH
DAUX
50%DVDD
Serial Interface Timing (Slave Mode)
LRCK
50%DVDD
tMBLR BICK 50%DVDD
tBSD 50%DVDD
SDATA tDXS tDXH
DAUX
50%DVDD
Serial Interface Timing (Master Mode)
CSN tCSS tCCKL tCCKH CCLK tCDH
50%DVDD
50%DVDD
tCDS
CDTI
C0
C0
R/W
A4
50%DVDD
CDTO
Hi-Z
WRITE/READ Command Input Timing
MS0078-E-02 -7-
2004/04
ASAHI KASEI
[AK4112B]
tCSW 50%DVDD
CSN tCSH
CCLK
50%DVDD
CDTI
D3
D2
D1
D0
50%DVDD
CDTO
Hi-Z
WRITE Data Input Timing
CSN 50%DVDD
CCLK
50%DVDD
CDTI
A1
A0
50%DVDD
tDCD CDTO Hi-Z D7 D6 D5 50%DVDD
READ Data Output Timing 1
tCSW CSN 50%DVDD
tCSH CCLK 50%DVDD
CDTI
50%DVDD
tCCZ CDTO D3 D2 D1 D0 50%DVDD
READ Data Input Timing 2
tPW PDN
30%DVDD
Power Down & Reset Timing
MS0078-E-02 -8-
2004/04
ASAHI KASEI
[AK4112B]
OPERATION OVERVIEW Non-PCM (AC-3, MPEG, etc.) Stream Detect
The AK4112B has a Non-PCM steam auto detect function. When the 32bit mode Non-PCM preamble based on Dolby "AC-3 Data Stream in IEC958 Interface" is detected, the AUTO goes "H". The 96bit sync code consists of 0x0000, 0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F. Detection of this pattern will set the AUTO "H". Once the AUTO is set "H", it will remain "H" until 4096 frames pass through the chip without additional sync pattern being detected. When those preambles are detected, the burst preambles Pc and Pd that follow those sync codes are stored to registers 0DH-10H.
Clock Recovery and 96kHz Detect
On chip low jitter PLL has a wide lock range with 22kHz to 108kHz and the lock time is less than 20ms. The 96kHz detect output pin FS96 goes "H" when the sampling rate is 88.2kHz or more and "L" at 54kHz or less. In X'tal Mode, the FS96 pin outputs the value which is set by XFS96. PLL loses lock when the received sync interval is incorrect.
Master Clock
The AK4112B has two clock outputs, MCKO1 and MCKO2. These clocks are derived from either the recovered clock or from the X'tal oscillator. The frequencies of the master clock outputs (MCKO1 & MCKO2) are set by OCKS0 and OCKS1 as shown in Table 1. 96kHz sampling is not supported at No.2. No. 0 1 2 3 OCKS1 0 0 1 1 OCKS0 0 1 0 1 MCKO1 256fs 256fs 512fs MCKO2 256fs 128fs 256fs X'tal 256fs 256fs 512fs Test Mode fs (kHz) 32, 44.1, 48, 96 32, 44.1, 48, 96 32, 44.1, 48
Default
Table 1. Master clock frequencies select
Clock Operation Mode
The CM0 and CM1 select the clock source of MCKO1/2 and the data source of SDTO via the dedicated pins or the control register. In Mode 2, the clock source is switched from PLL to X'tal when PLL goes unlock state. In Mode3, the clock source is fixed to X'tal, but PLL is also operating and the recovered data such as C bits can be monitored. Mode 0 1 2 3 CM1 0 0 1 1 CM0 0 1 0 1 UNLOCK 0 1 PLL ON OFF X'tal OFF ON Clock source PLL X'tal FS96 RFS96 XFS96 SDTO RX DAUX RX DAUX DAUX Default
ON ON PLL RFS96 XFS96 ON ON X'tal ON ON X'tal XFS96 ON: Oscillation (Power-up), OFF: STOP (Power-down) Table 2. Clock Operation Mode select
MS0078-E-02 -9-
2004/04
ASAHI KASEI
[AK4112B]
Clock Source
The following circuits are available to feed the clock to XTI pin (#5 pin) of AK4112B. 1) X'tal
XTI
XTO
AK4112B
Note: External capacitance depends on the crystal oscillator (Typ. 10-40pF)
2) External clock
XTI External Clock
XTO
AK4112B
Note: Input clock must not exceed DVDD.
3) Fixed to the Clock Operation Mode 0
XTI
XTO
AK4112B
MS0078-E-02 - 10 -
2004/04
ASAHI KASEI
[AK4112B]
Sampling Frequency and Pre-emphasis Detect
The AK4112B outputs the encoded information of sampling frequency and pre-emphasis in channel status to FS0, FS1 and PEM bits in control register. These information are output from channel 1 at default. It can be switched to channel 2 by CS12 bit in control register.
FS1 0 0 1 1
FS0 0 1 0 1
fs 44.1kHz Reserved 48kHz 32kHz
Byte 3 Bits 0-3 0000 all others 0100 1100
Table 3. fs information in Consumer Mode
FS1 0 0 1 1
FS0 0 1 0 1
fs 44.1kHz Reserved 48kHz 32kHz
Byte 0 Bits 6-7 10 00 01 11
Table 4. fs information in Profession Mode
PEM 0 1
Pre-emphasis OFF ON
Byte 0 Bits 3-5 0X100 0X100
Table 5. PEM in Consumer Mode
PEM 0 1
Pre-emphasis OFF ON
Byte 0 Bits 2-4 110 110
Table 6. PEM in professional Mode
MS0078-E-02 - 11 -
2004/04
ASAHI KASEI
[AK4112B]
De-emphasis Filter Control
The AK4112B includes the digital de-emphasis filter (tc=50/15s) by IIR filter corresponding to four sampling frequencies (32kHz, 44.1kHz, 48kHz and 96kHz). When DEAU bit="1", the de-emphasis filter is enabled automatically by sampling frequency and pre-emphasis information in the channel status. The AK4112B goes this mode at default. Therefore, in Parallel Mode, the AK4112B is always placed in this mode and the de-emphasis filter is controlled by the status bits in channel 1. In Serial Mode, DEM0/1 and DFS bits can control the de-emphasis filter when DEAU is "0". When the "0" data is input to the de-emphasis filter, the output data will be "0" or "-1". The internal de-empahsis filter is bypassed and the recovered data is output without any change if either pre-emphasis or de-emphasis Mode is OFF.
FS96 0 0 0 0 1 1 1 1
FS1 0 0 1 1 0 0 1 1
FS0 0 1 0 1 0 1 0 1
Mode 44.1kHz OFF 48kHz 32kHz OFF OFF 96kHz OFF
Table 7. De-emphasis Auto Control at DEAU="1" and PEM="1"
DFS 0 0 0 0 1 1 1 1
DEM1 0 0 1 1 0 0 1 1
DEM0 0 1 0 1 0 1 0 1
Mode 44.1kHz OFF 48kHz 32kHz OFF OFF 96kHz OFF Default
Table 8. De-emphasis Manual Control at DEAU="0" and PEM="1"
MS0078-E-02 - 12 -
2004/04
ASAHI KASEI
[AK4112B]
System Reset and Power-Down
The AK4112B has a power-down mode for all circuits by PDN pin can be partially powerd-down by PWN bit. The RSTN bit initializes the register and resets the internal timing. In Parallel Mode, only the control by PDN pin is enabled. The AK4112B should be reset once by bringing PDN pin = "L" upon power-up. PDN Pin (Pin #7): All analog and digital circuit are placed in the power-down and reset mode by bringing PDN= "L". All the registers are initialized, and clocks are stopped. Reading/Witting to the register are disabled. RSTN Bit (Address 00H; D0): All the registers except PWN and RSTN are initialized by bringing RSTN bit = "0". The internal timings are also initialized. Witting to the register is not available except PWN and RSTN. Reading to the register is disabled. PWN Bit (Address 00H; D1): The clock recovery part is initialized by bringing PWN bit = "0". In this case, clocks are stopped. The registers are not initialized and the mode settings are kept. Writing and Reading to the registers are enabled.
Biphase Input and Through Output
Four receiver inputs (RX1-4) are available in Serial Control Mode. Each input includes amplifier corresponding to unbalance mode and can accept the signal of 350mV or more. IPS0-1 selects the receiver channel, and OPS0-1 selects the source of the bit stream driving the transmit channel (TX). The TX output can be stopped by setting TXE bit "0". IPS1 0 0 1 1 IPS0 0 1 0 1 INPUT Data RX1 RX2 RX3 RX4 Default
Table 9. Recovery data select
OPS1 0 0 1 1
OPS0 0 1 0 1
INPUT Data RX1 RX2 RX3 RX4 Default
Table 10. Output data select
MS0078-E-02 - 13 -
2004/04
ASAHI KASEI
[AK4112B]
0.1uF 75 Coax 75 0.47nF
Note
RX
AK4112B
Figure 1. Consumer Input Circuit (Coaxial Input) Note: In case of coaxial input, if a coupling level to this input from the next RX input line pattern exceeds 50mV, there is a possibility to occur an incorrect operation. In this case, it is possible to lower the coupling level by adding this decoupling capacitor.
Optical Receiver Optical Fiber O/E
470 RX
AK4112B
Figure 2. Consumer Input Circuit (Optical Input)
In case of coaxial input, as the input level of RX line is small, in Serial Mode, be careful not to crosstalk among RX input lines. For example, by inserting the shield pattern among them. In Parallel Mode, only one channel input (RX1) is available and RX2-4 change to other pins for audio format control. Those pins must be fixed to "H" or "L". The AK4112B includes the TX output buffer. The output level meets combination 0.5V+/-20% using the external resistor network. The T1 in Figure 3 is a transformer of 1:1.
R1 TX R2 DVSS T1 75 cable
Vdd R1 R2 3.3V 240 150 3.0V 220 150
Figure 3. TX External Resistor Network
MS0078-E-02 - 14 -
2004/04
ASAHI KASEI
[AK4112B]
Error Handling
There are the following five factors which ERF pin goes "H". ERF pin shows the status of the internal PLL operation and it is "L" when the PLL is OFF (Clock Operation Mode 1). 1. Unlock Error 2. Parity Error 3. Biphase Error 4. Frame length Error 5. STC (Status Change) flag="1" : "H" when the PLL goes UNLOCK state. : Updated every sub-frame cycle. : Updated every sub-frame cycle : Updated every sub-frame cycle : Holds "1" until reading 03H.
In Parallel Mode, ERF pin outputs the ORed signal including the factors of 1,2,3 and 4. Once ERF pin goes "H", it maintains "H" for 1024/fs cycles after the all error factors are removed. Table 11 shows the state of each output pins when the ERF pin is "H". The Frame length Error is occurred when the interval of preamble in biphase signal is incorrect. When unlock state, the channel status bits are not updated and the previous data is maintained. Error Unlock Error Parity Error Biphase Error Frame Length Error AUTO "L" Output Output Output SDTO "L" Previous Data Previous Data Previous Data V "L" Output Output Output
Table 11. Error handling (Parallel Mode) In Serial Mode, ERF pin outputs the ORed signal including the factors of 1,2,3,4 and 5. However, Parity, Biphase and Frame Length Error can be masked by MPAR bit, and the STC flag can be masked by MSTC bit. When those are masked by each bit, the error factor does not affect ERF pin operation. The STC flag is set whenever a comparison between the last sample of bits D5-0 of the receiver status 1 register (03H) and the new sample are different This comparison is made every fs cycle. The STC flag is reset by reading the register 03H. This flag is also disabled during the first block after reset. Once ERF pin goes "H", it maintains "H" for 1024/fs cycles (can be changed by ERFH0-1 bits) after the all error factors (In case of STC, from STC flag "1" to reading 03H) are removed. Once PAR, BIP, FRERR, V or UNLOCK bit goes "1", it returns "0" by reading Receiver Status 2 (04H). When unlock state, the channel status bits are not updated and the previous data is maintained. Error & Status Unlock Error Parity Error Biphase Error Frame Length Error Status change Register PAR BIP FRERR 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 Pin STC 0 0 0 0 1 AUTO "L" Output Output Output Output SDTO "L" Previous Data Previous Data Previous Data Output V "L" Output Output Output Output TX Output Output Output Output Output
UNLOCK 1 0 0 0 0
Table 12. Error handling (Serial Mode; MPAR=1, MSTC=1)
MS0078-E-02 - 15 -
2004/04
ASAHI KASEI
[AK4112B]
(status change ) (ch. status ) STC bit (state A ) (state B)
Hold "1"
Reset
Command
READ 03H
ERF MCKO, BICK, LRCK SDTO V
ERF Hold Time
ERF pin timing at Status Change
error(UNLOCK, PAR, BIP, FRERR) ERF register (UNOCK, PAR, BIP, FRERR) Command MCKO,BICK,LRCK (UNLOCK) MCKO,BICK,LRCK (except UNLOCK) SDTO(UNLOCK) SDTO (except UNLOCK) Vpin (UNLOCK) Vpin (except UNLOCK)
(error)
ERF Hold Time
Hold "1"
Reset
READ 04H (fs: around 20kHz) Free Run
Previous Data
ERF pin timing at UNLOCK, PAR, BIP, FRERR error MS0078-E-02 - 16 2004/04
ASAHI KASEI
[AK4112B]
PD pin ="L" to "H"
Initialize
Read 03H
STC is reset, ERF pin ="L"
Read 04H
ERF pin ="H"
YES
Mute = "H"
Read 03H Mute="L"
STC is reset, ERF pin ="L"
Read 04H
NO
ERF pin ="H"
YES
Figure 4. Error handling sequence Example
MS0078-E-02 - 17 -
2004/04
ASAHI KASEI
[AK4112B]
Audio Serial Interface Format
The DIF0, DIF1 and DIF2 pins as shown in Table 13 can select eight serial data formats. In all formats the serial data is MSB-first, 2's compliment format. The SDTO is clocked out on the falling edge of BICK and the DAUX is latched on the rising edge of BICK. BICK outputs 64fs clock in Mode 0-5. Mode 6-7 are Slave Modes, and BICK is available up to 128fs at fs=48kHz. In the format equal or less than 20bit (Mode0-2), LSBs in sub-frame are truncated. In Mode 3-7, the last 4LSBs are auxiliary data (see Figure 5). When the Parity Error, Biphase Error or Frame Length Error occurs in a sub-frame, AK4112B continues to output the last normal sub-frame data from SDTO repeatedly until the error is removed. When the Unlock Error occurs, AK4112B output "0" from SDTO. In case of using DAUX pin, the data is transformed and output from SDTO. DAUX pin is used in Clock Operation Mode 1, 3 and unlock state of Mode 2. The input data format to DAUX should be left justified except in Mode5 and 7(Table 13). In Mode5 or 7, both the input data format of DAUX and output data format of SDTO are I2S. Mode6 and 7 are Slave Mode that is corresponding to the Master Mode of Mode4 and 5. In salve Mode, LRCK and BICK should be fed with synchronizing to MCKO1/2. The initial state of the audio format is the Master Mode upon the power-up. Therefore, if the audio format is changed to the Slave Mode after power-up, the setting of the external clocks should be careful until completing to set the control registers.
sub-frame of IEC958
0 preamble 34 Aux. LSB MSB 78 11 12 27 28 29 30 31 VUCP
MSB
LSB
23
0
AK4112B Audio Data (MSB First)
Figure 5. Bit configuration
Mode 0 1 2 3 4 5 6 7
DIF2 0 0 0 0 1 1 1 1
DIF1 0 0 1 1 0 0 1 1
DIF0 0 1 0 1 0 1 0 1
DAUX 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, I2S 24bit, Left justified 24bit, I2S
SDTO 16bit, Right justified 18bit, Right justified 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, I2S 24bit, Left justified 24bit, I2S
LRCK I/O H/L O H/L O H/L O H/L O H/L O L/H O H/L I L/H I
BICK 64fs 64fs 64fs 64fs 64fs 64fs 64-128fs 64-128fs I/O O O O O O O I I
Default
Table 13. Audio data format
MS0078-E-02 - 18 -
2004/04
ASAHI KASEI
[AK4112B]
LRCK(0)
0 1 2 15 16 17 31 0 1 2 15 16 17 31 0 1
BICK (0:64fs)
15 14 1 0 15 14 1 0
SDTO(0)
15:MSB, 0:LSB Lch Data Rch Data
Figure 5. Mode 0 Timing
LRCK(0)
0 1 2 9 10 11 12 31 0 1 2 9 10 11 12 31 0 1
BICK (0:64fs)
23 22 21 20 1 0 23 22 21 20 1 0
SDTO(0)
23:MSB, 0:LSB Lch Data Rch Data
Figure 6. Mode 3 Timing
LRCK
0 1 2 21 22 23 24 31 0 1 2 21 22 23 24 31 0 1
BICK (64fs)
23 22 21 2 1 0 23 22 3 2 1 0 23 22
SDTO(0)
23:MSB, 0:LSB Lch Data Rch Data
Figure 7. Mode 4, 6 Timing
Mode 4: LRCK, BICK: Output Mode 6: LRCK, BICK: Input
LRCK
0 1 2 22 23 24 25 31 0 1 2 21 22 23 24 25 31 0 1
BICK (64fs) SDTO(0)
23 22 21 2 1 0 23 22 3 2 1 0 23
23:MSB, 0:LSB Lch Data Rch Data
Figure 8. Mode 5, 7 Timing
Mode 5: LRCK, BICK: Output Mode 7: LRCK, BICK: Input
MS0078-E-02 - 19 -
2004/04
ASAHI KASEI
[AK4112B]
Serial Control Interface
The internal registers may be either written or read by the 4-wire P interface pins: CSN, CCLK, CDTI & CDTO. The data on this interface consists of Chip address (2bits, C0/1 are fixed to "00"), Read/Write (1bit), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is clocked out on the falling edge. For write operations, data is latched after the 16th rising edge of CCLK, after a high-to-low transition of CSN. For read operations, the CDTO output goes high impedance after a low-to-high transition of CSN. The maximum speed of CCLK is 5MHz. PDN= "L" resets the registers to their default values. When the state of P/S pin is changed, the AK4112B should be reset by PDN= "L".
CSN
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CCLK
CDTI WRITE CDTO CDTI READ CDTO
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
C1-C0: R/W: A4-A0: D7-D0:
Chip Address (Fixed to "00") READ/WRITE (0:READ, 1:WRITE) Register Address Control Data
Figure 10. Control I/F Timing
MS0078-E-02 - 20 -
2004/04
ASAHI KASEI
[AK4112B]
Register Map
Addr Register Name 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H Clock & Power down Control Input/Output Control Format & De-emphasis Control Receiver status 1 Receiver status 2 Channel A Status Byte 0 Channel A Status Byte 1 Channel A Status Byte 2 Channel A Status Byte 3 Channel B Status Byte 0 D7 0 MPAR V/TX ERF CV CA7 CA15 CA23 CA31 CB7 CB15 CB23 CB31 PC7 PC15 PD7 PD15 0 D6 BCU MSTC DIF2 0 STC CA6 CA14 CA22 CA30 CB6 CB14 CB22 CB30 PC6 PC14 PD6 PD14 0 D5 CM1 CS12 DIF1
AUDION
D4 CM0 TXE DIF0 AUTO
UNLOCK
D3 IPS1 DEAU PEM V CA3 CA11 CA19 CA27 CB3 CB11 CB19 CB27 PC3 PC11 PD3 PD11 0
D2 IPS0 DEM1 FS1 FRERR CA2 CA10 CA18 CA26 CB2 CB10 CB18 CB26 PC2 PC10 PD2 PD10 EFH1
D1 PWN OPS1 DEM0 FS0 BIP CA1 CA9 CA17 CA25 CB1 CB9 CB17 CB25 PC1 PC9 PD1 PD9 EFH0
D0 RSTN OPS0 DFS RFS96 PAR CA0 CA8 CA16 CA24 CB0 CB8 CB16 CB24 PC0 PC8 PD0 PD8 XFS96
OCKS1 OCKS0
CRC CA5 CA13 CA21 CA29 CB5 CB13 CB21 CB29 PC5 PC13 PD5 PD13 0
CA4 CA12 CA20 CA28 CB4 CB12 CB20 CB28 PC4 PC12 PD4 PD12 0
0AH Channel B Status Byte 1 0BH Channel B Status Byte 2 0CH Channel B Status Byte 3 0DH Burst Preamble Pc Byte 0 0EH Burst Preamble Pc Byte 1 0FH 10H 11H Burst Preamble Pd Byte 0 Burst Preamble Pd Byte 1 Count Control
Notes: For addresses from 12H to 1FH, data must not be written. When PDN pin goes "L", the registers are initialized to their default values. When RSTN bit goes "0", the internal timing is reset and the registers are initialized to their default values. All data can be written to the register even if PWN bit is "0".
MS0078-E-02 - 21 -
2004/04
ASAHI KASEI
[AK4112B]
Register Definitions Reset & Initialize
Addr 00H Register Name Clock & Power down Control R/W default RSTN: D7 0 RD 0 D6 BCU R/W 0 D5 CM1 R/W 0 D4 CM0 R/W 0 D3 R/W 0 D2 R/W 0 D1 PWN R/W 1 D0 RSTN R/W 1
OCKS1 OCKS0
Timing Reset & Register Initialize 0: Reset & Initialize 1: Normal Operation PWN: Power Down 0: Power down 1: Normal Operation OCKS1-0: Master Clock frequency Select CM1-0: Master Clock Operation Mode Select BCU: Block start & C/U output Mode When BCU=1, the 3 output pins change another function. MCKO2 pin B; block start signal AUTO pin C bit FS96 pin U bit The block signal goes high at the start of frame 0 and remains high until the end of frame 31.
(B, C, U, V output timing at RX mode, Master mode)
B
C (or U,V)
C(R191)
C(L0) 1/4fs
C(R0)
C(L1)
C(L31)
C(R31) C(L32)
LRCK SDTO (I2S) SDTO (except I2S)
L191
R191
L0
R0
R30
L31
R31
R190
L191
R191
L0
L30
R30
L31
MS0078-E-02 - 22 -
2004/04
ASAHI KASEI
[AK4112B]
Input/Output Control
Addr Register Name R/W default D7 MPAR R/W 1 D6 MSTC R/W 0 D5 CS12 R/W 0 D4 TXE R/W 1 D3 IPS1 R/W 0 D2 IPS0 R/W 0 D1 OPS1 R/W 0 D0 OPS0 R/W 0
01H Input/Output Control
OPS1-0: Output Through Data Select IPS1-0: Input Recovery Data Select TXE: TX Output Enable 0: Disable. TX output pin is placed in a high impedance state. 1: Enable CS12: Channel Status Select 0: Channel 1 1: Channel 2 Selects which channel status is used to derive AUDION, PEM, FS1 and FS0. The de-emphasis filter, however, is always controlled by channel 1 in the Parallel Mode. MSTC: Status change flag mask bit This bit is low to mask status change from being reported by ERF. MPAR: Parity mask bit This bit is low to mask Parity Error, Biphase Error and Frame Length Error from being reported by ERF.
Format & De-emphasis Control
Addr Register Name R/W default V/TX: D7 V/TX R/W 0 D6 DIF2 R/W 1 D5 DIF1 R/W 0 D4 DIF0 R/W 0 D3 DEAU R/W 1 D2 DEM1 R/W 0 D1 DEM0 R/W 1 D0 DFS R/W 0
02H Format & De-emphasis Control
V/TX Output Select 0: Validity Flag Output. This output is updated every fs cycle. 1: TX DFS: 96kHz De-emphasis Control DEM1-0: 32, 44.1, 48kHz De-emphasis Control DEAU: De-emphasis Auto Detect Enable 0: Disable 1: Enable DIF2-0: Audio Data Format Control
MS0078-E-02 - 23 -
2004/04
ASAHI KASEI
[AK4112B]
Receiver Status 1
Addr Register Name R/W default RFS96: D7 ERF RD 0 D6 0 RD 0 D5
AUDION
D4 AUTO RD 0
D3 PEM RD 0
D2 FS1 RD 0
D1 FS0 RD 0
D0 RFS96 RD 0
03H Receiver status 1
RD 0
96kHz Sampling Detect at Recovery Mode. 0: fs=54kHz or less. 1: fs=88.2kHz or more FS1-0: Sampling Frequency Output PEM: Pre-emphasis Output 0: OFF 1: ON This bit is made by encoding channel status bits. AUTO: Non-PCM Auto Detect 0: No detect 1: Detect This function is the same as AUTO pin. AUDION: Audio bit Output 0: Audio 1: Non Audio ERF: Unlock or Parity Error or Status change 0: No Error or No change 1: Error or Change This function is the same as ERF pin. This bit goes "1" when Unlock Error, Parity Error, Biphase Error, Frame Length Error or Status Change occurs. If MPAR=0 & MSTC=0, only an unlock error is reported.
Receiver Status 2
Addr Register Name R/W default PAR: D7 CV RD 0 D6 STC RD 0 D5 CRC RD 0 D4
UNLOCK
D3 V RD 0
D2 FRERR RD 0
D1 BIP RD 0
D0 PAR RD 0
04H Receiver status 2
RD 0
Parity Status (0:No Error, 1:Error) It is high if Parity Error is detected in the sub-frame. PAR is unaffected by the state of MPAR. BIP: Biphase Status (0:No Error, 1:Error) FRERR: Frame Error Status (0:No Error, 1:Error) V: Validity bit (0:No Error, 1:Error) UNLOCK: PLL Lock status (0:Lock, 1:Unlock) CRC: Cyclic Redundancy Check (0:No Error, 1:Error on either channel) STC: Status change flag of Receiver status 1 (0:No change, 1:change) This flag goes "H" when the latest value of D5-0 in Receiver Status 1(03H) is different from the previous value. This comparison is made at every fs cycle. This bit returns to "L" by reading Receiver Status 1(03H). The flag is disabled during the first block after Reset. CV: Channel Status Validity (0:Valid, 1:Not Valid, data is updating) This signal goes "H" at the start of frame 0 and maintains "H" until the end of frame 31.
MS0078-E-02 - 24 -
2004/04
ASAHI KASEI
[AK4112B]
Channel Status
Addr Register Name D7 CA7 CA15 CA23 CA31 CB7 CB15 CB23 CB31 D6 CA6 CA14 CA22 CA30 CB6 CB14 CB22 CB30 D5 CA5 CA13 CA21 CA29 CB5 CB13 CB21 CB29 D4 CA4 CA12 CA20 CA28 CB4 CB12 CB20 CB28 RD Not initialized D3 CA3 CA11 CA19 CA27 CB3 CB11 CB19 CB27 D2 CA2 CA10 CA18 CA26 CB2 CB10 CB18 CB26 D1 CA1 CA9 CA17 CA25 CB1 CB9 CB17 CB25 D0 CA0 CA8 CA16 CA24 CB0 CB8 CB16 CB24
05H Channel A Status Byte 0 06H Channel A Status Byte 1 07H Channel A Status Byte 2 08H Channel A Status Byte 3 09H Channel B Status Byte 0 0AH Channel B Status Byte 1 0BH Channel B Status Byte 2 0CH Channel B Status Byte 3 R/W default
CA31-0: Channel A Status Byte 4-1 CB31-0: Channel B Status Byte 4-1 Bit definition changes depending upon PRO bit setting. When CV=1, these bits are updating and may be invalid.
Burst Preamble Pc/Pd in non-PCM encoded Audio bitstreams
Addr Register Name D7 PC7 PC15 PD7 PD15 D6 PC6 PC14 PD6 PD14 D5 PC5 PC13 PD5 PD13 D4 PC4 PC12 PD4 PD12 RD Not initialized D3 PC3 PC11 PD3 PD11 D2 PC2 PC10 PD2 PD10 D1 PC1 PC9 PD1 PD9 D0 PC0 PC8 PD0 PD8
0DH Burst Preamble Pc Byte 0 0EH Burst Preamble Pc Byte 1 0FH Burst Preamble Pd Byte 0 10H Burst Preamble Pd Byte 1 R/W default
PC15-0: Burst Preamble Pc Byte 1, 0 PD15-0: Burst Preamble Pd Byte 1, 0
Count Control
Addr 11H Register Name Count Control R/W default XFS96: D7 0 RD 0 D6 0 RD 0 D5 0 RD 0 D4 0 RD 0 D3 0 RD 0 D2 EFH1 R/W 0 D1 EFH0 R/W 1 D0 XFS96 R/W 0
FS96 output select at X'tal Mode (clock Operation Mode1, Mode3 and Unlock state of Mode2) 1: FS96pin="H" 0: FS96pin="L" EFH1-0: Error Flag Hold Count Select 00: 512 LRCK 01: 1024 LRCK 10: 2048 LRCK 11: 4096 LRCK
MS0078-E-02 - 25 -
2004/04
ASAHI KASEI
[AK4112B]
Burst preambles in non-PCM bitstreams
sub-frame of IEC958
0 preamble 34 Aux. 78 11 12 LSB 27 28 29 30 31 MSB V U C P
16 bits of bitstream
0 15
Pa Pb Pc Pd
Burst_payload
stuffing
repetition time of the burst
Preamble word Pa Pb Pc Pd
Length of field 16 bits 16 bits 16 bits 16 bits
Contents sync word 1 sync word 2 Burst info Length code
value 0xF872 0x4E1F see Table 15. numbers of bits
Table 14. Burst preamble words Bits of Pc 0-4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16-31 0 0 1 value contents data type NULL data Dolby AC-3 data reserved PAUSE MPEG-1 Layer1 data MPEG-1 Layer2 or 3 data or MPEG-2 without extension MPEG-2 data with extension MPEG-2 AAC ADTS MPEG-2, Layer1 Low sample rate MPEG-2, Layer2 or 3 Low sample rate reserved DTS type I DTS type II DTS type III ATRAC ATRAC2/3 reserved reserved, shall be set to "0" error-flag indicating a valid burst_payload error-flag indicating that the burst_payload may contain errors data type dependent info bit stream number, shall be set to "0" Table 15. Fields of burst info Pc repetition time of burst in IEC958 frames
4096 1536
384 1152 1152 1024 384 1152 512 1024 2048 512 1024
5, 6 7
8-12 13-15
0
MS0078-E-02 - 26 -
2004/04
ASAHI KASEI
[AK4112B]
Non-PCM Bitstream timing
1) When Non-PCM preamble is not coming within 4096 frames,
PDN pin
Bit stream
Pa Pb Pc1 Pd1 Repetition time
Pa Pb Pc2 Pd2 >4096 frames
Pa Pb Pc3 Pd3
AUTO
Pc Register
"0"
Pc1
Pc2
Pc3
Pd Register
"0"
Pd1
Pd2
Pd3
2) When Non-PCM bitstream stops
ERF pin <20mS (Lock time) Bit stream Pa Pb Pc1 Pd1 Stop 2~3 Syncs (B,M or W) AUTO Pc Register
Pc0
Pc1
Pcn
Pd Register
Pd0
Pd1
Pdn
MS0078-E-02 - 27 -
2004/04
ASAHI KASEI
[AK4112B]
SYSTEM DESIGN
Figure 11 shows the example of system connection diagram for Serial Mode.
3.3V Supply
10u 0.1u +
1 2
DVDD DVSS TVDD V/TX XTI XTO PDN R AVDD AVSS RX1 RX2 RX3 RX4
CDTO CDTI CCLK CSN
28 27 26 25 24 23 22 21 20 19 18 17 16 15
3.3~5V Supply
+ 10u 3 0.1u C 5 4
Microcontroller
AK4112B
MCKO1 MCKO2 DAUX BICK SDTO LRCK ERF FS96 P/SN AUTO
(Note 8)
C 18k
6 7
3.3V Supply
10u + 0.1u
8 9 10 11
(see Figure 1,2)
12 13 14
DSP and AD/DA
Figure 11. Typical Connection Diagram (Serial Mode)
Notes: - "C" depends on the crystal oscillator (Typ. 10-40pF) - AVSS and DVSS must be connected the same ground plane - Digital signals, especially clocks, should be kept away from the R pin in order to avoid an effect to the clock jitter performance. .
MS0078-E-02 - 28 -
2004/04
ASAHI KASEI
[AK4112B]
PACKAGE
28pin VSOP (Unit: mm)
*9.80.2 0.675 28 15 A 7.60.2 +0.1 0.15-0.05 0.10.1 Detail A 0.50.2 Seating Plane 0.10 NOTE: Dimension "*" does not include mold flash. 0-10
2004/04 - 29 -
1.250.2
1 0.220.1
14 0.65
Material & Lead finish
Package molding compound: Epoxy Lead frame material: Cu Lead frame surface treatment: Solder plate
MS0078-E-02
*5.60.2
ASAHI KASEI
[AK4112B]
MARKING
AKM AK4112BVF
XXXBYYYYC
XXXXBYYYYC: XXXB: YYYYC:
Date code identifier Lot number (X : Digit number, B : Alpha character ) Assembly date (Y : Digit number C : Alpha character)
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
MS0078-E-02 - 30 -
2004/04

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