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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
* The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT594 8-bit shift register with output register
Product specification File under Integrated Circuits, IC06 December 1991
Philips Semiconductors
Product specification
8-bit shift register with output register
FEATURES * Synchronous serial input and output * 8-bit parallel output * Shift and storage register have independent direct clear and clocks * 100 MHz (typ.) * Output capability: - parallel outputs: bus driver - serial outputs: standard * ICC category: MSI APPLICATIONS * Serial-to parallel data conversion * Remote control holding register DESCRIPTION
74HC/HCT594
The 74HC/HCT594 are high-speed, Si-gate CMOS devices, and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74HC/HCT594 contain an 8-bit, non-inverting, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Separate clocks and direct overriding clears are provided on both the shift and storage registers. A serial output (Q7') is provided for cascading purposes. Both the shift and storage register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the shift register will always be one count pulse ahead of the storage register.
QUICK REFERENCE DATA GND = 0 V: Tamb = 250 C; tr = tf = 6 ns. TYPICAL SYMBOL tPHL/tPLH PARAMETER propagation delay SHCP to Q7' STCP to Qn SHR to Qn STR to Qn fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi + (CL x VCC2 x fo), where: fi = input frequency in MHz; fo = output frequency in MHz; (CL x VCC2 x fo) = sum of the outputs; CL = output load capacitance in pF; VCC = supply voltage in V. 2. For HC, the condition is VI = GND to VCC; for HCT, the condition is VI = GND to VCC - 1.5 V. ORDERING INFORMATION PACKAGES EXTENDED TYPE NUMBER PINS PC74HC/HCT594P PC74HC/HCT594T 16 16 PIN POSITION DIL SO MATERIAL plastic plastic CODE SOT38C, P SOT109A maximum clock frequency SHCP, STCP input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 13 13 11 11 100 3.5 84 15 15 14 14 100 3.5 89 ns ns ns ns MHz pF pF HCT UNIT
December 1991
2
Philips Semiconductors
Product specification
8-bit shift register with output register
PINNING SYMBOL Q0 to Q7 GND Q7' SHR SHCP STCP STR Ds VCC 8 9 10 11 12 13 14 16 PIN 15 & 1 to 7 parallel data outputs ground (0 V) serial data output shift register reset (active LOW) shift register clock input storage register clock input storage register reset active (LOW) serial data input supply voltage DESCRIPTION
74HC/HCT594
11
ge
12
ge
halfpage
SH CP ST CP Q7' Q0 Q1 Q2 14 DS Q3 Q4 Q5 Q6 SH R 10 ST R 13 Q7
ST R Q1 1 Q2 2 Q3 3 Q4 4 Q5 5 Q6 6 Q7 7 16 V CC 15 Q 0 14 D S 13 ST R DS ST CP SH R SH CP
13 12 10 11 14 R 1 SRG8 C1/ 1D
R2 C2
9 15 1 2 3 4 5 6 7
2D
594
12 ST CP 11 SH CP 10 SH R 9 Q7'
GND 8
MBC318
15 Q 0 1 Q1 2 Q2 3 Q3 4 Q4 5 Q5 6 Q6 7 Q7 9 Q7'
MBC319
MBC322 - 1
Fig.1 Logic symbol.
Fig.2 Pin configuration.
Fig.3 IEC logic symbol.
December 1991
3
Philips Semiconductors
Product specification
8-bit shift register with output register
74HC/HCT594
handbook, halfpage
14 D S 11 SHCP 8-STAGE SHIFT REGISTER Q7' 12 ST CP 8-BIT STORAGE REGISTER
10 SH R 9
13 ST R
Q 0 Q1 Q 2 Q 3 Q4 Q 5 Q 6 Q 7 15 1 2 3 4 5 6 7
MBC320
Fig.4 Functional diagram.
FUNCTION TABLE INPUTS SHCP X X X STCP X X X SHR L X L H STR X L H X X X X H DS OUTPUTS FUNCTION Q7' L NC L Q6' Qn NC L L NC a LOW level on SHR only affects the shift registers. a LOW level on STR only affects the storage registers. empty shift register loaded into storage register. logic HIGH level shifted into shift register stage 0. Contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal Q6') appears on the serial output (Q7'). contents of shift register stages (internal Qn') are transferred to the storage register and parallel output stages. contents of shift register shifted through. Previous contents of shift register transferred to the storage register and the parallel output stages.
X

H H
H H
X X
NC Q6n
Qn' Qn'
Note 1. H = HIGH voltage level L = LOW voltage level = LOW-to-HIGH transition NC = no change X = don't care.
December 1991
4
Philips Semiconductors
Product specification
8-bit shift register with output register
74HC/HCT594
handbook, full pagewidth
STAGE 0 DS D Q D
STAGES 1 TO 6 Q
STAGE 7 D Q Q7'
FFSH 0 CP R SHCP SH R
FFSH 7 CP R
D
Q
D CP
Q
FFST 0 CP R ST CP ST R
FFST 7 R
Q0
Q 1 Q 2 Q3 Q 4 Q 5 Q6
Q7
MBC321 - 1
Fig.5 Logic diagram.
handbook, full pagewidth SH CP
DS ST CP SH R ST R Q0 Q1
Q6 Q7 Q 7'
MBC323 - 1
Fig.6 Timing diagram.
December 1991
5
Philips Semiconductors
Product specification
8-bit shift register with output register
DC CHARACTERISTICS FOR 74HC For the DC characteristics, see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: parallel outputs, bus driver; serial output, standard. ICC category: MSI. AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Tamb (C) SYMBOL PARAMETER - - - - - - - - - - - - +25 -40 to +85 - - - - - - - - - - - - 100 20 17 100 20 17 100 20 17 125 25 21 125 25 21 125 25 21
74HC/HCT594
TEST CONDITIONS WAVEFORMS
min. typ. max. min. tPHL/tPLH propagation delay SHCP to Q7' propagation delay STCP to Qn tPHL propagation delay SHR to Q7' propagation delay STR to Qn tW 44 16 14 44 16 14 39 14 12 39 14 12 10 4 3 10 4 3 14 5 4 10 4 3 14 5 4 17 6 5 150 30 26 150 30 26 150 30 26 125 25 21 - - - - - - - - - - - - - - - - - -
-40 to +125 UNIT VCC (V) max. min. max. - - - - - - - - - - - - 120 24 20 120 24 20 120 24 20 150 30 26 150 30 26 150 30 26 225 45 38 225 45 38 225 45 38 185 37 31 - - - - - - - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0
185 37 31 185 37 31 185 37 31 155 31 26 - - - - - - - - - - - - - - - - - -
Fig.7
Fig.8
Fig.11
Fig.12
shift clock pulse width 80 HIGH or LOW 16 14 storage clock pulse width HIGH or LOW 80 16 14
Fig.7
Fig.8
shift and storage reset 80 pulse width HIGH or 16 LOW 14 tsu set-up time Ds to SHCP set-up time SHR to STCP set-up time SHCP to STCP 100 20 17 100 20 17 100 20 17
Fig.11 and Fig.12
Fig.9
Fig.10
Fig.8
December 1991
6
Philips Semiconductors
Product specification
8-bit shift register with output register
74HC/HCT594
Tamb (C) SYMBOL PARAMETER +25 -8 -3 -2 -14 -5 -4 30 92 109 - - - - - - - - - -40 to +85 - - - - - - - - -
TEST CONDITIONS WAVEFORMS
min. typ. max. min. th hold time Ds to SHCP 25 5 4 50 10 9 6.0 30 35 30 6 5 65 13 11 4.8 24 28
-40 to +125 UNIT VCC (V) max. min. max. 35 7 6 75 15 13 4.0 20 24 - - - - - - - - - ns ns ns ns ns ns MHz MHz MHz 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0
Fig.9
trem
removal time SHR to SHCP, STR to STCP maximum clock frequency SHCP or STCP
Fig.11 and Fig.12
fmax
Fig.7 and Fig.8
December 1991
7
Philips Semiconductors
Product specification
8-bit shift register with output register
DC CHARACTERISTICS FOR 74HCT For the DC characteristics, see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: parallel outputs, bus driver; serial output, standard. ICC category: MSI. Note to HCT types The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the following table. INPUT Ds SHR SHCP STCP STR
74HC/HCT594
UNIT LOAD COEFFICIENT 0.25 1.50 1.50 1.50 1.50
AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Tamb (C) SYMBOL PARAMETER - - - - 16 16 16 +25 -40 to +85 - - - - 20 20 20 TEST CONDITIONS WAVEFORMS
min. typ. max. min. tPHL/tPLH propagation delay SHCP to Q7' propagation delay STCP to Qn tPHL propagation delay SHR to Q7' propagation delay STR to Qn tW shift clock pulse width HIGH or LOW storage clock pulse width HIGH or LOW shift and storage reset pulse width HIGH or LOW tsu set-up time Ds to SHCP set-up time SHR to STCP set-up time SHCP to STCP th trem hold time Ds to SHCP removal time SHR to SHCP, STR to STCP maximum clock frequency SHCP or STCP 18 18 17 17 4 4 6 32 32 30 30 - - -
-40 to +125 UNIT VCC (V) max. min. max. - - - - 24 24 24 48 48 45 45 - - - ns ns ns ns ns ns ns 4.5 4.5 4.5 4.5 4.5 4.5 4.5
40 40 38 38 - - -
Fig.7 Fig.8 Fig.11 Fig.12 Fig.7 Fig.8 Fig.11 and Fig.12
20 20 20 5 10
4 6 7 -3 -5
- - - - -
25 25 25 6 13
- - - - -
30 30 30 7 15
- - - - -
ns ns ns ns ns
4.5 4.5 4.5 4.5 4.5
Fig.9 Fig.10 Fig.8 Fig.9 Fig.11 and Fig.12
fmax
30
92
-
24
-
20
-
MHz
4.5
Fig.7 and Fig.8
December 1991
8
Philips Semiconductors
Product specification
8-bit shift register with output register
AC WAVEFORMS
74HC/HCT594
SH CP INPUT
VM t su
(1)
1/ f max V M (1) tW t PLH t PHL V M (1)
MLA512
ST CP INPUT
Q n OUTPUTS
(1) HC: VM = 50%; VI = GND to VCC HCT: VM = 1.3 V; VI = GND to 3 V
(1) HC: VM = 50%; VI = GND to VCC HCT: VM = 1.3 V; VI = GND to 3 V
Fig.8 Fig.7 Waveforms showing the shift clock (SHCP) to output (Q7') propagation delays, the shift clock pulse width and the maximum shift clock frequency.
Waveforms showing the storage clock (STCP) to output (Qn) propagation delays, the storage clock pulse width, maximum storage clock frequency and the shift clock to storage clock set-up time.
handbook, halfpage
SH R INPUT
VM (1)
t su V M (1)
ST CP INPUT
Q n OUTPUTS
V M (1)
MBC326
(1) HC: VM = 50%; VI = GND to VCC HCT: VM = 1.3 V; VI = GND to 3 V
(1) HC: VM = 50%; VI = GND to VCC HCT: VM = 1.3 V; VI = GND to 3 V
Fig.9
Waveforms showing the data set-up and hold times for the Ds input.
Fig.10 Waveforms showing the set-up time from shift reset (SHR) to storage clock (STCP).
December 1991
9
Philips Semiconductors
Product specification
8-bit shift register with output register
74HC/HCT594
handbook, halfpage
handbook, halfpage
SH R INPUT
VM
(1)
ST R INPUT
VM (1) tW
tW
t rem VM (1)
t rem VM (1)
SH CP INPUT
ST CP INPUT
t PHL
(1)
t PHL
(1)
Q 7' OUTPUT
VM
Q n OUTPUTS
MBC324
VM
MBC325 - 1
(1) HC: VM = 50%; VI = GND to VCC HCT: VM = 1.3 V; VI = GND to 3 V
(1) HC: VM = 50%; VI = GND to VCC HCT: VM = 1.3 V; VI = GND to 3 V
Fig.11 Waveforms showing the shift reset (SHR) pulse width, the shift reset to output (Q7') propagation delay and the shift reset to shift clock (SHCP) removal time.
Fig.12 Waveforms showing the storage reset (STR) pulse width, the storage reset to outputs (Qn) propagation delay and the storage reset to storage clock (STCP) removal time.
PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines".
December 1991
10
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