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| Specificatio n, V ersion 2 .0 1, 2 004-02-05 TUA6120 'TORNADO' Gain controlled I/Q Mixer for d i g i t a l Q P S K o r 8PSK Sat Signa ls Wireless Components Never stop thinking. Edition 2004-02-05 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany (c) Infineon Technologies AG 9/16/03. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Specificatio n, V ersion 2 .0 1, 2 004-02-05 TUA6120 'TORNADO' Gain controlled I/Q Mixer for d i g i t a l Q P S K o r 8PSK Sat Signa ls Wireless Components Never stop thinking. Target Specification V1.1 Confidential Revision History: 2001-10-22 Previous Version: Page 11ff 48ff Pinning Defaults added V1.0 2001-07-06 Subjects (major changes since last revision) TUA6120 'TORNADO' Preliminary Specification Version 1.2 Confidential Revision History: 2002-02-25 Previous Version: Page all 12ff 29 38 42 43 50, 53 55, 56 57 58 V1.1 2001-10-22 Subjects (major changes since last revision) Version to preliminary TUA6120 'TORNADO' Equivalent I/O schematics and DC levels added Application Circuit changed Items # 1, # 10, # 11, # 12, # 13 changed Item # 83 changed Items # 94, # 95, # 98, # 100 changed Footnote added Band 10/11 overlap frequency changed Figure 4-2 changed tSU.ENASDA deleted Preliminary Specification Version 1.3 Confidential Revision History: 2002-12-20 Previous Version: Page diverse 38ff 48 49 50 52 53 54 V1.1 2001-10-22 Subjects (major changes since last revision) Input frequency extended to 2185 MHz TUA6120 'TORNADO' # 3, # 4, # 6, # 8, # 9, # 10, # 11, # 12, # 22, # 29, # 31, # 32, # 35, # 69, # 79, # 80, # 81, # 63, # 64, # 65, # 66, # 91, # 92, # 93, # 94, # 95 changed, # 14 added Bits 0 to 17, 21, 23 changed Bits 0 to 9 changed, new charge pump currents XTAL I/O new output levels new filter bandwidths ABL: New default Register 80: Footnote changed Target Specification Version 1.4 Confidential Revision History: 2003-01-06 Previous Version: Page 52 55 V1.3 2002-12-20 Subjects (major changes since last revision) Register 05: Xtal output control bit added TUA6120 'TORNADO' VCO band switching table Band # 9 , # 10: GHz-N and GHz-R divider ratio changed Preliminary Specification Version 1.5 Confidential Revision History: 2003-07-31 Previous Version: Page 11 12 15 16 22 29 29 36 38 38 39 39 41 41 43 49 50 52 54 V1.4 2003-01-06 Subjects (major changes since last revision) Function of pins 2, 14 and 23 changed Function of pin 2 changed Function of pin 14 changed Function of pin 23 changed Function of pins 2, 14 and 22 changed Function of pins 2, 14 and 22 changed pin 12, loop filter changed # 23; Value changed # 1, # 3, # 4, # 7, # 11; Values changed # 13, # 14; Value changed # 21, # 27-# 29; Value changed # 23-# 25; New added # 31, # 32; Value changed # 54; Value changed # 61-# 66; Value changed # 62; New added # 100; Value changed # 101; New added Bit 15; Definition changed Bit 7,6; Definition changed Bit 5; Value changed Bit 2,3,4,5; Definition changed TUA6120 'TORNADO' Preliminary Specification Version 2.0 Confidential Revision History: 2003-12-17 Previous Version: Page 8 10 16 22 29 35 36 36 36 36 36 38 38 38 38 38 38 38 38 38 39 39 39 40 40 40 40 40 40 41 41 41 V1.5 2003-07-31 Subjects (major changes since last revision) Splitting tuning range changed Splitting tuning range changed Pin 20 Equivalent I/O-Schematic, corrected Block diagram corrected Application circuit, Block diagram corrected # 4 Crystal oscillator divider, new # 14 AGC timing cap inputs, values changed # 17 , # 18 VREF - , VVCOREF - removed TUA6120 'TORNADO' # 17 , # 18 , # 19 VREF +, VVCOREF +, VVREF_BBF , values changed # 21 ESD-Protection , value changed # 23 Ambient temperature, value new # 1 Stand-by, loop- through on, changed RF input testing range changed # 3 minimum RF input level test condition, new # 4 Maximum RF input level min. limit, new # 6 Gain control range min. limit, new # 7 Overall voltage gain limit, changed # 11 Input IP2, value changed # 12 Input IP2, value changed # 14 Loop-through gain test condition, new # 15 RF input DC, new # 16 RF output DC, new # 26 Filter stop band, new # 33 Base-band I / Q inputs, new # 37 AGCCAP1 voltage, new # 43 VREF_BBF, new # 45 VCOREF+, new # 47 VREF+, new # 49 GHz PLL Phase detector Charge pump output, new # 60 PLL tuning step size, new added # 63 - # 66 Phase noise test condition, new # 67 PLL spurious at baseband outputs, new 41 42 42 42 43 43 47 49 50 50 54 55 56 58 59 # 68 Charge pump DC value changed # 71 - # 73 Synthesizer PLL active loop filter output, new # 74 - # 77 Tuning VCO range added # 82 - # 84, # 89 Crystal DC moved to reference oscillator I/O, new limits # 102 ADC clock for AGC, new Table 4-4 XTALDIV1 XTALDIV2, corrected I2C short read format, new Note1) for GHz R/N-counter, new Bit 8 -12; ADC clock description, added Note3) for Preamp = on, new RSSI bit 0 not used, corrected VCO band switching table changed VCO band splitting graph changed # 1 - # 2 I2C bus L, H level changed Electrical Diagrams, new Specification Version 2.01 Revision History: Previous Version: Page 12 39 2004-02-05 V2.0 2003-12-17 TUA6120 'TORNADO' Subjects (major changes since last revision) Correction of several Average DC voltages RF output DC, corrected For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com ABM(R), AOP(R), ARCOFI(R), ARCOFI(R)-BA, ARCOFI(R)-SP, DigiTape(R), EPIC(R)-1, EPIC(R)-S ELIC(R), FALC(R)54, FALC(R)56, FALC(R)-E1, FALC(R)-LH, IDEC(R), IOM(R), IOM(R)-1, IOM(R)-2 IPAT(R)-2, ISAC(R)-P, ISAC(R)-S, ISAC(R)-S TE, ISAC(R)-P TE, ITAC(R), IWE(R), MUSAC(R)-A OCTAT(R)-P, QUAT(R)-S, SICAT(R), SICOFI(R), SICOFI(R)-2, SICOFI(R)-4, SICOFI(R)-4C SLICOFI(R) are registered trademarks of Infineon Technologies AG. ACETM, ASMTM, ASPTM, POTSWIRETM, QuadFALCTM, SCOUTTM are trademarks of Infineon Technologies AG. Controller Area Network (CAN): License of Robert Bosch GmbH Gain controlled I/Q Mixer for digital QPSK or 8PSK Sat Signals TUA6120 'TORNADO' Version 2.01 Product Info General Description The TUA6120 'TORNADO' is a direct conversion receiver for digital QPSK or 8PSK Sat receiving systems in BICMOS technology. P-VQFN-48-4 Features Few, uncritical external components Low impedance unbalanced RF input RF loop-through Dual matched double balanced mixers Digital generation of 0/90 LO signals On-chip oscillators On-chip baseband filters Balanced I/Q outputs Internal AGC for constant output level dB-linear RSSI readout CMOS PLL-Synthesizer 2 high current switch outputs Buffered crystal oscillator I/O Low noise reference voltage 3-wire bus with sub addresses I2C bus with 4 chip addresses and sub addresses Splitting of Sat tuning range into 14 bands LO frequency above input frequency No external tuning voltage required Application DBS, DVB-S, DSS and ISDB-S SetTop Boxes Suitable for dual-NIM applications Any I/Q down converter from 915 MHz - 2185 MHz to 0 - 30 MHz Type TUA6120 'TORNADO' Ordering Code Q 67037-A4 Package P-VQFN-48-4 Specification 8 2004-02-05 TUA6120 'TORNADO' Version 2.01 Confidential Product Description 1 1.1 Product Description Overview The TUA6120 'TORNADO' is a Direct Conversion Receiver for digital QPSK or 8PSKSat receiving systems in BICMOS technology. Compared to the conventional superheterodyne receiver the DCR architecture eliminates expensive RF-filters for image rejection and IF-filters for channel selection. Instead there are on-chip filters with selectable bandwidth integrated. The DCR system is the most promising approach for low-cost digital set-top boxes front ends. Via a LNA input stage, the RF signal is split into two rails. One is the buffered loopthrough RF output and, the other goes through a PGA (Programmable Gain Amplifier) to the I/Q- Mixers. The signal of the synthesizer VCO is multiplied to 4 x RF input frequency by an internal 3.8-8.6 GHz PLL system. To drive the mixers, this 3.8-8.6 GHz signal is split into quadrature components by a digital divider by 4. The VCO from which the oscillator signal is derived, never runs at the input frequency. The mixers are followed by 2 matched base-band PGA's and filters. The filter roll-off is selectable by software. Behind the filters external coupling capacitors eliminate undesired DC-components. Then follow another two base-band amplifiers and output buffers. The gain of the Q base-band amplifier is adjustable for compensation of I/Q gain impairment. The AGC detector senses the output level and generates the control signals for the PGAs and the RSSI information which is readable via the bus. The AGC system is optimized for best SNR and IM performance. 1.2 Features Few, uncritical external components Low impedance unbalanced RF input RF loop-through Dual matched double balanced mixers Digital generation of 0/90 LO signals On-chip oscillators On-chip baseband filters Balanced I/Q outputs Internal AGC for constant output level Specification 9 2004-02-05 TUA6120 'TORNADO' Version 2.01 Confidential Product Description dB-linear RSSI readout CMOS PLL-Synthesizer 2 high current switch outputs Buffered crystal oscillator I/O Low noise reference voltage 3-wire bus with sub addresses I2C bus with 4 chip addresses and sub addresses Splitting of Sat tuning range into 14 bands LO frequency above input frequency No external tuning voltage required 1.3 Application DBS, DVB-S, DSS and ISDB-S Set-Top Boxes Suitable for dual-NIMM applications Any I/Q down converter from 915 MHz - 2185 MHz to frequencies 0 - 30 MHz 1.4 Package Outline P_VQFN_48-4.eps Specification 10 2004-02-05 TUA6120 'TORNADO' Version 2.01 Functional Description 2 2.1 Functional Description Pin Configuration BUSMODE XTALDIV1 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 VCCA3 GNDA3 AGCCAP1 AGCCAP2 FQIN BB1QOUT FIIN BB1IOUT VCCD GNDD SDA SCL 37 38 39 40 41 42 43 44 45 46 47 48 10 11 12 1 2 3 4 5 6 7 8 9 XTALDIV2 XTALOUT GNDOUT XTALIN VCCA4 VCCA5 QOUTi QOUT IOUTi IOUT XTALIO N.C. VREF+ CPOUT LPF1OUT VTUNE VCOGND VCOGND VCOGND VCOGND Port1 VCOREF+ TUA6120 'TORNADO' 19 18 17 16 15 14 13 CAS/EN RFIN GNDRFIN VCCA1 VCCA2 PORT0 VREF_BBF GNDA1 GNDA2 RFOUT Figure 2-1 Pin Configuration Specification 11 GNDRFOUT LPF2 2004-02-05 TUA6120 'TORNADO' Version 2.01 Functional Description 2.2 Table 2-1 Pin No. 1 Pin Definitions and Function Pin Definition and Function Equivalent I/O-Schematic Average DC voltage n.a. Symbol CAS/EN 1 Vref 2 VREF_BBF 2.4 V 2 3 PORT0 3 0.0/5.0 V 4 5 VCCA1 GNDA1 power supply analog ground 5.0 V 0.0 V Specification 12 2004-02-05 TUA6120 'TORNADO' Version 2.01 Functional Description Table 2-1 Pin No. 6 Pin Definition and Function (continued) Equivalent I/O-Schematic Average DC voltage 2.0 V Symbol RFIN 6 7 8 9 10 GNDRFIN GNDA2 VCCA2 RFOUT ground ground power supply analog 0.0 V 0.0 V 5.0 V 1.4 V 10 11 GNDRFOUT ground 0.0 V Specification 13 2004-02-05 TUA6120 'TORNADO' Version 2.01 Functional Description Table 2-1 Pin No. 12 Pin Definition and Function (continued) Equivalent I/O-Schematic Average DC voltage n.a. Symbol LPF2 12 13 VCOREF+ Vref 1.75 V 13 Specification 14 2004-02-05 TUA6120 'TORNADO' Version 2.01 Functional Description Table 2-1 Pin No. 14 Pin Definition and Function (continued) Equivalent I/O-Schematic Average DC voltage 0.0/5.0 V 14 Symbol Port 1 15 16 17 18 19 VCOGND VCOGND VCOGND VCOGND VTUNE ground ground ground ground 0.0 V 0.0 V 0.0 V 0.0 V n.a. 19 Specification 15 2004-02-05 TUA6120 'TORNADO' Version 2.01 Functional Description Table 2-1 Pin No. 20 Pin Definition and Function (continued) Equivalent I/O-Schematic Average DC voltage n.a. Vcc 5K 20 Symbol LPF1OUT 21 CPOUT n.a. 21 22 VREF+ Vref 1.6 V 22 23 N. C. n. a. Specification 16 2004-02-05 TUA6120 'TORNADO' Version 2.01 Functional Description Table 2-1 Pin No. 24 Pin Definition and Function (continued) Equivalent I/O-Schematic Average DC voltage n.a. Symbol XTALIO 24 25 XTALDIV2 0.0/3.2 V 28 25 26 XTALIN 26 1.6 V 27 XTALOUT 1.6 V 27 Specification 17 2004-02-05 TUA6120 'TORNADO' Version 2.01 Functional Description Table 2-1 Pin No. 28 Pin Definition and Function (continued) Equivalent I/O-Schematic Average DC voltage 0.0/3.2 V Symbol XTALDIV1 28 25 29 BUSMODE 5.0 V 29 30 QOUTi 2.4 V 31 QOUT 31 30 2.4 V 32 GNDOUT ground 0.0 V Specification 18 2004-02-05 TUA6120 'TORNADO' Version 2.01 Functional Description Table 2-1 Pin No. 33 Pin Definition and Function (continued) Equivalent I/O-Schematic Average DC voltage 2.4 V Symbol IOUTi 34 34 IOUT 33 2.4 V 35 36 37 38 39 VCCA5 VCCA4 VCCA3 GNDA3 AGCCAP1 power supply analog power supply analog power supply analog ground 39 5.0 V 5.0 V 5.0 V 0.0 V 3.15 V Specification 19 2004-02-05 TUA6120 'TORNADO' Version 2.01 Functional Description Table 2-1 Pin No. 40 Pin Definition and Function (continued) Equivalent I/O-Schematic Average DC voltage n.a. 40 Symbol AGCCAP2 1) 41 FQIN 2.4 V 41 42 BB1QOUT 2.4 V 42 Specification 20 2004-02-05 TUA6120 'TORNADO' Version 2.01 Functional Description Table 2-1 Pin No. 43 Pin Definition and Function (continued) Equivalent I/O-Schematic Average DC voltage 2.4 V Symbol FIIN 43 44 BB1IOUT 2.4 V 44 45 46 47 VCCD GNDD SDA power supply digital ground 5.0 V 0.0 V n.a. 47 48 SCL 48 n.a. 1) If the AGC is in external mode, this pin is used as AGC input, see Register 04 on page 51 Specification 21 2004-02-05 TUA6120 'TORNADO' Version 2.01 Functional Description 2.3 Functional Block Diagram BUSMODE XTALDIV1 XTALDIV2 25 XTALOUT GNDOUT 36 35 34 33 32 31 30 29 28 27 26 VCCA3 XTALIN VCCA4 VCCA5 IOUTi QOUTi IOUT QOUT 37 24 XTALIO GNDA3 38 IBaseband Amp QBaseband Amp Crystal Oscillator Crystal Divider Crystal I/O Buffer 23 N.C. AGCCAP1 39 AGC Detector IBaseband Filter IBaseband Amp QBaseband Filter QBaseband Amp Power Supply 22 VREF+ AGCCAP2 40 RSSI AGC Encoder 21 CPOUT BB2QIN 41 20 LPF1OUT FQOUT 42 19 VTUNE BB2IIN 43 18 VCOGND I-Mixer FIOUT P0 Q-Mixer 17 44 VCOGND VCCD 45 I2 C / 3-Wire Bus CMOS Synthesizer PLL Synthesizer VCOs GNDD 46 PGA GHz VCOs, GHz PLL, Quadrature Phase Generator 16 VCOGND 15 VCOGND SDA 47 14 PORT1 LNA SCL 48 RF Buffer 13 VCOREF+ 1 2 3 4 5 6 7 8 9 10 11 12 RFOUT GNDRFOUT VREF_BBF CAS/EN GNDA1 GNDRFIN GNDA2 PORT0 VCCA1 VCCA2 LPF2 RFIN TUA6120 Blockdiag Figure 2-2 Block Diagram Specification 22 2004-02-05 TUA6120 'TORNADO' Version 2.01 Functional Description 2.4 Frequency programming The tuning frequency of the RF input controlled by the PLL is given below: Fin M = [ ( P N ) + A ] fref = --- fref -------R R Input frequency calculation frequency of RFinput. with A N Figure 2-3 rf : ri : P: A: N: R: reference frequency input (crystal oscillator). divide ratio of the prescaler [P/(P+1) = (32/33)] . divide ratio of the A-counter (max. 7 bit). divide ratio of the N-counter (max. 11 bit). divide ratio of the R-counter (max. 10 bit). M = (P N) + A : total divide ratio of the PLL (with A < N). In addition to the above calculation, for each frequency the correct values of the GHz PLL and the VCO settings must be set. See "VCO band switching table" on Page 55 [(P N) + A] P [P - 1] Figure 2-4 Condition for continuous frequency steps 2.5 Functional Block Description The main functions of the chip are split into a bipolar analog signal processing, a bipolar digital signal generation of 0/ 90 LO-signals, and a CMOS synthesizer. Extremely symmetrical layout with matched structures result in best phase and gain balance of the in-phase and quadrature-phase signals. 2.5.1 AGC-System A complete AGC system is integrated. At the I/Q outputs an AGC detector monitors the output signal. It generates a dB-linear RSSI signal to the input level (Radio Signal Strength Indicator), and control signals to adjust the gain of the PGA's (Programmable Gain Amplifiers). PGA's are used because of their good intermodulation performance during gain control. The smallest AGC step is 0.5 dB, the AGC range is 63.5 dB. The internal AGC can be disabled. Then an external AGC voltage can be applied to pin 40. Specification 23 2004-02-05 TUA6120 'TORNADO' Version 2.01 Functional Description 2.5.2 LNA and RF-Buffer The LNA is a 75 input amplifier with high linearity and low noise. At its output the RF signal is split. One part goes through the RF-buffer amplifier to a 75 RF-output. 2.5.3 PGA and I/Q-Mixers The other part goes through a 48 dB control range PGA to the I and Q mixers. Both are of the double balanced mixer (Gilbert cell) type. A second PGA is arranged between the mixer output and the following baseband amplifier. For best performance the 0/ 90 LO-signals are fed to the mixers via open collector stages with well defined output impedance and levels. 2.5.4 Baseband Amplifiers and Filters The 4 base band amplifiers are of wide-band operational type with high overshoot margin. The amplifiers have a fixed gain of 16 dB and 30 MHz-0dB bandwidth. The distribution of the whole DC-gain into two AC-coupled 16 dB amplifiers ensures that the base band amplifiers are not overloaded by a DC-voltage that may be caused by mixer offset or mixer LO feedback to the input. All 4 outputs can be disabled by bus control. In this state the outputs switch to low voltage and low impedance. Filters with programmable roll-off are inserted between the baseband amplifiers. The I and Q output voltages are programmable. The outputs are differential for best interference immunity. 2.5.5 Output Ports The output ports are designed with open collector transistors for high current pull down and slow switching application. 2.5.6 Reference Voltage The central reference voltage is a low noise high PSSR bandgap with approx. 2.4 V DC and low temperature drift. 2.5.7 Reference Oscillator The reference oscillator operates with crystals from 1 - 16 MHz. Specification 24 2004-02-05 TUA6120 'TORNADO' Version 2.01 Functional Description 2.5.8 Crystal Oscillator Input/Output This pin accepts an external quartz clock or supplies a quartz clock to the channel decoder. The frequency is controlled by a divider stage. 2.5.9 Synthesizer Loop filter The synthesizer loop filter can be designed active by using an internal inverting BICMOS amplifier or passive (see Application Circuit on page 29). The loop filter input is internally connected to the phase detector / charge pump output. The BICMOS amplifier output may be disabled (high impedance) by bus. 2.5.10 Synthesizer VCO's The synthesizer VCO's are symmetrical Colpitts type oscillators with high-Q internal tank circuits. The synthesizer VCO's oscillate at a programmable offset to the input frequency. This guarantees minimum oscillator pulling and self-mixing which results in undesirable DC offset voltage. 2.5.11 Phase Shift 0 / 90 To get minimum quadrature phase error, a digital generation of the 0/90 phase shifted local oscillator signal is implemented by a 3.8-8.6 GHz Johnson-counter / 4 . This counter is designed in high speed stacked ECL bipolar technology. 2.5.12 GHz VCO This block consists of two on-chip bipolar LC-Oscillators (3.4-6.2 GHz and 6.0-8.6 GHz) controlled via on-chip PLL . The GHz VCO's oscillate at 4 times the input frequency and are current controlled. The resonant circuit is an on chip symmetrical inductor driven by differential pair amplifier whose current variable parasitic capacitance is used for frequency tuning. The used special multi-tanh gilbert cell makes a wide tuning range possible. The GHz VCO's are under control of a 3.8-8.6 GHz PLL system. The reference frequency of this system is the output of the synthesizer VCO divided by a programmable counter; variation is 200-315 MHz (depending on the selected synthesizer tuning range). At the same time this is the operating frequency range of the phase detector / charge pump. The high speed charge pump is completely on-chip and designed in BICMOS technology with an external loop filter bandwidth set to 9 MHz. The GHz VCO frequency is fed to the phase detector via the high speed ECL Johnson counter /4 and a lower speed programmable ECL counter. Specification 25 2004-02-05 TUA6120 'TORNADO' Version 2.01 Functional Description 2.6 GHz PLL With conventional DCR systems the synthesizer VCO oscillates exactly at the desired receiving frequency. This is avoided in the TUA6120 'TORNADO' by a cascaded double PLL tuning system. The main benefits of this concept are: accurate 0 / 90 generation of the LO signals for the RF input mixers no oscillator at input frequency programmable frequency offset of the synthesizer VCO referred to the RF input frequency and due to that a very low VCO oscillator pulling and self mixing due to crosstalk the possibility of splitting the tuning range into several bands. These advantages are derived from a 2nd GHz PLL system with two VCO's at 4 x Fin. This 2nd GHz PLL system is located in the broken up feedback of the synthesizer PLL 1 between the VCO1 and the programmable counter input N1. Fref PLL 1 (Synthesizer) VCO1 PLL 2 VCO2 R1 PD1 CP1 interrupted PLL 1 R2 PD2 CP2 N : main counter N1 R : reference counter PD : phase detector CP : charge pump VCO : voltage controlled oscillator Q2 : Quadraturphase + prescaler X N2 Q2 cascaded PLL system LO I/Q output to mixer Figure 2-5 Cascaded PLL system This location enables a shift of the synthesizer VCO1 to other frequencies, independent of the required input LO frequency of the RF mixers. In this case the synthesizer VCO must not oscillate at the required LO frequency of the mixer input. Nevertheless the synthesizer PLL is referred to the LO frequency of the mixer input which makes it easy to program the PLL because it is set exactly to the receiving frequency. Another benefit is the exact mapping of the PLL stepsize to the tuning frequency. This is not possible in a conventional PLL tuning system with the feedback of the VCO1 directly to the programmable counters N1, if the VCO1 is not running on the RF input Specification 26 2004-02-05 TUA6120 'TORNADO' Version 2.01 Functional Description frequency. This may become clear in the above concept, if the interrupted PLL 1 is closed and the LO I/Q output is cut off from node x. In this case step size and tuning frequency have additional terms of calculation. Depending on the system concept. they do not fit to the programmed values of the synthesizer PLL 1, because it is referred to the VCO1 and no longer to the LO I/Q output. (Following dependencies will become valid, Ftune = (N2 / R2)Fvco1 and Fstep = (N2 / R2)PLL1step ). The R2 and N2 counters of the GHz PLL enable a programmable frequency offset of the synthesizer VCO to the RF input as well as a splitting of the required RF tuning range. For the band splitting feature the counters R2 and N2 of the GHz PLL must be used with 2 different values (e.g. 4/2 and 4/3). As a result VCO1 will pass his range twice, while the LO I/Q output to mixer will have a tuning range which is split into 2 bands. In the feedback of the GHz PLL is located the high speed Johnson-counter / 4 (Q2) which acts as prescaler for the two 3.4 - 8.6 GHz VCO's and accurate 0 / 90 LO generator. The complete GHz PLL is designed in high speed ECL cascoded technology which enables counter frequencies up to 15 GHz, oscillator frequencies up to 10 GHz and phase detector / charge pump signal slopes of less then 100 ps. Specification 27 2004-02-05 TUA6120 'TORNADO' Version 2.01 Functional Description 2.6.1 Functional GHz PLL Block Diagram 2nd GHz PLL (Quadrature Phase loop) loop filter 9 MHz programming lines VCO2 4 x Fin 3.4-6.2GHz 6.0-8.6GHz GR programmable counter /2 - /8 counter / 2 0.4 - 3.8 GHz phase detector type 4 100-550 MHz Fpd2 GN programmable counter /2 - /8 counter / 2 0.85 - 2.2 GHz counter/2 0/90counter/2 0.95-2.15 GHz to the mixers I Q FIQ 2nd loop reference input GR Fvco = FIQ * -------GN detailed drawing 2nd loop output 2nd GHz-PLL , performing Quadrature Phase Generator, Band-switching and VCO Offset Fvco Synthesizer VCO reference oscillator 1-16 MHz 3.2 - 3.5 GHz 3.5 - 3.8 GHz programming lines input synthesizer input = Fpr Fvco conventional synthesizer loop loop filter 25 kHz I2C / 3-wire bus programming Interface R programmable counter 2-1023 0.5 - 16 MHz N+A Fref phase detector type 4 DC - 2 MHz programmable counter 2-2023 1 - 150 MHz P modulus.prescaler 32 / 33 FN 0.2 - 2.5 GHz programming lines Synthesizer Loop Figure 2-6 GHz PLL block diagram Specification 28 2004-02-05 TUA6120 'TORNADO' Version 2.01 Application 3 3.1 Application Application Circuit BUSMODE XTAL div 1 100 100n 36 100n 35 22p 22p 100 220n 33 32 100 22p 22p 39p 100 220n 30 29 4n7 28 4n7 27 4 MHz 39p 4n7 26 25 220n 34 220n 31 10p VCCA3 100n XTAL div 2 VCCA4 VCCA5 QOUTi QOUT IOUT IOUTi 37 24 XTALIO 38 IBaseband Amp QBaseband Amp Crystal Oscillator Crystal Divider Crystal I/O Buffer 23 220n 39 100n AGC Detector IBaseband Filter IBaseband Amp QBaseband Filter QBaseband Amp Power Supply 22 470p 100n 21 2.2k 100n ext. AGC 100n 40 RSSI AGC Encoder 21 470p 2.2k 41 20 1.8k 20 1.8k 1n 1n 220n 42 19 loop filter 1 passive 19 43 18 44 P0 220n I-Mixer Q-Mixer 17 VCC digital 10 10n 45 I2C / 3-Wire Bus CMOS Synthesizer PLL Synthesizer VCOs 46 PGA GHz VCOs, GHz PLL, Quadrature Phase Generator 16 15 220 4n7 47 14 SDA 100p 220 PORT1 LNA 48 RF Buffer 13 220n SCL 100p 1 4n7 2 3 4n7 220n 4 100n 5 6 7 8 9 100n 10 11 12 1n 100p 100p 6k8 220 loop filter 2 PORT0 RF in VCC analog 1 VCC analog 2 CAS/EN RF out 4n7 TUA6120 Application Figure 3-1 Application circuit Specification 29 2004-02-05 active TUA6120 'TORNADO' Version 2.01 Application 3.2 Phase noise performance of application The over all system phase noise at base band of the TUA 6120 is strongly dependent on several parameters : 1.programming of the 2nd PLL (GHz-PLL setting of the R2 and N2 counter) 2.programming of the 1st synthesizer PLL - receiving frequency (variation of the VCO steepness due to non linearity of the varicap), - phase detector current, - crystal frequency, - step size = Fref, - loop filter parameter. ( bandwidth ) A well balanced phase noise over the whole tuning range requires an optimized parameter programming of the synthesizer PLL for each receiving frequency - 1st you have to decide for the optimum loop filter bandwidth for your application. Narrow band loop filter : achieves better PLL outband phase noise at high frequencies offset but lower PLL inband phase noise at low frequency offset. Wide band loop filter : achieves better PLL inband phase noise at low frequencies offset but lower PLL outband phase noise at high frequency offset. - 2nd you have to decide for the crystal frequency for your application. Higher crystal frequency achieves better PLL inband phase noise. - 3rd you have to decide for the main stepsize for your application. Higher step size achieves better PLL inband phase noise. - 4th during programming the desired receiving frequency you have to set step size and phase detector output current for each frequency. This is necessary to compensate the non linearity of the varicap. All this is done in the above application circuit which obtains in conjunction with the TUA 6120 programming kit the following worst case phase noise values : Wide band loop filter 25 kHz, at tuning frequency 2150 MHz Offset Frequency Measured phase noise at base band 1 - 82 10 - 83 100 - 102 1000 - 108 kHz dBc/Hz For detailed information see our separate evaluation report TUA 6120 C1/C2. Specification 30 2004-02-05 TUA6120 'TORNADO' Version 2.01 Application * VCO gain vs. Vtune (typical) valid for the application above, band splitting into 14 ranges .YFR 9&2 ORZ 0+] 9 9&2 KLJK 9WXQH >9@ * VCO gain vs. Fin (typical) valid for the application above, band splitting into 14 ranges .YFR 0+] 9 )LQSXW >0+]@ Specification 31 2004-02-05 TUA6120 'TORNADO' Version 2.01 Application * VCO tuning voltage (typical) valid for the application above, band splitting into 14 ranges 7XQLQJ 9ROWDJH >9@ ,QSXW )UHTXHQF\ >0+]@ * Optimum phase detector current (typical) for minimum loop filter bandwidth variation valid for the application above, band splitting into 14 ranges )LQ >0+]@ 2SWLPXP &KDUJHSXPS FXUUHQW IRU FRQVWDQW ORRS EDQGZLGWK DQG SKDVHQRLVH YV )LQ $YDLODEOH FXUUHQW RI 78$ %RUGHU EHWZHHQ FXUUHQWV Specification P$ 32 2004-02-05 TUA6120 'TORNADO' Version 2.01 Application * Optimum available phase detector current (typical) ,&3RSW DYDLODEOH >P$@ ,QSXW )UHTXHQF\ >0+]@ * Phase detector current switching table (typical) Result of graphics above > MHz 900 912 931 935 960 986 1000 1016 1043 1064 1080 1120 1150 1167 1185 1216 mA 1.333 1.667 2.000 1.000 1.333 1.667 1.000 1.333 1.667 2.000 1.000 1.333 1.667 1.000 1.333 1.667 > MHz 1242 1255 1261 1294 1313 1334 1368 1396 1415 1441 1479 1500 1524 1563 1596 1615 mA 2.000 1.000 1.333 1.667 1.000 1.333 1.667 2.000 1.000 1.333 1.667 1.000 1.333 1.667 2.000 1.000 > MHz 1680 1725 1750 1778 1824 1862 1885 1922 1972 2000 2032 2084 2129 2155 mA 1.333 1.667 1.000 1.333 1.667 2.000 1.000 1.333 1.667 1.000 1.333 1.667 2.000 1.000 Specification 33 2004-02-05 TUA6120 'TORNADO' Version 2.01 Application * Frequency band splitting into 14 ranges (no VCO frequency in receiving band) 51 )LQSXW >0+]@ KLJK VLGH 9&2 VSOLWWLQJ UDQJHV 51 51 51 51 51 51 6\QWK9FR ORZKLJK UDQJH 6\QWK9FR ORZKLJK VZLWFKLQJ 51 *+] YFR UDQJH/ *+] YFR UDQJH+ *+] YFR UDQJH+([W )YFR >0+]@ Specification 34 2004-02-05 TUA6120 'TORNADO' Version 2.01 Reference 4 4.1 4.1.1 Reference Electrical Data Absolute Maximum Ratings WARNING The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC will result. Table 4-1 Absolute Maximum Ratings # Parameter Symbol 1 2 3 4 5 6 7 8 Supply voltages 1, 2, 3, 4, 5 VVCCA1, 2, 3 ,4, 5 VVCCD Supply voltage 6 Crystal oscillator VXTALout, XTALin VXTALDIV1, 2 Crystal oscillator divider Crystal oscillator VXTALIO buffered I/O Synthesizer charge pump out VCPOUT Synthesizer Loop filter output VLPF1OUT VP0, P1 Port outputs IP0, P1 IP0, P1 Port outputs, t Imax 9 VP0, P1 = VVCCD, I = max 10 GHz-PLL Charge pump out VLPF2 VFIOUT, VFQQOUT 11 Baseband outputs IBB1IOUT, IBB1QOUT 12 Baseband filter inputs I/Q VBB2IIN, VBB2QIN Limit Values min max - 0.3 5.5 - 0.3 - 0.3 - 0.3 0 0 0 0 5.5 3.2 3.2 VVCCD VVCCD VVCCD VVCCD 15 30 1 0 0 VVCCA2 VVCCA2 4 0 VVCCA1 Unit Remarks V V V V V V V V mA mA ms V V mA V Specification 35 2004-02-05 TUA6120 'TORNADO' Version 2.01 Reference Table 4-1 Absolute Maximum Ratings (continued) Symbol Limit Values # Parameter min max VIOUT, IOUTi, 0 VVCCA1 VQOUT, QOUTi 13 Baseband outputs IIOUT, IOUTi, 4 IQOUT, QOUTi 14 AGC timing cap inputs 15 RF input 16 RF output 17 Reference voltage filter VAGCCAP1, VAGCCAP2 VLNA VRFOUT VREF+ 0 0 1.0 0 0 0 - 0.3 3.2 3.5 2.0 3.2 3.2 3.2 Unit Remarks V mA V V V V V V 18 VCO Reference voltage filter VVCOREF+ VVREF_BBF 19 Baseband filter reference 20 I2C / 3-Wire-Bus SCL,SDA, CAS/EN BUSMODE VESD Ptot TA Tj VVCCD+0.3 V 2 1300 kV mW C C C K/W 3) 2) 1) 21 ESD-Protection 22 Total power dissipation 23 Ambient temperature 24 Junction temperature -20 70 125 150 2 Tstg 25 Storage temperature Thermal resistance junction Rth 26 case 1) all ESD tests done according to EIA/JESD22-A114-B (HBM in circuit test), as a single device in circuit contact discharge test. The maximum ambient temperature depends on the mounting conditions of the package. Any application mounting must guarantee not to exceed the maximum junction temperature of 125 C. Referred to top center of package. 2) 3) Notes: All values are referred to ground (pin), unless stated otherwise. All currents are designated according to the source and sink principle, i.e. if the device pin is to be regarded as a sink (the current flows into the stated pin to internal ground), it has a negative sign, and if it is a source (the current flows from Vs across the designated pin), it has a positive sign. Specification 36 2004-02-05 TUA6120 'TORNADO' Version 2.01 Reference 4.1.2 Operating Range Table 4-2 Operating Range Symbol # Parameter Supply voltages 1,2,3,4,5 2 Supply voltage 6 Difference between VCCA1, VCCA2, VCCA3, VCCA4, 3 VCCA5, VCCD and between all GND pins 4 Input frequency range 1 VVCCA1, 2, 3, 4, 5 Limit Values min max 4.75 4.75 5.25 5.25 Unit Test Conditions Item V V VVCCD V -0.3 0.3 V fRFIN 915 -20 2185 70 MHz C 1) 5 Ambient temperature TA 1) This value is not subject to production test - verified by design/characterization. The maximum ambient temperature depends on the mounting conditions of the package. Any application mounting must guarantee not to exceed the maximum junction temperature of 125 C. Specification 37 2004-02-05 TUA6120 'TORNADO' Version 2.01 Reference 4.1.3 Table 4-3 AC/DC Characteristics AC/DC Characteristics, TA = 25 C, VVCCA1,VCCA2, VCCD = 5 V Symbol Limit Values min typ max Unit Test Conditions Item # Parameter Power supply 1 Total current consumption IVCCA1+ IVCCA2+ IVCCA3+ IVCCA4+ IVCCA5+ IVCCD 155 189 183 9 50 225 mA mA mA mA normal operation loop-through off Total stand by Stand-by, loopthrough on pin 4,9, 35, 36, 37, 45 RF input (950-2150MHz) RF source impedance 75 , RF input, pin 6, test circuit fRFIN 2 Input frequency 915 2185 MHz -79.5 dBm f = 1000 MHz minimum RF input VRFIN output level = 3 level -82 -77 dBm 1Vpp differential 4 maximum RF input VRFIN level RRFIN CRFIN 61 81 -60 -19.5 -17.0 -8 75 1.2 63.5 83,5 - 50 - 90 -5 35 5 -3 40 10 10 -1 38 5 Input impedance f = 1000 MHz, in AGC range dBm out of AGC range f = 0.9 - 2.2 GHz pF dBm dB dB -40 -80 output level = 1Vpp differential pin 6 6 Gain control range GV 7 Overall voltage gain GV VCO power present at RF input LO power present at 9 RF input input compression 10 point -1 dB 11 Input IP2 8 12 Input IP3 13 Noise Figure PVCO PLO ICP IIP2 IIP3 NF dBm f = R2 / N2 x fin dBm f = fin dBm minimum gain dBm dBm input level = -25 dBm output level = 600 mVpp differential 22MHz BBfilter on 11.5 dB dB maximum gain, DSB pin 10 14 Loop-through gain Gp Specification 75 , load 2004-02-05 TUA6120 'TORNADO' Version 2.01 Reference Table 4-3 AC/DC Characteristics, TA = 25 C, VVCCA1, VCCA2, VCCD = 5 V (cont'd) Symbol Limit Values min typ max 1.8 2.0 2.2 Unit Test Conditions Item # Parameter RF input DC 15 DC voltage RF output DC 16 DC voltage VRFin VRFout V pin 6 1.2 1.4 1.6 V pin 10 Base-band I / Q outputs, IOUT, IOUTi, QOUT, QOUTi, BB1IOUT, BB1QOUT, pins 34-33, 31-30, 44, 42 RL>1M VIout,Qout 17 DC voltage 2.4 V 18 DC quiescent current IIout,Qout VIOUT VQOUT BW-0.5 dB BW-1 dB BW -3 dB BW-1 dB BW-1 dB BW-1 dB G G RIOUT, RQOUT 5 28 7 33 39 2.4 500 20 30 50 9.8 19.5 29 -45 1000 22 35 60 11 22 33 -50 0.5 2 0 4 0.5 50 mA 2000 mVpp RL>1M RL>1M, CL < 10p, differential Baseband I/Q 19 output voltage see Register 05 on page 52 also pins 42, 44 Baseband I/Q 21 output bandwidth 22 Baseband filter 1 23 bandwidth Baseband filter 2 24 bandwidth Baseband filter 3 25 bandwidth 26 Filter stop band Baseband I/Q 27 output flatness Quadrature error, 28 phase 29 30 31 Quadrature error, gain Baseband I/Q output impedance 20 MHz no filter MHz reference=1MHz MHz 1Vpp differential 12.2 MHz 24.5 MHz 37 MHz dBc dB deg dB dB dB reference=1MHz 1Vpp differential Table "Register 05" on Page 52 f > 3 x froll-off up to 10 MHz, no filter 950 MHz, 1600 MHz, 2150 MHz, RFin = -35 dBm, test circuit dynamic resistance maximum gain minimum gain also pins 42, 44 IFOUT, SNR @ 45 Mbaud, QFOUT 1Vpp differential IFOUT, 32 QFOUT Specification 2004-02-05 TUA6120 'TORNADO' Version 2.01 Reference Table 4-3 AC/DC Characteristics, TA = 25 C, VVCCA1, VCCA2, VCCD = 5 V (cont'd) Symbol Limit Values min typ max Unit Test Conditions Item # Parameter Base-band I / Q inputs FIin, FQin, pins 41, 43 VFIin,FQin 33 DC voltage 34 Input resistance RFIin,FQin AGCCAP2 voltage input 35 Gain control range VGAIN Gain control input RGAIN 36 impedance 0.35 1 2.4 18 V k 1.65 V M RL>1M internal typical values pin 40 pin 40 AGCCAP1 voltage (AGC = internal) 37 Agc rectifier voltage VAgccap1 Port outputs, P0, P1 38 Supply voltage 3.15 V within AGC range pin 39 VP 0 0 0 5.5 0.5 15 10 1 V V mA 39 LOW output voltage VP 40 LOW output current IP 41 HIGH output current IP 42 Port outputs,I = max t Imax VREF_BBF 43 Reference voltage Vref 44 Vref output current Iref VCOREF+ 45 Reference voltage Vref 46 Vref output current Iref VREF+ 47 Reference voltage Vref 48 Vref output current Iref max. Vcc IP = 15 mA pins 3,14 A VP = 5 V ms VP0, P1 = VVCC 2.2 2.4 2.6 2 V mA pin 2 1.6 1.75 1.9 2 V mA pin 13 1.45 1.6 1.75 2 V mA pin 22 GHz PLL Phase detector Charge pump output / Loop filter input VLPF2 0.4 4.5 V loop locked 49 DC voltage ILPF2 50 DC current -100 100 A pin 12 Specification 40 2004-02-05 TUA6120 'TORNADO' Version 2.01 Reference Table 4-3 AC/DC Characteristics, TA = 25 C, VVCCA1, VCCA2, VCCD = 5 V (cont'd) Symbol Limit Values min typ max 2 0 2 32/33 -164 -159 -158 -155 -149 2 1 992 794 992 1984 4 2000 65631 2047 127 1023 Unit Test Conditions Item # Parameter Synthesizer PLL 51 N-counter divider N 52 A-counter divider A 53 R-counter divider R 54 Prescaler divider P 55 Equivalent phase PLL PLL 56 noise at phase detector input, PLL 57 @ 1 kHz offset, PLL within loop band 58 width, 6 kHz loop PLL BW, SSB Quadrature phase 59 mismatch 60 PLL tuning step size fref 61 Total divider ratio 1) M 62 Input frequency 1) 11-Bit, CMOS 7- Bit, CMOS 10-Bit, CMOS Bipolar dBc /Hz fref = 30 kHz dBc /Hz fref = 100 kHz dBc /Hz fref = 125 kHz dBc/ dBc/ Hz fref Hz fref = 250 kHz = 1000 kHz deg kHz P = 32/33 fref = 800 kHz MHz fref = 1 MHz fref = 2 MHz fRFIN The minimum total divider ratio is only important for continuous frequency step size, if lower divider ratios are used not all frequencies are possible. To find out the missing frequencies our control program for I2C / 3-wire bus may be used. Overall phase noise, fref = 800 kHz, loop filter bandwidth = 25 kHz (Figure 3.1) dBc/ tot 80 84 63 Phase noise Hz 1 kHz offset dBc tot 64 SSB 82 86 /Hz 10 kHz offset dBc/ tot 65 output level = 100 105 Hz 100 kHz offset +10dBm, 2 MHz dBc 66 105 110 / 1 MHz offset tot Hz PLL spurious at baseband outputs IOUT, IOUTi, QOUT, QOUTi ATT 67 PLL spurious -40 dBc fout=1MHz, 1Vpp diff. Synthesizer Phase detector Charge pump output / Vtune input VCPOUT 0.4 68 DC voltage 4.5 V loop locked ICPOUT 69 DC current 1 2 mA 70 Tristate output current ICPOUT 0.1 41 pin 19 1 nA VCPOUT = 2 V pin 21 Specification 2004-02-05 TUA6120 'TORNADO' Version 2.01 Reference Table 4-3 AC/DC Characteristics, TA = 25 C, VVCCA1, VCCA2, VCCD = 5 V (cont'd) Symbol Limit Values min typ max Unit Test Conditions Item # Parameter Synthesizer PLL active loop filter output VLPF1out 0.4 71 DC voltage ILPF1out 72 DC current 10 73 internal pull-up Tuning VCO's 74 Synthesizer VCO 1 75 Synthesizer VCO 2 76 GHz VCO 1 77 GHz VCO 2 Crystal oscillator 78 Crystal frequency 79 Crystal resistance negative input 80 impedance 81 Drive current f R ZXTALIN IQOSZ 1 4 30 420 900 0 0.9 200 1.8 400 1.6 2.4 3.2 0 RLPF1out f f f f 3230 3500 3600 5900 5 VVCC V 5000 A k 3500 3770 6200 8800 MHz MHz MHz MHz internal Pull-up pin 20 connect to VCCD 16 MHz 100 parallel resonance series resonance f = 4 MHz pins 26, 27 Arms f = 4 MHz Reference oscillator input/output -0.2 DC voltage XTALIN V 82 XTALIN see Register 02 on page 50 0 83 XTALIO input 150 VXtalIO voltage, 84 see Register 02 on page 50 1.5 85 XTALIO input impedance RXtalIO 3.0 V preamp enabled 3.0 V preamp disabled 1000 mVpp preamp = on 3.0 Vpp k Vpp Vpp Vpp 3.2 0.1 V mA k k k RL > 1M, Vcc = 5 V, CL = 10 pF preamp = off pin 24 86 XTALIO output VXtalIO 87 voltage 88 see Register 02 on page 50 VXTALOUT 89 XTALOUT VDC 90 91 XTALIO output current IXtalIO RXtalIO RXtalIO RXtalIO see Register 02 on page 50 XTALIO output 92 impedance 93 Specification 1.4 1.2 1.2 42 VXtalIO = 1.8 Vpp VXtalIO = 2.6 Vpp VXtalIO = 3.3 Vpp 2004-02-05 TUA6120 'TORNADO' Version 2.01 Reference Table 4-3 AC/DC Characteristics, TA = 25 C, VVCCA1, VCCA2, VCCD = 5 V (cont'd) Symbol Limit Values min typ max Unit Test Conditions Item # Parameter I2C and 3-Wire-bus Clock, Data, Enable, pins 1, 47, 48 HIGH level input VIH 94 1.30 voltage LOW level input VIL 95 -0.5 voltage LOW level output VOL 96 voltage (DATA), 0 only I2C-bus Hysteresis of Vhys 97 Schmitt trigger 0.2 inputs IH 98 H-input current 99 L-input current 1 VVCC V 0.71 V 0.4 0.6 V VVCC of P in the range 1.8 to 5 V 3 mA sink current 6 mA sink current V 10 A A VI = VVCC VI = GND IL -10 ) VVCC of P in the range 1.8 to 5 V. BUSMODE H-input current 100 H-input voltage L-input current XTALDIV1, XTALDIV2 101 H-input voltage L-input current VH IL 2.8 -60 3.2 V A VI = open VI = GND pins 25, 28 IH VH IL 10 VVCC-1 VVCC -60 A V A VI = VVCC VI = open VI = GND pin 29 ADC clock for AGC = Crystal frequency / ADC clock divider fin 102ADC clock freq. 0.5 1 MHz see Register 02 on page 50 Table 4-4 XTAL divider ratio XTALDIV2 1) XTALDIV1 1) XTAL divider ratio 0 0 1 0 1 2 1 0 4 1 1 8 1) 0: Pin is connected to ground. 1: Pin is open (internal pull up current). Specification 43 2004-02-05 TUA6120 'TORNADO' Version 2.01 Reference 4.2 4.2.1 Bus Interface Addressing Table 4-5 Pin Function BUSMODE Pin Designation Function bus mode select 2 0 I C mode 3-wire mode 1 or open 1) SDA serial data data in/out SCL clock clock in CAS / EN I C: chip address select,3-W: enable 2 four chip addresses 1) 0: chip is addressed see Table 4-6 Chip Address Organization in I2C Mode on page 44, see Table 4-7 Address selection in I2C Mode on page 44. Table 4-6 Chip Address Organization in I2C Mode Name Byte MSB bit6 bit5 bit4 Write Mode Address Byte ADB 1 1 0 0 Read Mode Address Byte ADB 1 1 0 0 Table 4-7 Address selection in I2C Mode MA1 0 0 1 1 MA0 0 1 0 1 bit3 0 0 bit2 MA1 MA1 bit1 LSB MA0 R/W=0 MA0 R/W=1 Voltage at CAS/EN (0 to 0.1) x VCC open circuit or (0.2 to 0.3) x VCC (0.4 to 0.6) x VCC (0.9 to 1) x VCC Chip Address (Hex) Write Mode Read Mode C0 C1 C2 C4 C6 C3 C5 C7 Specification 44 2004-02-05 TUA6120 'TORNADO' Version 2.01 Reference 4.2.2 Sub Addressing Table 4-8 Sub Addresses of Write Data Registers Function Hex MSB S6 S5 S4 A/N Divider 00 0 0 0 0 Reference 01 0 0 0 0 Divider Control Bytes 02 0 0 0 0 Port Byte 03 0 0 0 0 04 0 0 0 0 AGC Mode Baseband 05 0 0 0 0 Control Test Modes 06 0 0 0 0 Table 4-9 Function Status not used RSSI Sub Addresses of Read Data Registers Hex MSB S6 S5 S4 80 1 0 0 0 81 1 0 0 0 82 1 0 0 0 S3 0 0 0 0 0 0 0 S2 0 0 0 0 1 1 1 S1 0 0 1 1 0 0 1 LSB 0 1 0 1 0 1 0 S3 0 0 0 S2 0 0 0 S1 0 0 1 LSB 0 1 0 Specification 45 2004-02-05 TUA6120 'TORNADO' Version 2.01 Reference 4.3 Bus Data Format Table 4-10 Bus Data Format I2C-bus Write Mode Bit STA 1 1 0 0 0 MA0 MA1 0 ACK S7 S6 S5 S4 S3 S2 S1 S0 ACK DX ... D5 D4 D3 D2 D1 D0 ACK STO MSB LSB MSB Function MSB I2C-bus Read Mode Bit STA 1 1 0 0 0 MA0 MA1 0 ACK S7 S6 S5 S4 S3 S2 S1 S0 ACK STA 1 1 0 0 0 MA0 MA1 1 ACK DX ... D5 D4 D3 D2 D1 D0 1 STO LSB MSB Function MSB chip address (Write) chip address (Write) 3W-bus Write Mode Bit S7 S6 S5 S4 S3 S2 S1 S0 Function MSB 3W-bus Read Mode Bit S7 S6 S5 S4 S3 S2 S1 S0 Function MSB sub address (Write) 00H...06H sub address (Read) 80H...82H sub address (Write) 00H...06H sub address (Read) 80H...82H LSB LSB restart MSB LSB LSB data in X...0 (X=7,15 or 23) chip address (Read) LSB LSB MSB DX ... D5 D4 D3 D2 D1 D0 MSB data in X...0 (X=7,15 or 23) LSB DX ... D5 D4 D3 D2 D1 D0 MSB data out X...0 (X=7) LSB 1)after each byte an acknowledge is generated. data out X...0 (X=7) LSB STA: Start condition, STO: Stop condition, ACK: Acknowledge. Specification 46 2004-02-05 TUA6120 'TORNADO' Version 2.01 Reference Table 4-11 I2C Short Read Bus Data Format I2C-bus Read Mode first read Bit STA 1 1 0 0 0 MA0 MA1 0 ACK S7 S6 S5 S4 S3 S2 S1 S0 ACK STA 1 1 0 0 0 MA0 MA1 1 ACK DX ... D5 D4 D3 D2 D1 D0 1 STO Function MSB The first read must have the same format as a single read : - Write chip address (write) - Sub address (write) - Read chip address (write) - Data (read) all following read calls to the same register may have the following short read format : - Read chip address (write) - Data (read) LSB MSB This mode will only be terminated by a new write operation with - Write chip address (write) chip address (Write) sub address (Read) 80H...82H repeated short read to the same register as first read LSB restart MSB STA 1 1 0 0 0 MA0 MA1 1 ACK DX ... D5 D4 D3 D2 D1 D0 1 STO restart MSB chip address (Read) chip address (Read) LSB MSB LSB MSB data out X...0 (X=7) data out X...0 (X=7) LSB LSB Specification 47 repeat loop 2004-02-05 TUA6120 'TORNADO' Version 2.01 Reference 4.4 Write Registers, Data Byte Specification Table 4-12 Data Byte Specification of Write Data Registers Register 00 Subaddress 00H A/N Divider Bits V Function Description Bit Symbol 23 1 reserved must be set to 1 GHz VCO1 is on 0 22 GV GHz VCO switch 1 GHz VCO2 is on 0 Synthesizer VCO Syth. VCO1 is on 21 SV switch Syth. VCO2 is on 1 GN2 GN1GN0 Divider ratio 20 GN2 0 0 0 4 GHz PLL 0 0 1 2 N-counter 1 0 3 0 programmable 19 GN1 0 1 1 4 divider bits 1 0 0 5 1 0 1 6 N = 2 ... 8 18 GN0 1 1 0 7 1 1 1 8 10 17 D17 2 16 D16 29 Synthesizer 15 D15 28 N-counter 27 programmable 14 D14 13 D13 26 divider bits: 25 N = 210 x D17+ ... + 12 D12 11 D11 24 22 x D9 + 21 x D8 + 10 D10 23 D7 9 D9 22 8 D8 21 N = 2 ... 2047 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 20 26 25 24 23 22 21 20 Synthesizer A-counter programmable divider bits: A = 26 x D6 +... + 22 x D2 + 21 x D1 + D0 A = 0 ... 127 Defaults 1 0 1 GN2 GN1 GN0 0 0 1 0 0 0 0 0 1 0 0 1 1 1 0 0 0 0 0 1 0 Default divider ratio N = 39 Default divider ratio A =2 Specification 48 2004-02-05 TUA6120 'TORNADO' Version 2.01 Reference Table 4-12 Data Byte Specification, Write Registers (continued) Register 01 Subaddress 01H Reference Divider Bits V Function Description Bit Symbol 0 forbidden Prescaler 15 MOD divider ratio 1 Div. ratio = 32/33 CP1 CP0 14 CP1 0 1 mA 0 Charge-pump 0 1 1.33 mA current 13 CP0 1 0 1.66 mA 1 1 2 mA Divider ratio 1.) GR2 GR1GR0 0 12 GR2 0 0 4 GHz PLL 0 0 1 2 R-counter 0 1 0 3 programmable 11 GR1 0 1 1 4 divider bits 1 0 0 5 R = 2 ... 8 1 0 1 6 10 GR0 1 1 0 7 1 1 1 8 9 9 R9 2 8 R8 28 Synthesizer R-counter 7 R7 27 programmable 6 R6 26 divider bits: 25 5 R5 R = 29 x R 9+ ... + 4 R4 24 2 2 x R2 + 21 x R1 + 3 R3 23 R0 22 2 R2 1 R1 21 R = 2 ... 1023 0 R0 20 1.) Defaults 1 CP1 CP0 0 0 GR2 GR1 GR0 1 0 0 0 0 0 0 0 1 0 1 1 0 Default divider ratio R = 5 2.) The GHz R/N-counter (register 00 bits 18,19,20; register 01 bits 10,11,12) are Johnson counters which may hang up if they start from a forbidden state. For a 2-3-4-5-6-7-8 counter chain forbidden states can appear at non binary divider values of 3, 5, 6, 7. Whereas the forbidden states in odd counter values correct themselves this will not happen with even counter values. Therefore the remaining counter value of 6 may come into an forbidden state if the programming is switched from a higher value (7 or 8) to 6, because the higher divider values include the forbidden states for counter value of 6. Therefore it is an absolute must to program the counter chain to e.g. 5 (which does not include forbidden states for 6) before it is set from higher values to 6. If this is not done a proper operation of the TUA6120 cannot be guaranteed. Reference frequency is 800 kHz with a 4 MHz crystal. 2.) Specification 49 2004-02-05 TUA6120 'TORNADO' Version 2.01 Reference Table 4-12 Data Byte Specification of Write Data Registers (continued) Register 02 Subaddress 02H Control Bytes Bits V Function Description Defaults Bit Symbol 15 FL1 14 FL0 13 AGCP 12 11 10 9 8 AC4 AC3 AC2 AC1 AC0 ST1 ST0 0 0 0 6 ST0 5 1 1 0 0 1 0 1 0 1 24 23 22 21 20 Lock Flag control if FL0 = 11) Lock detect output as selected by FL11) AGC polarity 2) AGC ADC clock control divider ratio AC = 24 * AC4+...+ 21 *AC1+ AC0, AC = 1 ... 31 Lock Flag at P0 Lock Flag at P1 Lock Flag not at port Lock Flag at port positive AGC slope negative AGC slope ADC clock for AGC = Crystal frequency / ADC clock divider ratio 0 0 0 7 ST1 QB1 1 1 QB1 QB0 0 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 4 QB0 0 1 0 AGC,ADC cycle time = 0 1/9 of ADC clock 0 ST1 Normal mode 0 Stand-by and Loop- Normal mode, but loop thru off thru control Stand-by but LNA and loop-thru on Total stand-by QB1 XTAL is input Output level = 1.8 Vpp XTAL I/O control 0 Output level = 2.6 Vpp Output level = 3.3 Vpp Quartz I/O input level Preamp = off 3) Default divider ratio AC = 8 ST0 0 QB0 1 3 QIL 2 PDP 1 CPT 0 OS 1) 2) 3) 0 Preamp = on Polarity = negative Phase-detector polarity control Polarity = positive Charge-pump control Charge-pump = on 4) Charge-pump = off LPF1OUT = off LPF1OUT on/off LPF1OUT = on 1 0 0 Port is switched to tristate if used as lock flag output. The port sinks current if the flag is set. Only valid if AGC is external, otherwise Table "Register 04" on Page 51 Preamp = on is only allowed if XTAL I/O control is input (register 02, bits 4,5 = 0) more Table "XTALIO input" on Page 42 If not in test mode, otherwise Table "Register 06" on Page 53. 4) Specification 50 2004-02-05 TUA6120 'TORNADO' Version 2.01 Reference Table 4-12 Data Byte Specification of Write Data Registers (continued) Register 03 Subaddress 03H Port Byte Bits V Function Description Defaults Bit Symbol 0 7 P7 6 P6 0 5 P5 0 not used 0 4 P4 3 P3 0 2 P2 0 Port 1 current is off 0 0 1 P1 1 Port 1 current is on Port control 0 Port 0 current is off 0 P0 0 1 Port 0 current is on Register 04 Subaddress 04H AGC Mode Bit Symbol Bits 7 AI1 AI1 AI0 0 6 AI0 0 1 1 5 AL3 4 AL2 3 AL1 2 AL0 1 0 not used 0 1 0 1 AGC current V Function Description Isource = 20 A = constant Isink = 150 nA Isink = 300 nA Isink = 450 nA Isink = 600 nA if AL3 = 1, AL2 = 1, AL1 = 1, AL0 = 0: AGC is external, otherwise AGC is internal Defaults AI1 AI0 0 0 AGC control 0 0 0 0 0 0 Specification 51 2004-02-05 TUA6120 'TORNADO' Version 2.01 Reference Table 4-12 Data Byte Specification of Write Data Registers (continued) Register 05 Subaddress 05H Baseband Control Bits V Function Description Defaults Bit Symbol not used 0 7 F1 F0 F1 F0 6 F1 0 0 Full bandwidth 0 0 Base-band filter 1 11 MHz 0 roll-off 1 0 33 MHz 5 F0 1 1 22 MHz BB amps = on 0 Base-band 0 4 ED amplifier control 1 BB amps = off GA2 GA1 GA0 GA2 GA1 GA0 0.5 Vpp 0 0 0 3 GA2 0.75 Vpp 0 0 1 0 2 GA1 0 1 1 1 GA0 1 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 I/Q output level, differential 1.0 Vpp 1.25 Vpp 1.5 Vpp 1.75 Vpp 2.0 Vpp not used Xtal output = on Xtal output control Xtal output = off 0 0 1 0 0 XO Specification 52 2004-02-05 TUA6120 'TORNADO' Version 2.01 Reference Table 4-12 Data Byte Specification of Write Data Registers (continued) Register 06 Subaddress 06H Test Modes Bits V Function Description Defaults Bit Symbol not used 0 7 ABL ABL ABL ABL 2 1 2 1 6 ABL2 ABL pulse for 0 0 1.7 ns 1) 2.5 ns 0 1 0 1 phase detector 5 ABL1 1 0 3.8 ns 1 1 5.8 ns Charge-pump = bipolar 0 0 4 CPM 1 Charge-pump = monopolar Charge-pump = sinking 0 0 current, if CPM = 1 Charge-pump 3 CPP control Charge-pump = sourcing 1 current if CPM = 1 0 Charge-pump = on 0 2 CPT 1 Charge-pump = off (tristate) 1 PIO 0 TED 1) 2) 0 1 0 1 Test frequency control Testmode control P0, P1 are input for fref, fdiv 2) P0, P1 are output for fref, fdiv Testmode disabled Testmode enabled 1 0 ABL bits are independent of testmode control bit TED. I/O for fref is P0, I/O for fdiv is P1. fref is the output frequency of the R-counter and fdiv the output frequency of theN-counter. Specification 53 2004-02-05 TUA6120 'TORNADO' Version 2.01 Reference 4.5 Read Registers, Data Byte Specification Table 4-13 Data Byte Specification of Read Data Registers Register 80 Subaddress 80H Status Bit Symbol Bits Function Description Defaults 1) 7 POR POR = 1 if power-on reset power-on flag 6 FL lock-in flag FL = 1 if loop is locked STBY3 = 0 if loop through is on. 5 STBY3 stand-by flag 3 Default is loop through on STBY2 = 0 if LNA is on. 4 STBY2 stand-by flag 2 Default is LNA on STBY1=0 if direct converter is on. 3 STBY1 stand-by flag 1 Default is direct converter on AGC = 1 if AGC is external. 2 AGC AGC flag As default AGC is in internal mode 1 not used 1 0 1 1) The power-on flag is reset after a read operation. Register 82 Subaddress 82H RSSI Bit Symbol Bits 7 RS7 6 RS6 5 RS5 4 RS4 3 RS3 2 RS2 1 RS1 0 RS0 Function 27 26 25 24 23 22 21 20 RSSI (Field-strength indicator) RSSI = 0 ... 127 not used Description RSSI = 27x RS7+ 26x RS6+...+ 21x RS1 Defaults 0 0 0 without 0 input 0 signal 0 0 0 Specification 54 2004-02-05 TUA6120 'TORNADO' Version 2.01 Reference 4.6 VCO band switching table Table 4-14 VCO band switching fRFIN Synth. SV GHz GV GHz N- GHz RGHz GHz R-counter 2) Band [MHz] VCO1) bit VCO bit divider divider N-counter 1) 1) 1) 1) ratio 1) ratio 2) GN2 GN1 GN0 GR2 GR1 GR0 915 1 2 1 8 1 1 1 935 935 2 1 0 1000 7 1 1 0 1000 1 0 1 3 2 2 0 1080 1080 4 1 0 1167 1 0 6 1 0 1 1167 5 2 1 1255 1255 6 1 0 1313 8 1 1 1 1313 2 1 7 1415 1415 8 0 1 1500 7 0 1 0 1 1 0 3 1500 9 2 1 1615 1615 10 0 1 1750 6 1 0 1 1750 11 2 1 1885 1 2 1885 1 0 12 2000 7 1 1 0 2000 13 2 1 4 0 1 1 2155 2155 1 0 6 1 0 1 14 2185 1) 2) see Register 00 on page 48. see Register 01 on page 49. Remark: The total input frequency range is divided into 14 bands. The crossover frequency of the GHz VCO's, 1500 MHz, is in bold italic letters. After power-on the band 3 is selected as default. Specification 55 2004-02-05 TUA6120 'TORNADO' Version 2.01 Reference 4.7 VCO band splitting 6\QWK 9&2 6\QWK 9&2 0+] 0+] 0+] 0+] 0+] 0+] 0+] ,QSXW )UHTXHQF\ >0+]@ 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] )UHTXHQF\ RI 6\QWKHVL]HU 9&2 >0+]@ Figure 4-1 VCO band splitting Specification 56 2004-02-05 *+] 9&2 0+] 0+] *+] 9&2 TUA6120 'TORNADO' Version 2.01 Reference 4.8 Bus Timing BUSMODE = 0 tBUF SDA tLOW tR SCL P S tHD.STA tHD.DAT tHIGH tSU.DAT tHD.STA S tSU.STA tSU.STO P tF tSP S - START condition P - STOP condition Figure 4-2 I2C Bus BUSMODE = 1 DATA tLOW tR CLOCK tWHEN ENABLE S tSU.SCLENA P tSU.SCLENA tHD.STA tHD.DAT tHIGH tSU.DAT tSU.STO tF tSP Figure 4-3 3-Wire Bus Specification 57 2004-02-05 TUA6120 'TORNADO' Version 2.01 Reference Table 4-15 Bus Timing No Parameter 1 2 3 4 LOW level input voltage (SDA, SCL, CAS/EN, BUSMODE) HIGH level input voltage (SDA, SCL, CAS/EN, BUSMODE) Hysteresis of Schmitt trigger inputs Pulse width of spikes which must be suppressed by the input filter LOW level output voltage (SDA), only I2C-bus at 3mA sink current at 6mA sink current Output fall time from VIH min to VIL max with a bus capacitance from 10pF to 400pF with up to 3mA sink current at VOL Symbol VIL VIH VHys tSP Limit Values min max -0.5 1.3 0.2 0 50 0.71 5.5 Unit V V V ns 5 VOL tOF fSCL tBUF tHD.STA tLOW tHIGH tSU.STA tHD.DAT tSU.DAT tR, tF tSU.STO tSU.SCLEN A 0 20+0.1Cb1) 0 1.3 0.6 1.3 0.6 0.6 0 100 20+0.1Cb1) 0.6 0.6 0.6 -- 0.4 0.6 250 400 300 400 V V ns kHz s s s s s ns ns ns s s s pF 6 7 SCL clock frequency Bus free time between a STOP and START 8 condition 2) Hold time (repeated) START/ENABLE ON 9 condition. After this period, the first clock pulse is generated. 10 LOW period of the SCL clock pulse 11 12 13 14 15 16 HIGH period of the SCL clock pulse Set-up time for a repeated START condition 2) Data hold time Data set-up time Rise time, fall time of SDA and SCL signals Set-up time for STOP/ENABLE OFF condition 17 Setup time SCL to CAS/EN 18 H-pulse width (CAS/EN) for new data protocol 3) tWHEN Cb 19 Capacitive load for each bus line 1) Cb = capacitance of one bus line in pF. Note that the maximum tF for the SDA and SCL bus lines quoted in table above (300ns) is longer than the specified maximum tOF for the output stages (250ns).This allows series protection resistors to be connected between the SDA/SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tF. only for I2C bus mode. 2) Specification 58 2004-02-05 TUA6120 'TORNADO' Version 2.01 Reference 4.9 Electrical Diagrams 4.9.1 Current consumption vs. Vcc In this measurement the TUA6120 starts with the power on reset settings. PLL tuned to 1000 MHz (Crystal = 4MHz, Fref = 800kHz), Baseband filter off, other settings see 4.4 Write Registers, Data Byte Specification on page 48. Power on reset & ,FF >9@ Vref start-up 9FF >9@ Specification 59 2004-02-05 TUA6120 'TORNADO' Version 2.01 Reference 4.9.2 RF input impedance, Smith diagram 35 40 45 50 30 75 10 0 25 20 15 15 0 200 250 100 150 200 250 500 10 15 20 25 30 35 40 45 50 75 0 1k 1k 2.2 G 1.5 G 10 800 M 15 20 25 30 35 40 45 4.9.3 RF input return loss vs. input frequency 5HWXUQ /RVV >G%@ normalised to 50 50 ,QSXW )UHTXHQF\ >0+]@ 75 10 0 Specification 60 500 5 5 250 200 15 0 10 5 500 1k 2004-02-05 TUA6120 'TORNADO' Version 2.01 Reference 4.9.4 Noise figure vs. input frequency (YDOXDWLRQ ERDUG 5HY 1RLVHILJXUH G% ,QSXW )UHTXHQF\ 0+] 4.9.5 S/N vs. input level #0+] RXWSXW OHYHO FRQVW G%P XQEDODQFHG 61 5DWLR G% ,QSXW /HYHO G%P Specification 61 2004-02-05 TUA6120 'TORNADO' Version 2.01 Reference 4.9.6 ,QSXW /HYHO G%P RF input range RXWSXW OHYHO 9SS XQEDODQFHG PHDVXUHG LQ HYDOXDWLRQ ERUG 5HY 3LQ PLQ G%P 3LQ PD[ G%P ,QSXW )UHTXHQF\ 0+] 4.9.7 Input level vs. AGC voltage $*& SRVLWLYH VORSH 0+] ,QSXW OHYHO >G%P@ $*& YROWDJH >9@ Specification 62 2004-02-05 TUA6120 'TORNADO' Version 2.01 Reference 4.9.8 RF output impedance, Smith diagram 35 40 45 50 30 75 10 0 25 20 15 15 0 200 250 100 150 200 250 500 10 15 20 25 30 35 40 45 50 75 0 1k 5 800 M 5 1.5 G 250 10 2.2 G 15 20 25 30 35 40 45 4.9.9 1. Baseband output impedance, Smith diagram 35 40 45 50 50 30 75 75 25 10 0 10 0 15 15 0 200 250 100 M 30 M 100 150 200 250 500 10 15 20 25 30 35 40 45 50 75 1k 1k 500 1k 0 100 k 250 10 15 20 25 30 35 40 45 Specification 63 50 75 10 0 500 5 5 1k 500 200 200 15 15 0 0 20 10 10 5 5 500 1k 2004-02-05 TUA6120 'TORNADO' Version 2.01 Reference 4.9.10 2. Baseband output impedance, Smith diagram 35 40 45 50 30 75 10 0 25 20 15 15 0 200 250 100 150 200 250 10 15 20 25 30 35 40 45 50 75 0 100 k 5 100 k 1k 1k 5 100 M 500 15 20 25 30 35 40 45 4.9.11 2. Baseband output-inverted impedance, Smith diagram 35 40 45 50 50 30 75 75 25 10 0 10 0 15 15 0 200 30 M 10 15 20 25 5 100 M 100 30 35 40 45 50 75 100 ser. resistor 150 200 250 500 0 100 k 5 100 k 1k 1k 30 M 100 M 15 20 25 30 35 40 45 Specification 64 50 75 10 0 250 10 500 250 10 250 500 200 200 15 15 0 0 20 10 100 M 30 M 30 M 100 ser. resistor 500 1k 10 5 5 500 1k 2004-02-05 TUA6120 'TORNADO' Version 2.01 Reference 4.9.12 I-Q Impairments %DVH EDQG VLJQDO 0+] G%P *DLQ >5) OHYHO *DLQ >5) OHYHO G%P@ G%P@ G%P@ G%P@ *DLQ >5) OHYHO *DLQ >5) OHYHO ,4 *DLQ >G%@ 5) ,QSXW )UHTHQF\ >0+]@ %DVH EDQG VLJQDO 0+] G%P 3KDVH >5) OHYHO 3KDVH >5) OHYHO G%P@ G%P@ G%P@ G%P@ 3KDVH >5) OHYHO 3KDVH >5) OHYHO ,4 3KDVH >'HJUHH@ 5) ,QSXW )UHTHQF\ >0+]@ Specification 65 2004-02-05 TUA6120 'TORNADO' Version 2.01 Reference 4.9.13 Second order intermodulation input related (IIP2) ,,3 DW 3X G%P 3X 3 XQGHVLUHG ! FRQVWDQW 3G 3 GHVLUHG ! YDULDEOH ,,3 >G%P@ ,,3B ,,3B 3G >G%P@ 4.9.14 Third order intermodulation input related (IIP3) %% ILOWHU 0+] 21 0+= 5HO ,,3 5HO ,,3 >G%@ 0+= ,,3 0+= ,,3 3LQ >G%P@ Specification 66 2004-02-05 ,,3 >G%P@ 0+] 5HO ,,3 TUA6120 'TORNADO' Version 2.01 Reference 4.9.15 Phasenoise 3KDVHQRLVH # RXWSXW OHYHO G%P *DLQ PLQ &U\VWDO 0+] )UHI N+] )RXW 0+] /RRSILOWHU N+] (9$%RDUG UHY #N+] #N+] #N+] #0+] ,FS VZLWFKLQJ >G%F@ P$ P$ P$ P$ P$ P$ P$ P$ P$ P$ P$ P$ LQSXW IUHTXHQF\ >0+]@ P$ P$ 4.9.16 Frequency response of base band filter both base band amplifiers in series, coupling capacitor 220 nF %DVHEDQGILOWHU 0+] G% 0+] P$ Specification 67 2004-02-05 TUA6120 'TORNADO' Version 2.01 Reference %DVHEDQGILOWHU 0+] G% 0+] %DVHEDQGILOWHU 0+] G% 0+] Specification 68 2004-02-05 TUA6120 'TORNADO' Version 2.01 Table of Contents page 1 1.1 1.2 1.3 1.4 2 2.1 2.2 2.3 2.4 2.5 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 2.5.6 2.5.7 2.5.8 2.5.9 2.5.10 2.5.11 2.5.12 2.6 2.6.1 3 3.1 3.2 4 4.1 4.1.1 4.1.2 4.1.3 4.2 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Pin Definitions and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Frequency programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGC-System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LNA and RF-Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PGA and I/Q-Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baseband Amplifiers and Filters . . . . . . . . . . . . . . . . . . . . . . . . Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Oscillator Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . Synthesizer Loop filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synthesizer VCO's . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phase Shift 0x / 90x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GHz VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 23 24 24 24 24 24 24 25 25 25 25 25 GHz PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Functional GHz PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . 28 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Phase noise performance of application . . . . . . . . . . . . . . . . . . . . 30 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 35 37 38 Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 69 2004-02-05 Specification TUA6120 'TORNADO' Version 2.01 Table of Contents page 4.2.1 4.2.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.9.1 4.9.2 4.9.3 4.9.4 4.9.5 4.9.6 4.9.7 4.9.8 4.9.9 4.9.10 4.9.11 4.9.12 4.9.13 4.9.14 4.9.15 4.9.16 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Sub Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Bus Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Write Registers, Data Byte Specification . . . . . . . . . . . . . . . . . . . . 48 Read Registers, Data Byte Specification . . . . . . . . . . . . . . . . . . . 54 VCO band switching table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 VCO band splitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Electrical Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Current consumption vs. Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 RF input impedance, Smith diagram . . . . . . . . . . . . . . . . . . . . . 60 RF input return loss vs. input frequency . . . . . . . . . . . . . . . . . . 60 Noise figure vs. input frequency . . . . . . . . . . . . . . . . . . . . . . . . 61 S/N vs. input level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 RF input range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Input level vs. AGC voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 RF output impedance, Smith diagram . . . . . . . . . . . . . . . . . . . . 63 1. Baseband output impedance, Smith diagram . . . . . . . . . . . . 63 2. Baseband output impedance, Smith diagram . . . . . . . . . . . . 64 2. Baseband output-inverted impedance, Smith diagram . . . . . 64 I-Q Impairments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Second order intermodulation input related (IIP2) . . . . . . . . . . . 66 Third order intermodulation input related (IIP3) . . . . . . . . . . . . . 66 Phasenoise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Frequency response of base band filter both base band amplifiers in series, coupling capacitor 220 nF 67 Specification 70 2004-02-05 |
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