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D a ta S h e e t , V 1 . 0, S ep t e mb e r 20 0 5
SPIDER - TLE 7232G
SPI Driver for Enhanced Relay Control Eight Channel Low-Side Switch
Automotive Power
SPI Driver for Enhanced Relay Control SPIDER - TLE 7232G
Table of Contents
Page
Product Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.2 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.1 Pin Assignment SPIDER - TLE 7232G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4 Block Description and Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . .11 4.1 Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.1.1 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1.2 Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1.3 Inductive Output Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1.4 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1.5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1.6 Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4.2.1 Over Load Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.2 Over Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.3 Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2.5 Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.3 Diagnostic Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 4.3.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.3.2 Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.4 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 4.4.1 SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.4.2 Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.4.3 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.4.4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.4.5 SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.4.6 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5 Package Outlines SPIDER - TLE 7232G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
6 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Data Sheet
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SPI Driver for Enhanced Relay Control
SPIDER - TLE 7232G
The SPIDER - TLE 7232G is an eight channel lowside power switch in P-DSO-24-3 package providing embedded protective functions. It is especially designed for standard relays in automotive applications. A serial peripheral interface (SPI) is utilized for control and diagnosis of the device and the load. For direct control, there is an input pin available. The power transistors are built by N-channel vertical power MOSFETs. The device is monolithically integrated in Smart Power Technology.
P-DSO-24-3
Product Summary
Supply voltage Supply voltage for SO buffer On-State resistance at 25 C Nominal load current Over load current limitation Output leakage current per channel at 25 C Drain to source clamping voltage SPI clock frequency
Vdd VVSO RDS(ON, max) IL(nom, max) IDS(LIM, min) IDS(OFF, max) VDS(CL, min) fSCLK(max)
4.5 ... 5.5 V 3.0 ... 5.5 V 1.2 240 mA 1A 1 A 48 V 5 MHz
Type SPIDER - TLE 7232G
Data Sheet
Ordering Code SP0000-89034
3
Package P-DSO-24-3
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SPI Driver for Enhanced Relay Control SPIDER - TLE 7232G
Basic Features
* * * * * 16 bit SPI for diagnostics and control SPI providing daisy chain capability 3.3 V and 5 V compatible SPI A configurable input pin offers complete flexibility for PWM operation Stable behavior at under voltage
Protective Functions
* * * * Short circuit protection Over load protection, configurable behavior (limitation or shutdown) Thermal shutdown, configurable behavior (latch or restart) Electrostatic discharge protection (ESD)
Diagnostic Functions
* * * * * Diagnostic information via SPI Open load detection in OFF-state Shorted to GND detection in OFF-state Over temperature in ON-state Over load in ON-state
Applications
* Especially designed for driving relays in automotive applications * All types of capacitive, resistive and inductive loads
Data Sheet
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SPI Driver for Enhanced Relay Control SPIDER - TLE 7232G
Overview
1
Overview
The SPIDER - TLE 7232G is an eight channel low-side relay switch (1.2 per channel) in P-DSO-24-3 package providing embedded protective functions. The 16 bit serial peripheral interface (SPI) is utilized for control and diagnosis of the device and the loads. The SPI interface provides daisy-chain capability in order to assemble multiple devices in one SPI chain by using the same number of micro-controller pins. The SPIDER - TLE 7232G is equipped with one input pin that can be individually routed to the output control of each channel thus offering complete flexibility in design and PCBlayout. The input mapping as well as the boolean operation between input signal an output control signal is configured via SPI. The device provides full diagnosis of the load, which is open load, short to GND as well as short circuit to Vbat detection and over load / over temperature indication. The SPI diagnosis flags indicate latched fault conditions that may have occurred. Each output stage is protected against short circuit. In case of over load, the current of the affected channel is limited. There is a temperature sensor available for each channel to protect the device in case of over temperature. The shut down behavior in case of over load or over temperature can be configured via SPI for each channel individually.
1.1
Block Diagram
VDD OUT0 OUT1 IN input map boolean operation output control OUT2 OUT3 OUT4 OUT5 temperature sensor control, diagnostic and protective functions short circuit detection gate control open load detection OUT6 OUT7
RST CS SCLK SI VSO SO
reset / stand-by
SPI
hardware configuration
output monitor diagnosis register
GND
Overview .emf
Figure 1
Data Sheet
Block Diagram
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SPI Driver for Enhanced Relay Control SPIDER - TLE 7232G
Overview
1.2
Terms
Following figure shows all terms used in this data sheet.
Vbat
Idd Vdd V VSO VRST VIN V CS IVSO IRST IIN ICS ISCLK
VDD VSO RST IN CS SCLK SI SO GND IGND
OUT0 OUT1
I D0 I D1 I D2 I D3 I D4 I D5 I D6 I D7 V DS0 V DS1 V DS2 V DS3 V DS4 VDS5 VDS6 VDS7
SPIDER TLE 7232G
OUT2 OUT3 OUT4 OUT5 OUT6 OUT7
VSCLK ISI VSI VSO ISO
Terms.emf
Figure 2
Terms
In all tables of electrical characteristics is valid: Channel related symbols without channel number are valid for each channel separately (e.g. VDS specification is valid for VDS0 ... VDS7). All SPI register bits are marked as follows: ADDR.PARAMETER (e.g. CTL.OUT0). In SPI register description, the values in bold letters (e.g. 0) are default values.
Data Sheet
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SPI Driver for Enhanced Relay Control SPIDER - TLE 7232G
Pin Configuration
2
2.1
Pin Configuration
Pin Assignment SPIDER - TLE 7232G
(top view)
CS IN OUT2 OUT3 GND GND GND GND OUT4 OUT5 VSO SO
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
RST VDD OUT1 OUT0 GND GND GND GND OUT7 OUT6 SI SCLK
P-DSO-24.emf
Figure 3
Pin Configuration P-DSO-24-3
2.2
Pin 23 11
Pin Definitions and Functions
Symbol VDD VSO I/O - - - Function Power supply Power supply for SO buffer Ground
Power Supply
5, 6, 7, 8, GND 17, 18, 19, 20 Power Stages 21 22 3
Data Sheet
OUT0 OUT1 OUT2
O O O
Drain of power transistor channel 0 Drain of power transistor channel 1 Drain of power transistor channel 2
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SPI Driver for Enhanced Relay Control SPIDER - TLE 7232G
Pin Configuration Pin 4 9 10 15 16 Inputs 24 2 SPI 1 13 14 12 CS SCLK SI SO I I I O SPI Chip select (active low) Serial clock Serial data in Serial data out RST IN I I Reset input pin (active low) Input multiplexer input pin Symbol OUT3 OUT4 OUT5 OUT6 OUT7 I/O O O O O O Function Drain of power transistor channel 3 Drain of power transistor channel 4 Drain of power transistor channel 5 Drain of power transistor channel 6 Drain of power transistor channel 7
Data Sheet
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SPI Driver for Enhanced Relay Control SPIDER - TLE 7232G
Electrical Characteristics
3
3.1
Electrical Characteristics
Maximum Ratings
Stresses above the ones listed here may affect device reliability or may cause permanent damage to the device. Unless otherwise specified: Vdd = 4.5 V to 5.5 V, Tj = -40 C to 150 C Pos. Parameter Symbol Limit Values min. Power Supply 3.1.1 3.1.2 3.1.3 Power supply voltage max. 5.5 20 28 Unit Test Conditions V
1)
short circuit protection (single pulse) Power Stages 3.1.4 3.1.5 3.1.6 Load current
Vdd VSO supply voltage VVSO Power supply voltage for full Vbat(SC)
-0.3 -0.3 0
Vdd + 0.3 V
V
OVL = 0 2) OVL = 1
ID Voltage at power transistor VDS Maximum energy EAS
dissipation one channel single pulse
-1
1 48
A V mJ
3)
65 30 Maximum energy dissipation one channel repetitive pulses 1 * 104 cycles 1 * 106 cycles Logic Pins 3.1.7 3.1.8 3.1.9 3.1.10 Voltage at input pin Voltage at reset pin Voltage at chip select pin Voltage at serial clock pin
Tj(0) = 85 C ID(0) = 0.35 A Tj(0) = 150 C ID(0) = 0.25 A
mJ
3)
EAR
18 13
Tj(0) = 150 C ID(0) = 0.20 A ID(0) =0.17 A
V V V V
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VIN VRST VCS VSCLK
9
-0.3 -0.3 -0.3 -0.3
5.5 5.5 5.5 5.5
Data Sheet
SPI Driver for Enhanced Relay Control SPIDER - TLE 7232G
Electrical Characteristics Unless otherwise specified: Vdd = 4.5 V to 5.5 V, Tj = -40 C to 150 C Pos. 3.1.11 Parameter Voltage at serial input pin Symbol Limit Values min. max. 5.5 5.5 150 60 -55 -2 150 2 -0.3 -0.3 -40 Unit Test Conditions V V C C C kV according to EIA/JESD 22-A 114B
VSI 3.1.12 Voltage at serial output pin VSO
Temperatures 3.1.13 Junction Temperature Dynamic temperature increase while switching Storage Temperature ESD susceptibility HBM
3.1.14 3.1.15 3.1.16
Tj Tj Tstg VESD
ESD Susceptibility
1) Vdd + 0.3 V < 5.5 V 2) Details on configuration of protective function OLCR.OVL can be found in Section 4.2.5 3) Pulse shape represents inductive switch off: ID(t) = ID(0) x (1 - t / tpulse); 0 < t < tpulse
Data Sheet
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SPI Driver for Enhanced Relay Control SPIDER - TLE 7232G
Block Description and Electrical Characteristics
4
4.1
Block Description and Electrical Characteristics
Power Stages
The SPIDER - TLE 7232G is an eight channel low-side relay switch. The power stages are built by N-channel vertical power MOSFET transistors.
4.1.1
Power Supply
The SPIDER - TLE 7232G is supplied by power supply line Vdd which is used for the digital as well as the analog functions of the device including the gate control of the power stages. There is a power-on reset function implemented for the supply line. After start-up of the power supply, all SPI registers are reset to their default values. A capacitor at pins VDD to GND is recommended. The voltage at pin VSO is used by the driver of the SO line at the SPI. It is designed to be functional at a wide voltage range. There is a reset pin available. At low level at this pin, all registers are set to their default values and the quiescent supply current is minimized.
4.1.2
Input Circuit
There is an input pin available at SPIDER - TLE 7232G to control the output stages.
channel 2 channel 1 channel 0
IN IIN MAP0 OUT0
OR
& BOL0
gate control
SLE0
channel 7 channel 6 channel 5 channel 4 channel 3
OR
& OUT3 BOL3 MAP3
gate control
SLE3
InputLogic.emf
Figure 4
Data Sheet
Input Mapping and Boolean Operator
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SPI Driver for Enhanced Relay Control SPIDER - TLE 7232G
Block Description and Electrical Characteristics The input signal can be configured to be used as control signal of the output stages for each channel separately. The channels 0 to 3 differ from the channels 4 to 7 in the mapping behavior. Please refer to Figure 4 for details. The current sink to ground at the input pin ensures that the channels switch off in case of open pin. The zener diode protects the input circuit against ESD pulses.
4.1.3
Inductive Output Clamp
When switching off inductive loads, the potential at pin OUT rises to VDS(CL) potential, because the inductance intends to continue driving the current. The voltage clamping is necessary to prevent destruction of the device, see Figure 5 for details. Nevertheless, the maximum allowed load inductance is limited.
V bat ID VDS L, RL
OUT VDS(CL)
GND
OutputClamp .emf
Figure 5
Output Clamp Implementation
Maximum Load Inductance
During demagnetization of inductive loads, energy has to be dissipated in the SPIDER TLE 7232G. This energy can be calculated with following equation:
V bat - V DS(CL) RL ID L E = V DS(CL) ----------------------------------- ln 1 - ----------------------------------- + I D -----RL RL V bat - V DS(CL)
The equation simplifies under the assumption of RL = 0: V bat 2 1 E = -- LI D 1 - ----------------------------------- 2 V bat - V DS(CL)
(1)
(2)
The energy, which is converted into heat, is limited by the thermal design of the component.
Data Sheet 12 V1.0, 2005-09-30
SPI Driver for Enhanced Relay Control SPIDER - TLE 7232G
Block Description and Electrical Characteristics
4.1.4
Timing Diagrams
The power transistors are switched on and off with a dedicated slope via the OUT bits of the serial peripheral interface SPI. The switching times tON and tOFF are designed equally.
CS
SPI: ON tON
SPI: OFF tOFF t
VDS
80%
20%
t
SwitchOn.emf
Figure 6
Switching a Resistive Load
When the input mapping is configured accordingly, a high signal at the input pin is equivalent to a SPI ON command.
Data Sheet
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SPI Driver for Enhanced Relay Control SPIDER - TLE 7232G
Block Description and Electrical Characteristics
4.1.5
Electrical Characteristics
Unless otherwise specified: Vdd = 4.5 V to 5.5 V, Tj = -40 C to 150 C typical values: Vdd = 5.0 V, Tj = 25 C Pos. Parameter Symbol Limit Values min. Power Supply 4.1.1 4.1.2 4.1.3 Power supply voltage Vdd Power supply current Idd(ON) Power supply reset current 4.5 3 5.5 5 10 V mA A all channels ON typ. max. Unit Test Conditions
Idd(RST)
VRST = 0 V VIN = 0 V VSCLK = 0 V VSI = 0 V VCS = Vdd
4.1.4
Power-on reset threshold voltage On-State resistance per channel
Vdd(PO)
4.5
V
Output Characteristics 4.1.5
RDS(ON)
1.0 1.2 2.1 1 2 5 48 60
4.1.6
Output leakage current in stand-by mode (per channel) Output clamping voltage L level of pin IN H level of pin IN
ID(RST)
A
IL = 300 mA Vdd = 5 V Tj = 25 C 1) Tj = 150 C VDS = 13.5 V Tj = 25 C 1) Tj = 125 C Tj = 150 C 1)
4.1.7
VDS(CL)
V
Input Characteristics 4.1.8 4.1.9
VIN(L) VIN(H)
VIN
0 2.0 0.1 10 20 50
1.0
V V V
1)
Vdd
4.1.10 Input voltage hysteresis at pin IN
4.1.11 L-input pull-down IIN(L) current through pin IN 4.1.12 H-input pull-down IIN(H) current through pin IN
100 100
A A
1)
VIN = 1 V VIN = 5 V
Data Sheet
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SPI Driver for Enhanced Relay Control SPIDER - TLE 7232G
Block Description and Electrical Characteristics Unless otherwise specified: Vdd = 4.5 V to 5.5 V, Tj = -40 C to 150 C typical values: Vdd = 5.0 V, Tj = 25 C Pos. Reset Parameter Symbol Limit Values min. typ. max. 1 V V A A Unit Test Conditions
VRST(L) 4.1.14 H level of pin RST VRST(H) 4.1.15 L-input pull-up current IRST(L)
4.1.13 L level of pin RST through pin RST 4.1.16 H-input pull-up current through pin RST Thermal Resistance 4.1.17 Junction to ambient all channels active Timings 4.1.18 Power-on wake up time 4.1.19 Reset duration 4.1.20 Turn-on time VDS = 20% Vbat
0 2 0 20 50
Vdd
10 100
VRST = 1 V VRST = 2 V
IRST(H)
Rthja
75
K/W
1) 2)
twu(PO) tRST(L) tON
10
200
s s s
15 60 4.1.21 Turn-off time VDS = 80% Vbat
resistive load SLE = 0 SLE = 1 s
Vbat = 14 V IDS = 300 mA,
tOFF
15 60
resistive load SLE = 0 SLE = 1
Vbat = 14 V IDS = 300 mA,
1) Not subject to production test, specified by design 2) Device mounted on PCB (100 mm x 100 mm x 1.5 mm). PCB without blown air. All channels with balanced loads.
Note: Characteristics show the deviation of parameter at the given supply voltage and junction temperature. Typical values show the typical parameters expected from manufacturing.
Data Sheet
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SPI Driver for Enhanced Relay Control SPIDER - TLE 7232G
Block Description and Electrical Characteristics
4.1.6
Command Description
Reset Value: 08H
3 MAP3 rw 2 MAP2 rw 1 MAP1 rw 0 MAP0 rw
IMCR Input Mapping Configuration Register
7 MAP7 rw 6 MAP6 rw 5 MAP5 rw 4 MAP4 rw
Field MAPn (n = 7-0)
Bits n
Type Description rw Input Mapping Configuration Channel n 0 Channel n can not be controlled with input pin (default value). 1 Channel n can be controlled with input pin, depending on additional set-up.
BOCR Boolean Operator Configuration Register
7 BOL7 rw 6 BOL6 rw 5 BOL5 rw 4 BOL4 rw 3 BOL3 rw 2 BOL2 rw
Reset Value: 00H
1 BOL1 rw 0 BOL0 rw
Field BOLn (n = 7-0)
Bits n
Type Description rw Boolean Operator Configuration Channel n 0 Logic "OR" for channel n (default value). 1 Logic "AND" for channel n.
Data Sheet
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SPI Driver for Enhanced Relay Control SPIDER - TLE 7232G
Block Description and Electrical Characteristics SRCR Slew Rate Configuration Register
7 SLE7 rw 6 SLE6 rw 5 SLE5 rw 4 SLE4 rw 3 SLE3 rw 2 SLE2 rw
Reset Value: 00H
1 SLE1 rw 0 SLE0 rw
Field SLEn (n = 7-0)
Bits n
Type Description rw Slew Rate Configuration Channel n 0 Channel n is switched fast (default value). 1 Channel n is switched slowly.
CTL Output Control Register
7 OUT7 rw 6 OUT6 rw 5 OUT5 rw 4 OUT4 rw 3 OUT3 rw 2 OUT2 rw
Reset Value: 00H
1 OUT1 rw 0 OUT0 rw
Field OUTn (n = 7-0)
Bits n
Type Description rw Output Control Channel n 0 Channel n is switched off (default value). 1 Channel n is switched on, depending on additional set-up.
Data Sheet
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SPI Driver for Enhanced Relay Control SPIDER - TLE 7232G
Protection Functions
4.2
Protection Functions
The device provides embedded protective functions. Integrated protection functions are designed to prevent IC destruction under fault conditions described in this data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are not designed for continuous repetitive operation. There is an over load and over temperature protection implemented in the SPIDER TLE 7232G. The behavior of the protective functions can be set-up via SPI. Following figure gives an overview about the protective functions.
IN OVTn OUTn temperature monitor & gate control current limitation T
Tn
input mapping
& OVLn CLn
OUTn
BOLn
MAPn
delay
GND
Protection.emf
Figure 7
Protective Functions
4.2.1
Over Load Protection
The SPIDER - TLE 7232G is protected in case of over load or short circuit of the load. The behavior in case of over load can be configured as follows: a) The current is limited to IDS(LIM). After time td(fault), the according over load flag Ln is set. The channel may shut down due to over temperature. b) The current is limited to IDS(LIM). After time td(off), the over loaded channel n switches off and the according over load flag Ln is set. The over load flag (CLn) of the affected channel is cleared by a low-high transition of the input signal. For timing information, please refer to Figure 8 for details.
Data Sheet
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SPI Driver for Enhanced Relay Control SPIDER - TLE 7232G
Protection Functions
OLCR.OVL = 0 IN t ID ID(lim) td(fault) t L = 1b L = 0b ID ID(lim) IN
OLCR.OVL = 1
t
td(off) t L = 1b L = 0b
OverLoadTiming .emf
Figure 8
Over Load Behavior
4.2.2
Over Temperature Protection
A temperature sensor for each channel causes an overheated channel n to switch off immediately to prevent destruction. The behavior in case of over temperature can be configured as follows: a) After cooling down, the channel is switched on again with thermal hysteresis Tj. b) The affected channel stays switched off until the over temperature flag is cleared. The over temperature flag of the affected channel is cleared by a low-high transition of the input signal.
4.2.3
Reverse Polarity Protection
In case of reverse polarity, the intrinsic body diode of the power transistor causes power dissipation. The reverse current through the intrinsic body diode has to be limited by the connected load. The Vdd supply pin must be protected against reverse polarity externally. The over-temperature protection as well as other protective functions are not active during reverse polarity.
Data Sheet
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SPI Driver for Enhanced Relay Control SPIDER - TLE 7232G
Protection Functions
4.2.4
Electrical Characteristics
Unless otherwise specified: Vdd = 4.5 V to 5.5 V, Tj = -40 C to 150 C typical values: Vdd = 5.0 V, Tj = 25 C Pos. Parameter Symbol Limit Values min. Over Load Protection 4.2.1 4.2.2 Over load current limitation Over load shut-down delay time Over temperature shut-down threshold Thermal hysteresis typ. max. 2 50 A s Unit Test Conditions OVL = 0 OVL = 1
ID(lim) td(off)
1 10
Over Temperature Protection 4.2.3 4.2.4
Tj(OT)
Tj(OT)
170 10
200
C K
1)
1)
1) Not subject to production test, specified by design
Data Sheet
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SPI Driver for Enhanced Relay Control SPIDER - TLE 7232G
Protection Functions
4.2.5
Command Description
Reset Value: 00H
4 OVL4 rw 3 OVL3 rw 2 OVL2 rw 1 OVL1 rw 0 OVL0 rw
OLCR Over Load Configuration Register
7 OVL7 rw 6 OVL6 rw 5 OVL5 rw
Field OVLn (n = 7-0)
Bits n
Type Description rw Over Load Configuration Channel n 0 Channel n limits the current in case of over load (default value). 1 Channel n shuts down in case of over load.
OTCR Over Temperature Configuration Register
7 OVT7 rw 6 OVT6 rw 5 OVT5 rw 4 OVT4 rw 3 OVT3 rw 2 OVT2 rw
Reset Value: 00H
1 OVT1 rw 0 OVT0 rw
Field OVTn (n = 7-0)
Bits n
Type Description rw Over Temperature Configuration Channel n 0 Autorestart (default value) 1 Latched shut down
Data Sheet
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SPI Driver for Enhanced Relay Control SPIDER - TLE 7232G
Diagnostic Features
4.3
Diagnostic Features
The SPI of SPIDER - TLE 7232G provides diagnosis information about the device and about the load. There are following diagnosis flags implemented: * The diagnosis information of the protective functions (flags CLn and Tn) of channel n is latched in the diagnosis flag Pn. * The open load diagnosis of channel n is latched in the diagnosis flag OLn. * The short to gnd monitor information of channel n is latched in the diagnosis flag SGn. All flags are cleared after a successful SPI transmission. There is an output state monitor implemented in the device that indicates the switch state of the device in register STA. Depending on the voltage level at input pin and protective functions the bits are high or low. Please see Figure 9 for details:
VDD SPI
CHn MUX 00 01 10
V DS(SG) SGn VDS(OL) OLn
STA. OUTn
IDS(SG)
OUTn
IDS(PD)
gate control CLn Pn
OR
protective functions
Tn GND
diagnosis .emf
Figure 9
Block Diagram Diagnosis
Data Sheet
22
V1.0, 2005-09-30
SPI Driver for Enhanced Relay Control SPIDER - TLE 7232G
Diagnostic Features
4.3.1
Electrical Characteristics
Unless otherwise specified: Vdd = 4.5 V to 5.5 V, Tj = -40 C to 150 C typical values: Vdd = 5.0 V, Tj = 25 C Pos. Parameter Symbol Limit Values min. OFF State Diagnosis 4.3.1 4.3.2 Open load detection threshold voltage typ. max. Unit Test Conditions
VDS(OL)
Vdd - Vdd - Vdd - V
2.5 50 2 1.3 90 150 A
ID(PD) Output pull-down diagnosis current per channel
Short to gnd detection threshold voltage Output diagnosis current for short to gnd per channel Fault delay time
4.3.3
VDS(SG) ID(SG) td(fault)
Vdd - Vdd - Vdd - V
3.4 3.0 2.6 A
4.3.4
-150
-100
-50
VDS = 0 V
4.3.5
50
100
200
s
Data Sheet
23
V1.0, 2005-09-30
SPI Driver for Enhanced Relay Control SPIDER - TLE 7232G
Diagnostic Features
4.3.2
Command Description
Reset Value: 00H
5 OUT5 r 4 OUT4 r 3 OUT3 r 2 OUT2 r 1 OUT1 r 0 OUT0 r
STA Output Status Monitor
7 OUT7 r 6 OUT6 r
Field OUTn (n = 7-0)
Bits n
Type Description r Output Status 0 Voltage level at channel n: VDS > VDS(OL). 1 Voltage level at channel n: VDS < VDS(OL).
Data Sheet
24
V1.0, 2005-09-30
SPI Driver for Enhanced Relay Control SPIDER - TLE 7232G
Serial Peripheral Interface (SPI)
4.4
Serial Peripheral Interface (SPI)
The diagnosis and control interface is based on a serial peripheral interface (SPI). The SPI is a full duplex synchronous serial slave interface, which uses four lines: SO, SI, SCLK and CS. Data is transferred by the lines SI and SO at the data rate given by SCLK. The falling edge of CS indicates the beginning of a data access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of CS. A modulo 8 counter ensures that data is taken only, when a multiple of 8 bit has been transferred. The interface provides daisy chain capability.
SO SI CS SCLK
time
SPI.emf MSB MSB 14 14 13 13 12 12 11 11 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB
Figure 10
Serial Peripheral Interface
The SPI protocol is described in Section 4.4.5. It is reset to the default values after power-on reset or a low signal at pin RST.
4.4.1
SPI Signal Description
CS - Chip Select: The system micro controller selects the SPIDER - TLE 7232G by means of the CS pin. Whenever the pin is in low state, data transfer can take place. When CS is in high state, any signals at the SCLK and SI pins are ignored and SO is forced into a high impedance state.
CS High to Low transition:
* The diagnosis information is transferred into the shift register.
CS Low to High transition:
* Command decoding is only done, when after the falling edge of CS exactly a multiple (1, 2, 3, ...) of eight SCLK signals have been detected. * Data from shift register is transferred into the input matrix register. * The diagnosis flags are cleared. SCLK - Serial Clock: This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling edge of SCLK while the serial output
Data Sheet 25 V1.0, 2005-09-30
SPI Driver for Enhanced Relay Control SPIDER - TLE 7232G
Serial Peripheral Interface (SPI) (SO) shifts diagnostic information out on the rising edge of the serial clock. It is essential that the SCLK pin is in low state whenever chip select CS makes any transition. SI - Serial Input: Serial input data bits are shifted in at this pin, the most significant bit first. SI information is read on the falling edge of SCLK. The 16 bit input data consist of two parts (control and data). Please refer to Section 4.4.5 for further information. SO Serial Output: Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CS pin goes to low state. New data will appear at the SO pin following the rising edge of SCLK. Please refer to Section 4.4.5 for further information.
4.4.2
Daisy Chain Capability
The SPI of SPIDER - TLE 7232G provides daisy chain capability. In this configuration several devices are activated by the same CS signal MCS. The SI line of one device is connected with the SO line of another device (see Figure 11), which builds a chain. The ends of the chain are connected with the output and input of the master device, MO and MI respectively. The master device provides the master clock MCLK, which is connected to the SCLK line of each device in the chain.
device 1
MO SI SPI SO SI
device 2
SPI SO SI
device 3
SPI SO
CS
CS
SCLK
SCLK
CS
MI MCS MCLK
Figure 11
Daisy Chain Configuration
In the SPI block of each device, there is one shift register where one bit from SI line is shifted in each SCLK. The bit shifted out can be seen at SO. After 16 SCLK cycles, the data transfer for one device has been finished. In single chip configuration, the CS line must go high to make the device accept the transferred data. In daisy chain configuration the data shifted out at device #1 has been shifted in to device #2. When using three devices in daisy chain, three times 16 bits have to be shifted through the devices. After that, the MCS line must go high (see Figure 12).
Data Sheet
26
SCLK
SPI_DasyChain.emf
V1.0, 2005-09-30
SPI Driver for Enhanced Relay Control SPIDER - TLE 7232G
Serial Peripheral Interface (SPI)
MI MO MCS MCLK
time
SPI_DasyChain2.emf
SO device 3 SI device 3
SO device 2 SI device 2
SO device 1 SI device 1
Figure 12
Data Transfer in Daisy Chain Configuration
4.4.3
Timing Diagrams
tCS(lead) tCS(lag) tSCLK(P) tSCLK(H) tSCLK(L)
0.7Vdd 0.2Vdd
tCS(td)
0.7Vdd 0.2Vdd
CS
SCLK
tSI(su) tSI(h)
SI
tSO(v) tSO(dis)
0.7Vdd 0.2Vdd
SO
0.7Vdd 0.2Vdd SPI Timing.emf
Figure 13
Timing Diagram
Data Sheet
27
V1.0, 2005-09-30
SPI Driver for Enhanced Relay Control SPIDER - TLE 7232G
Serial Peripheral Interface (SPI)
4.4.4
Electrical Characteristics
Unless otherwise specified: VVSO = 3.0 V to 5.5 V, Vdd = 4.5 V to 5.5 V, Tj = -40 C to 150 C typical values: VVSO = 5.0 V, Vdd = 5.0 V, Tj = 25 C Pos. Parameter Symbol Limit Values min. typ. Power Supply 4.4.1 Power supply voltage VVSO for SO buffer L level of pin CS VCS(L) SCLK VSCLK(L) SI VSI(L) 4.4.3 H level of pin CS VCS(H) SCLK VSCLK(H) SI VSI(H) 4.4.4 4.4.5 4.4.6 L-input pull-up current ICS(L) through CS H-input pull-up current through CS 10 5 5 20 2 3.0 5.5 V max. Unit Test Conditions
Input Characteristics (CS, SCLK, SI) 4.4.2 0 1 V
Vdd
V
50 50 50
A A A
VCS = 0 V
1)
ICS(H)
VCS = 2 V
1)
L-input pull-down current through pin SCLK ISCLK(L) SI ISI(L) H-input pull-down current through pin SCLK ISCLK(H) SI ISI(H) L level output voltage VSO(L) H level output voltage VSO(H)
VSCLK = 1 V VSI = 1 V
10 20 50 A
4.4.7
VSCLK = 5 V VSI = 5 V
0 4.6 2.4 -10 0.4 5 3 10 A V
Output Characteristics (SO) 4.4.8 4.4.9
4.4.10 Output tristate leakage current
Data Sheet
ISO(OFF)
ISO = -2.5 mA ISO = 2 mA VVSO = 5 V VVSO = 3 V VCS = Vdd
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28
SPI Driver for Enhanced Relay Control SPIDER - TLE 7232G
Serial Peripheral Interface (SPI) Unless otherwise specified: VVSO = 3.0 V to 5.5 V, Vdd = 4.5 V to 5.5 V, Tj = -40 C to 150 C typical values: VVSO = 5.0 V, Vdd = 5.0 V, Tj = 25 C Pos. Parameter Symbol Limit Values min. typ. Timings 4.4.11 Serial clock frequency fSCLK 0 200 50 50 250 5 MHz ns ns ns ns max. Unit Test Conditions
tSCLK(P) 4.4.13 Serial clock high time tSCLK(H) 4.4.14 Serial clock low time tSCLK(L) 4.4.15 Enable lead time tSCLK(lead)
4.4.12 Serial clock period (falling CS to rising SCLK) 4.4.16 Enable lag time tSCLK(lag) (falling SCLK to rising CS) 4.4.17 Transfer delay time (rising CS to falling CS) 4.4.18 Data setup time (required time SI to falling SCLK)
250
ns
tCS(del) tSI(su)
250
ns
20
ns
4.4.19 Data hold time (falling tSI(h) SCLK to SI) 4.4.20 Output disable time (rising CS to SO tristate)
20 150
ns ns
1)
tSO(dis)
4.4.21 Output data valid time tSO(v) with capacitive load
1) Not subject to production test, specified by design.
100
ns
CL = 50 pF 1)
Data Sheet
29
V1.0, 2005-09-30
SPI Driver for Enhanced Relay Control SPIDER - TLE 7232G
Serial Peripheral Interface (SPI)
4.4.5
SPI Protocol
The SPI protocol of the SPIDER - TLE 7232G provides two types of registers. The control registers and the diagnosis registers. After power-on reset, all register bits set to default values. SI Reset Value: xxxxH
15 14 13 0 12 0 11 0 10 9 ADDR 8 7 6 5 4 3 2 1 0
CMD
DATA
Field CMD
Bits 15:14
Type Description Command 00 Diagnosis only: The requested data is shifted out at SO. This command does not change any register setting. 01 Read register: The register content of the addressed register will be sent in the next frame. 10 Reset registers: All registers are reset to their default values. 11 Write register: The data of the SI word will be written to the addressed register. Address Pointer to register for read and write command Data Data written to or read from register selected by address ADDR
ADDR DATA
10:8 7:0
Data Sheet
30
V1.0, 2005-09-30
SPI Driver for Enhanced Relay Control SPIDER - TLE 7232G
Serial Peripheral Interface (SPI) SO Standard Diagnosis
15 14 13 12 11 10 9 CH4 8 7 CH3 6 5 CH2 4
Reset Value: xxxxH
3 CH1 2 1 CH0 0
CH7
CH6
CH5
Field CHn (n = 7-0)
Bits (2n+1): 2n
Type Description Standard Diagnosis for Channel n 00 Short circuit to GND 01 Open load 10 Over load, over temperature 11 Normal operation
SO Second Frame of Read Command
15 0 14 1 13 0 12 0 11 0 10 9 ADDR 8 7 6 5 4
Reset Value: xxxxH
3 2 1 0
DATA
Field ADDR DATA
Bits 10:8 7:0
Type Description Address Pointer to register for read and write command Data Data written to or read from register selected by address ADDR
Note: Reading a register needs two SPI frames. In the first frame the RD command is sent. In the second frame the output at SPI signal SO will contain the requested information. A new command can be executed in the second frame.
Data Sheet
31
V1.0, 2005-09-30
SPI Driver for Enhanced Relay Control SPIDER - TLE 7232G
Serial Peripheral Interface (SPI)
4.4.6
Name IMCR OLCR
Register Overview
W/R W/R W/R Addr 001B 010B 011B 100B 101B 110B 111B 7 6 5 4 3 2 1 0 default
1)
MAP7 MAP6 MAP5 MAP4 MAP3 MAP2 MAP1 MAP0 08H BOL7 OVL7 SLE7 BOL6 OVL6 SLE6 BOL5 OVL5 SLE5 BOL4 OVL4 SLE4 BOL3 OVL3 SLE3 BOL2 OVL2 SLE2 BOL1 OVL1 SLE1 BOL0 OVL0 SLE0 00H 00H 00H
BOCR W/R OTCR W/R SRCR W/R STA CTL R W/R
OVT7 OVT6 OVT5 OVT4
OVT3 OVT2 OVT1 OVT0 00H
OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 00H OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 00H
1) The default values are set after reset.
Data Sheet
32
V1.0, 2005-09-30
SPI Driver for Enhanced Relay Control SPIDER - TLE 7232G
Package Outlines SPIDER - TLE 7232G
5
Package Outlines SPIDER - TLE 7232G
0.2 -0.1
2.65 MAX.
0.35 x 45
+0.0 9
2.45 -0.2
1.27 0.35 +0.15 2) 24
0.4 +0.8
0.1 0.2 24x
13 10.3 0.3
1
15.6 -0.4 1)
12
Index Marking
1) 2)
Does not include plastic or metal protrusion of 0.15 max. per side Lead width can be 0.61 max. in dambar area
0.23
8 MAX.
Dimensions in mm
7.6 -0.2 1)
Figure 14
P-DSO-24-3 (Plastic Dual Small Outline Package)
You can find all of our packages, sorts of packing and others in our Infineon Internet Page "Products": http://www.infineon.com/products. Data Sheet 33 V1.0, 2005-09-30
SPI Driver for Enhanced Relay Control SPIDER - TLE 7232G
Revision History
6
Version V1.0
Revision History
Date 05-09-30 Changes release of data sheet
Data Sheet
34
2005-09-30
SPI Driver for Enhanced Relay Control SPIDER - TLE 7232G
Edition 2005-09-30 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany
(c) Infineon Technologies AG 2005.
All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Data Sheet
35
2005-09-30
http://www.infineon.com
Published by Infineon Technologies AG

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