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KM48V8004B, KM48V8104B
CMOS DRAM
8M x 8bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
This is a family of 8,388,608 x 8 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -5 or -6), power consumption(Normal or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 8Mx8 EDO Mode DRAM family is fabricated using Samsungs advanced CMOS process to realize high band-width, low power consumption and high reliability.
FEATURES
* Part Identification - KM48V8004B/B-L(3.3V, 8K Ref.) - KM48V8104B/B-L(3.3V, 4K Ref.) * Active Power Dissipation Unit : mW Speed -45 -5 -6 * Refresh Cycles Part NO. KM48V8004B* KM48V8104B Refresh cycle 8K 4K Refresh time Normal 64ms L-ver 128ms
RAS CAS W
* Extended Data Out Mode operation * CAS-before-RAS refresh capability * RAS-only and Hidden refresh capability * Self-refresh capability (L-ver only) * Fast parallel test mode capability * LVTTL(3.3V) compatible inputs and outputs * Early Write or output enable controlled write * JEDEC Standard pinout * Available in Plastic SOJ and TSOP(II) packages * +3.3V0.3V power supply 4K 468 432 396
8K 360 324 288
FUNCTIONAL BLOCK DIAGRAM
Control Clocks Vcc Vss
VBB Generator
Refresh Control Refresh Counter Memory Array 8,388,608 x 8 Cells
Sense Amps & I/O
* Access mode & RAS only refresh mode : 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.) CAS-before-RAS & Hidden refresh mode : 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)
U
Refresh Timer
Row Decoder Data in Buffer DQ0 to DQ7 Data out Buffer OE
Performance Range: Speed -45 -5 -6
tRAC
45ns 50ns 60ns
tCAC
12ns 13ns 15ns
tRC
74ns 84ns 104ns
tHPC
17ns 20ns 25ns
A0~A12 (A0~A11)*1 A0~A9 (A0~A10)*1
Row Address Buffer Col. Address Buffer Column Decoder
Note) *1 : 4K Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
KM48V8004B, KM48V8104B
CMOS DRAM
PIN CONFIGURATION (Top Views)
*KM48V80(1)04BK VCC DQ0 DQ1 DQ2 DQ3 N.C VCC W RAS A0 A1 A2 A3 A4 A5 VCC 1 U 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VSS DQ7 DQ6 DQ5 DQ4 VSS CAS OE A12(N.C)* A11 A10 A9 A8 A7 A6 VSS
*KM48V80(1)04BS
VCC DQ0 DQ1 DQ2 DQ3 N.C VCC W RAS A0 A1 A2 A3 A4 A5 VCC
1 U 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VSS DQ7 DQ6 DQ5 DQ4 VSS CAS OE A12(N.C)* A11 A10 A9 A8 A7 A6 VSS
(K : 400mil SOJ)
(S : 400mil TSOP(II))
* (N.C) : N.C for 4K Refresh product
Pin Name A0 - A12 A0 - A11 DQ0 - 7 VSS RAS CAS W OE VCC N.C
Pin Function Address Inputs(8K Product) Address Inputs(4K Product) Data In/Out Ground Row Address Strobe Column Address Strobe Read/Write Input Data Output Enable Power(+3.3V) No Connection
KM48V8004B, KM48V8104B
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol VIN,VOUT VCC Tstg PD IOS Rating -0.5 to +6.5 -0.5 to +4.6 -55 to +150 1 50
CMOS DRAM
Units V V C W mA
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70C)
Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 3.0 0 2.0 -0.3*2 Typ 3.3 0 Max 3.6 0 +5.5*1 0.8 Units V V V V
*1 : 6.5V at pulse width15ns which is measured at VCC *2 : -1.3 at pulse width15ns which is measured at VSS
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Parameter Input Leakage Current (Any input 0VINVCC+0.3V, all other pins not under test=0 Volt) Output Leakage Current (Data out is disabled, 0VVOUTVCC) Output High Voltage Level(IOH=-2mA) Output Low Voltage Level(IOL=2mA) Symbol II(L) IO(L) VOH VOL Min -5 -5 2.4 Max 5 5 0.4 Units uA uA V V
KM48V8004B, KM48V8104B
DC AND OPERATING CHARACTERISTICS (Continued)
Symbol Power Speed KM48V8004B ICC1 Dont care Normal L Dont care -45 -5 -6 Dont care -45 -5 -6 -45 -5 -6 Dont care -45 -5 -6 Dont care Dont care 100 90 80 2 2 100 90 80 110 100 90 500 300 100 90 80 400 400 Max KM48V8104B 130 120 110 2 2 130 120 110 120 110 100 500 300 130 120 110 400 400
CMOS DRAM
Units mA mA mA mA mA mA mA mA mA mA mA uA uA mA mA mA uA uA
ICC2
ICC3
ICC4
Dont care Normal L Dont care L L
ICC5
ICC6 ICC7 ICCS
ICC1* : Operating Current (RAS and CAS, Address cycling @tRC=min.) ICC2 : Standby Current (RAS=CAS=W=VIH) ICC3* : RAS-only Refresh Current (CAS=VIH, RAS cycling @tRC=min.) ICC4* : Extended Data Out Mode Current (RAS=VIL, CAS, Address cycling @tHPC=min.) ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V) ICC6* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @tRC=min) ICC7 : Battery back-up current, Average power supply current, Battery back-up mode Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, CAS=CAS-before-RAS cycling or 0.2V W, OE=VIH, Address=Dont care, DQ=Open, TRC=31.25us ICCS : Self Refresh Current RAS=CAS=0.2V, W=OE=A0 ~ A12(A11)=VCC-0.2V or 0.2V, DQ0 ~ DQ7=VCC-0.2V, 0.2V or Open
*Note : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one EDO mode cycle time, tHPC.
KM48V8004B, KM48V8104B
CAPACITANCE (TA=25C, VCC=3.3V, f=1MHz)
Parameter Input capacitance [A0 ~ A12] Input capacitance [RAS, CAS, W, OE] Output capacitance [DQ0 - DQ7] Symbol CIN1 CIN2 CDQ Min -
CMOS DRAM
Max 5 7 7 Units pF pF pF
AC CHARACTERISTICS (0CTA70C, See note 1,2)
Test condition : VCC=3.3V0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z Output buffer turn-off delay from CAS OE to output in Low-Z Transition time (rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold time referenced to CAS Read command hold time referenced to RAS Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data set-up time Symbol Min -45 Max Min 84 113 45 12 23 3 3 3 1 25 45 8 35 7 11 9 5 0 7 0 7 23 0 0 0 7 6 8 7 0 5K 33 22 10K 50 13 3 3 3 1 30 50 8 38 8 11 9 5 0 7 0 7 25 0 0 0 7 7 8 7 0 10K 37 25 10K 50 13 50 13 25 3 3 3 1 40 60 10 40 10 14 12 5 0 10 0 10 30 0 0 0 10 10 10 10 0 10K 45 30 10K 50 13 -5 Max Min 104 138 60 15 30 -6 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 9 8 8 4 10 3,4,10 3,4,5 3,10 3 6,14 3 2 Units Note
tRC tRWC tRAC tCAC tAA tCLZ tCEZ tOLZ tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWP tRWL tCWL tDS
74 101
KM48V8004B, KM48V8104B
AC CHARACTERISTICS (Continued)
Parameter Data hold time Refresh period (Normal) Refresh period (L-ver) Write command set-up time CAS to W delay time RAS to W delay time Column address to W delay time CAS set-up time (CAS -before-RAS refresh) CAS hold time (CAS -before-RAS refresh) RAS to CAS precharge time Access time from CAS precharge Hyper Page cycle time Hyper Page read-modify-write cycle time CAS precharge time (Hyper page cycle) RAS pulse width (Hyper page cycle) RAS hold time from CAS precharge OE access time OE to data delay CAS precharge to W delay time Output buffer turn off delay time from OE OE command hold time Write command set-up time (Test mode in) Write command hold time (Test mode in) W to RAS precharge time (C-B-R refresh) W to RAS hold time (C-B-R refresh) Output data hold time Output buffer turn off delay from RAS Output buffer turn off delay from W W to data delay OE to CAS hold time CAS hold time to OE OE precharge time W pulse width (Hyper Page Cycle) RAS pulse width (C-B-R self refresh) RAS precharge time (C-B-R self refresh) CAS hold time (C-B-R self refresh) Symbol Min -45 Max Min 7 64 128 0 24 57 35 5 10 5 24 17 47 6.5 45 24 12 8 36 3 5 10 10 10 10 4 3 3 8 5 5 5 5 100 74 -50 13 13 11 10 41 3 5 10 10 10 10 5 3 3 15 5 5 5 5 100 90 -50 13 13 13 200K 20 47 7 50 30 13 13 52 3 5 10 10 10 10 5 3 3 15 5 5 5 5 100 110 -50 200K 0 27 64 39 5 10 5 28 25 56 10 60 35 64 128 0 32 77 47 5 10 5 -5 Max Min 10 -6
CMOS DRAM
Units Max ns 64 128 ms ms ns ns ns ns ns ns ns 35 ns ns ns ns 200K ns ns 15 ns ns ns 13 ns ns ns ns ns ns ns 13 13 ns ns ns ns ns ns ns us ns ns
Note 9
tDH tREF tREF tWCS tCWD tRWD tAWD tCSR tCHR tRPC tCPA tHPC tHPRWC tCP tRASP tRHCP tOEA tOED tCPWD tOEZ tOEH tWTS tWTH tWRP tWRH tDOH tREZ tWEZ tWED tOCH tCHO tOEP tWPE tRASS tRPS tCHS
7
7 7 7 7
3 13 13
6
11 11
6,14 6
15,16,17 15,16,17 15,16,17
KM48V8004B, KM48V8104B
TEST MODE CYCLE
Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address RAS pulse width CAS pulse width RAS hold time CAS hold time Column Address to RAS lead time CAS to W delay time RAS to W delay time Column Address to W delay time Hyper Page cycle time Hyper Page read-modify-write cycle time RAS pulse width (Hyper page cycle) Access time from CAS precharge OE access time OE to data delay OE command hold time Symbol Min -45 Max Min 89 121 50 17 28 50 12 18 39 28 29 62 40 22 52 50 200K 29 17 13 13 18 18 10K 10K 55 13 18 43 30 35 72 47 25 53 55 200K 33 18 20 20 55 18 30 10K 10K 65 15 20 50 35 39 84 54 30 61 65 -5 Max Min 109 145 -6
CMOS DRAM
( Note 11 )
Units Max ns ns 65 20 35 10K 10K ns ns ns ns ns ns ns ns ns ns ns ns ns 200K 40 20 ns ns ns ns ns 3 7 7 7 13 13 3,4,10,12 3,4,5,12 3,10,12 Note
tRC tRWC tRAC tCAC tAA tRAS tCAS tRSH tCSH tRAL tCWD tRWD tAWD tHPC tHPRWC tRASP tCPA tOEA tOED tOEH
79 110
KM48V8004B, KM48V8104B
NOTES
CMOS DRAM
1. An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 2ns for all inputs. 3. Measured with a load equivalent to 1 TTL load and 100pF. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCDtRCD(max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol. 7. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCStWCS(min), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWDtCWD(min), tRWDtRWD(min) and tAWDtAWD(min), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in OE controlled write cycle and read-modify-write cycles. 10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If
tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.
11. These specifications are applied in the test mode. 12. In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 13. tASC6ns, Assume tT = 2.0ns 14. If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes high before RAS high going, the open circuit condition of the output is achieved by RAS high going. 15. If tRASS100us, then RAS precharge time must use tRPS instead of tRP. 16. For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K/8K) cycles of burst refresh must be executed within 64ms before and after self refresh, in order to meet refresh specification. 17. For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification.
KM48V8004B, KM48V8104B
READ CYCLE
CMOS DRAM
tRC tRAS
RAS VIH VIL -
tRP
tCRP
CAS VIH VIL -
tCSH tRCD tRSH tCAS
tCRP
tRAD tASR
A VIH VIL -
tRAH
tASC
tRAL tCAH
COLUMN ADDRESS
ROW ADDRESS
tRCS
W VIH VIL -
tRCH tRRH
tWEZ tAA
OE VIH VIL -
tCEZ tOEZ tOEA
DQ0 ~ DQ3(7) VOH VOL -
tRAC OPEN
tOLZ tCAC tCLZ
tREZ
DATA-OUT
Dont care Undefined
KM48V8004B, KM48V8104B
WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRC tRAS
RAS VIH VIL -
tRP
tCSH tCRP
CAS VIH VIL -
tRCD tRAD
tRSH tCAS
tCRP
tASR
A VIH VIL -
tRAH
tASC
tRAL tCAH
COLUMN ADDRESS
ROW ADDRESS
tCWL tRWL tWCS
W VIH VIL -
tWCH tWP
OE
VIH VIL -
DQ0 ~ DQ3(7) VIH VIL -
tDS
tDH
DATA-IN
Dont care Undefined
KM48V8004B, KM48V8104B
WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRC tRAS
RAS VIH VIL -
tRP
tCRP
CAS VIH VIL -
tCSH tRCD tRSH tCAS tCRP
tRAD tRAL tASR
A VIH VIL -
tRAH
tASC
tCAH
COLUMN ADDRESS
ROW ADDRESS
tCWL tRWL
W VIH VIL -
tWP
OE
VIH VIL -
tOED tDS
tOEH tDH
DATA-IN
DQ0 ~ DQ3(7) VIH VIL -
Dont care Undefined
KM48V8004B, KM48V8104B
READ - MODIFY - WRITE CYCLE
CMOS DRAM
tRAS
RAS VIH VIL -
tRWC
tRP
tCRP
CAS VIH VIL -
tRCD tRAD tRAH
tRSH tCAS
tASR
VIH VIL -
tASC
tCAH tCSH
A
ROW ADDR
COLUMN ADDRESS
tAWD tCWD
W VIH VIL -
tRWL tCWL tWP
tRWD
OE VIH VIL -
tOEA tOLZ tCLZ tCAC tAA tRAC
VALID DATA-OUT
tOED tOEZ tDS tDH
VALID DATA-IN
DQ0 ~ DQ3(7) VI/OH VI/OL -
Dont care Undefined
KM48V8004B, KM48V8104B
HYPER PAGE READ CYCLE
CMOS DRAM
tRASP
RAS VIH VIL o
tRP
tCSH tCRP
CAS VIH VIL -
tRHCP tHPC tCP tHPC tCAS tCP tHPC tCAS tCP tCAS
tRCD tCAS tRAD
tASR
A VIH VIL -
tRAH tASC
ROW ADDR
tCAH
tASC
tCAH
tASC
tCAH
COLUMN ADDR
tASC
tCAH
tREZ
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
tRAL tRCS
W VIH VIL -
tRRH tRCH
tCAC tAA tCPA tAA tOCH tOEA tCAC tOEA tOEP
tCAC tAA tCPA
tCPA tCAC tAA tCHO tOEP
OE
VIH VIL -
tOEA tOEZ
VALID DATA-OUT VALID DATA-OUT
DQ0 ~ DQ3(7) VOH VOL -
tRAC
tDOH
VALID DATA-OUT
tOEZ
tOEZ
tOLZ tCLZ
VALID DATA-OUT
Dont care Undefined
KM48V8004B, KM48V8104B
HYPER PAGE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRASP
RAS VIH VIL o
tRP tRHCP
tCRP
CAS VIH VIL -
tHPC tRCD tCAS tRAD tCSH tASC tCP tCAS
o
tHPC tCP
tRSH tCAS
tASR
A VIH VIL -
tRAH
tCAH
tASC
tCAH
o
tASC
tCAH
ROW ADDR.
COLUMN ADDRESS
COLUMN ADDRESS
o
COLUMN ADDRESS
tRAL tWCS
W VIH VIL -
tWCH
tWCS
tWCH tWP tCWL
o o o
tWCS
tWCH tWP tCWL tRWL
tWP tCWL
OE
VIH VIL -
DQ0 ~ DQ3(7) VIH VIL -
tDS
tDH
VALID DATA-IN
tDS
tDH
o
VALID DATA-IN
tDS
tDH
o
VALID DATA-IN
Dont care Undefined
KM48V8004B, KM48V8104B
HYPER PAGE READ-MODIFY-WRITE CYCLE
CMOS DRAM
tRASP
RAS VIH VIL -
tRP tRSH tHPRWC
tCSH tCRP
tRCD tCAS tRAD tRAH
tCP tCAS tRAL tASC
COL. ADDR COL. ADDR
tCRP
CAS
VIH VIL -
tASR
A VIH VIL ROW ADDR
tASC
tCAH
tCAH
tRCS
W VIH VIL -
tCWL tWP tCWD tAWD tCPWD tOEA tOED
tRWL tCWL tWP
tCWD tAWD tRWD tOEA tCAC tAA tCAC
OE
VIH VIL -
tOED tDH tDS tAA tDH tOEZ tDS
tOEZ
DQ0 ~ DQ3(7) VI/OH VI/OL -
tRAC tCLZ tOLZ
VALID DATA-OUT
tCLZ
VALID DATA-IN
tOLZ
VALID DATA-OUT
VALID DATA-IN
Dont care Undefined
KM48V8004B, KM48V8104B
HYPER PAGE READ AND WRITE MIXED CYCLE
CMOS DRAM
tRASP
RAS VIH VIL READ(tCAC) READ(tCPA) WRITE READ(tAA)
tRP
tHPC tCP
CAS VIH VIL -
tHPC tCP tCP tCAS tASC
COL. ADDR
tRHCP tHPC tCAS tASC tCAH
COL. ADDR
tRAD tASR tRAH tASC
tCAS tCAH
tCAS tCAH
tCAH
tASC
COLUMN ADDRESS
A
VIH VIL -
ROW ADDR
COLUMN ADDRESS
tRAL tRCS
W VIH VIL -
tRCH
tRCS
tRCH tWCS
tWCH
tRCH
tWPE tCLZ tCPA
OE VIH VIL -
tWED
DQ0 ~ DQ3(7) VI/OH VI/OL -
tOEA tCAC tAA tRAC
tWEZ
tDH tWEZ
VALID
DATA-OUT
tDS tCLZ
VALID DATA-IN
tAA
VALID DATA-OUT
tREZ
VALID DATA-OUT
Dont care Undefined
KM48V8004B, KM48V8104B
RAS - ONLY REFRESH CYCLE*
NOTE : W, OE, DIN = Dont care DOUT = OPEN tRC
RAS VIH VIL -
CMOS DRAM
tRP
tRAS tCRP tRPC tCRP
CAS
VIH VIL -
tASR
A VIH VIL -
tRAH
ROW ADDR
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE , A = Dont care
tRP
RAS VIH VIL -
tRC tRAS
tRP
tRPC tCP tCSR tCHR
tRPC
CAS
VIH VIL -
tWRP
W VIH VIL -
tWRH
DQ0 ~ DQ3(7) VOH VOL -
tCEZ OPEN
Dont care Undefined
KM48V8004B, KM48V8104B
HIDDEN REFRESH CYCLE ( READ )
CMOS DRAM
tRC
RAS VIH VIL -
tRP
tRC tRAS
tRP
tRAS
tCRP
CAS VIH VIL -
tRCD
tRSH
tCHR
tRAD tASR
A VIH VIL -
tRAL tASC tCAH
COLUMN ADDRESS
tRAH
ROW ADDRESS
tRCS
W VIH VIL -
tWRH
tAA
OE VIH VIL -
tOEA tOLZ tCAC tCEZ tREZ tWEZ tOEZ
DATA-OUT
DQ0 ~ DQ3(7) VOH VOL -
tCLZ tRAC OPEN
Dont care Undefined
* In Hidden refresh cycle of 64Mb A-dile & B-die, when CAS signal transits from Low to High, the valid data may be cut off.
KM48V8004B, KM48V8104B
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRC
RAS VIH VIL -
tRP
tRC tRAS
tRP
tRAS tCRP
tRCD
tRSH
tCHR
CAS
VIH VIL -
tRAD tASR
A VIH VIL -
tRAH
tASC
tRAL tCAH
COLUMN ADDRESS
ROW ADDRESS
tWCS
W VIH VIL -
tWRP tWCH tWP
tWRH
OE
VIH VIL -
tDS
DQ0 ~ DQ3(7) VIH VIL -
tDH
DATA-IN
Dont care Undefined
KM48V8004B, KM48V8104B
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE, A = Dont care
CMOS DRAM
tRP
RAS VIH VIL -
tRASS
tRPS
tRPC tCP tCSR tCHS
tRPC
CAS
VIH VIL -
DQ0 ~ DQ3(7) VOH VOL -
tCEZ OPEN
W
VIH VIL -
tWRP
tWRH
TEST MODE IN CYCLE
NOTE : OE , A = Dont care tRC tRAS tRPC tCP
CAS VIH VIL -
tRP
RAS VIH VIL -
tRP
tRPC tCSR tCHR
tWTS
W VIH VIL -
tWTH
DQ0 ~ DQ3(7) VOH VOL -
tOFF OPEN
Dont care Undefined
KM48V8004B, KM48V8104B
PACKAGE DIMENSION
32 SOJ 400mil
CMOS DRAM
Units : Inches (millimeters)
#32 0.435 (11.06) 0.445 (11.30) 0.400 (10.16) 0.360 (9.15) 0.380 (9.65) 0.010 (0.25) TYP 0.018 (0.45) 0.030 (0.75) 0~8
O
0.006 (0.15) 0.012 (0.30)
#1 0.027 (0.69) MIN 0.841 (21.36) MAX 0.820 (20.84) 0.830 (21.08) 0.148 (3.76) MAX 0.026 (0.66) 0.032 (0.81) 0.015 (0.38) 0.021 (0.53)
0.0375 (0.95)
0.050 (1.27)
32 TSOP(II) 400mil
Units : Inches (millimeters)
0.455 (11.56) 0.471 (11.96)
0.400 (10.16)
0.004 (0.10) 0.010 (0.25) 0.841 (21.35) MAX 0.821 (20.85) 0.829 (21.05) 0.047 (1.20) MAX
0.037 (0.95)
0.050 (1.27)
0.002 (0.05) MIN 0.012 (0.30) 0.020 (0.50)

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