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AS4LC256K16EO
(R)
3.3V 256K X 16 CMOS DRAM (EDO) Features
* Organization: 262,144 words x 16 bits * High speed
- 45/60 ns RAS access time - 10/12/15/20 ns column address access time - 7/10/10 ns CAS access time
* Low power consumption
* EDO page mode * 5V I/O tolerant * 512 refresh cycles, 8 ms refresh interval
- RAS-only or CAS-before-RAS refresh or self refresh
* Read-modify-write * LVTTL-compatible, three-state I/O * JEDEC standard packages
- Active: 280 mW max (AS4LC256K16EO-35) - Standby: 2.8 mW max, CMOS I/O (AS4LC256K16EO35)
- 400 mil, 40-pin SOJ - 400 mil, 40/44-pin TSOP II
* 3.3V power supply * Latch-up current > 200 mA
Pin arrangement
SOJ
Vcc I/O0 I/O1 I/O2 I/O3 Vcc I/O4 I/O5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10
Pin designation
TSOP II VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7
NC NC WE RAS
Pin(s)
44 43 42 41 40 39 38 37 36 35 32 31 30 29 28 27 26 25 24 23 GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8 NC
LCAS UCAS OE
Description Address inputs Row address strobe Input/output Output enable Column address strobe, upper byte Column address strobe, lower byte Read/write control Power (3.3V 0.3V) Ground
AS4LC256K16EO
AS4LC256K16EO
I/O6
I/O7 NC NC WE RAS NC A0 A1 A2
I/O9
I/O8 NC LCAS UCAS OE A8 A7 A6 A5
1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 21 22
A0 to A8 RAS I/O0 to I/O15 OE UCAS LCAS WE VCC GND
A3
Vcc
A4
GND
NC A0 A1 A2 A3 VCC
A8 A7 A6 A5 A4 GND
Selection guide
Symbol Maximum RAS access time Maximum column address access time Maximum CAS access time Maximum output enable (OE) access time Minimum read or write cycle time Minimum EDO page mode cycle time Maximum operating current Maximum CMOS standby current tRAC tCAA tCAC tOEA tRC tPC ICC1 ICC2 AS4LC256K16EO-35 35 17 7 7 50 15 70 200 AS4LC256K16EO-45 45 20 10 10 80 17 60 200 AS4LC256K16EO-60 60 25 10 10 100 30 50 200 Unit ns ns ns ns ns ns mA A
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Copyright (c) Alliance Semiconductor. All rights reserved.
AS4LC256K16EO
(R)
Functional description
The AS4LC256K16EO is a high-performance 4 megabit CMOS Dynamic Random Access Memory (DRAM) organized as 262,144 words by 16 bits. The AS4LC256K16EO is fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. The AS4LC256K16EO features a high speed page mode operation in which high speed read, write and read-write are performed on any of the 512 x 16 bits defined by the column address. The asynchronous column address uses an extremely short row address capture time to ease the system level timing constraints associated with multiplexed addressing. Very fast CAS to output access time eases system design. Refresh on the 512 address combinations of A0 to A8 during an 8 ms period is accomplished by performing any of the following:
* RAS-only refresh cycles * Hidden refresh cycles * CAS-before-RAS refresh cycles * Normal read or write cycles * Self refresh cycles
The AS4LC256K16EO is available in standard 40-pin plastic SOJ and 40/44-pin TSOP II packages compatible with widely available automated testing and insertion equipment. System level features include single power supply of 3.3V 0.3V tolerance and direct interface with TTL logic families.
Logic block diagram
VCC GND
REFRESH CONTROLLER COLUMN DECODER DATA I/O BUFFER
I/O0 to I/O15
SENSE AMP
RAS
RAS CLOCK GENERATOR
UCAS LCAS
CAS CLOCK GENERATOR
A0 A1 A2 A3 A4 A5 A6 A7 A8
OE
ADDRESS BUFFERS ROW DECODER 512x512x16 ARRAY (4,194,304)
SUBSTRATE BIAS GENERATOR
WE
WE CLOCK GENERATOR
Recommended operating conditions
Parameter Supply voltage Input voltage Symbol VCC GND VIH VIL Min 3.0 0.0 2.0 -1.0 Typ 3.3 0.0 - -
(Ta = 0C to +70C) Max Unit 3.6 0.0 VCC + 1 0.8 V V V V
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AS4LC256K16EO
(R)
Absolute maximum ratings
Parameter Input voltage Output voltage Power supply voltage Operating temperature Storage temperature (plastic) Soldering temperature x time Power dissipation Short circuit output current Latch-up current Symbol Vin Vout VCC TOPR TSTG TSOLDER PD Iout Min -1.0 -1.0 -1.0 0 -55 - - - 200 Max +7.0 +7.0 +7.0 +70 +150 260 x 10 1 50 - Unit V V V C C
o
C x sec
W mA mA
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC electrical characteristics
-35 Parameter Input leakage current Output leakage current Operating power supply current Symbol IIL IOL ICC1 Test conditions 0V Vin +5.5V pins not under test = 0V DOUT disabled, 0V Vout +5.5V RAS, UCAS, LCAS, address cycling; tRC=min RAS = UCAS = LCAS = VIH RAS cycling, UCAS = LCAS = VIH, tRC = min RAS=UCAS=LCAS=VIL, address cycling: tSC = min RAS=UCAS=LCAS= VCC - 0.2V RAS, UCAS, LCAS, cycling; tRC = min IOUT = -2 mA IOUT = 2 mA RAS = UCAS = LCAS=VIL, WE = OE = A0-A8 = VCC-0.2V, DQ0-DQ15 = VCC-0.2V, 0.2V are open Min -10 -10 - - Max 10 10 70 200 -45 Min -10 -10 - - Max 10 10 60 200 -60 Min -10 -10 - - Max Unit 10 10 50 A A mA 1,2 Note
TTL standby power ICC2 supply current Average power supply current, RAS ICC3 refresh mode EDO page mode average power supply current CMOS standby power supply current CAS-before-RAS refresh power supply current Output Voltage ICC4
200 A 40 mA 1
-
50
-
45
-
-
40
-
35
-
35
mA
1,2
ICC5
-
400
-
400
-
400 A
ICC6 VOH VOL ICC7
- 2.4 -
50 - 0.4
- 2.4 -
50 - 0.4
- 2.4 -
50 - 0.4
mA V V
1
Self refresh current
-
400
-
400
-
400 A
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AS4LC256K16EO
(R)
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AS4LC256K16EO
(R)
AC parameters common to all waveforms
-35 Std Symbol Parameter tRC tRP tRAS tCAS tRCD tRAD tRSH(R) tCSH tCRP tASR tRAH tT tREF tCLZ Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS hold time (read cycle) RAS to CAS hold time CAS to RAS precharge time Row address setup time Row address hold time Transition time (rise and fall) Refresh period CAS to output in low Z Min 50 15 35 6 12 8 10 35 5 0 6 1.5 - 0 Max - - 75K - 18 14 - - - - - 50 8 - Min 80 20 45 10 18 13 10 45 5 0 8 1.5 - 3 -45 Max - - 75K - 32 23 - - - - - 50 8 - Min 100 20 60 10 15 15 12 60 5 0 9 1.5 - 3 -60 Max Unit - - 75K - 45 30 - - - - - 50 8 - ns ns ns ns ns ns ns ns ns ns ns ns ms ns 4,5 3 8 6 7 Notes
Read cycle
-35 Std Symbol tRAC tCAC tAA tAR(R) tRCS tRCH
tRRH
-45 Max 35 7 17 - - - - - - 8 Min - - - 35 0 0 0 25 5 0 Max 45 10 22 - - - - - - 10 Min - - - 40 0 0 0 30 5 0
-60 Max 60 10 30 - - - - - - 10 Unit ns ns ns ns ns ns ns ns ns ns 8,10 9 9 Notes 6 6,13 7,13
Parameter Access time from RAS Access time from CAS Access time from address Column add hold from RAS Read command setup time Read command hold time to CAS Read command hold time to RAS Column address to RAS Lead time CAS precharge time Output buffer turn-off time
Min - - - 28 0 0 0 18 4 0
tRAL tCPN tOFF
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AS4LC256K16EO
(R)
Write cycle
-35 Std Symbol Parameter tASC tCAH tAWR tWCS tWCH tWCR tWP tRWL tCWL tDS tDH tDHR Column address setup time Column address hold time Column address hold time to RAS Write command setup time Write command hold time Write command hold time to RAS Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Data-in hold time to RAS Min 0 5 28 0 0 28 5 11 11 0 5 28 Max - - - - - - - - - - - - Min 0 6 35 0 0 35 6 12 12 0 6 35 -45 Max - - - - - - - - - - - - Min 0 10 40 0 0 40 10 12 12 0 10 45 -60 Max Unit - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns 12 12 11 11 Notes
Read-modify-write cycle
-35 Std Symbol Parameter tRWC tRWD tCWD tAWD tRSH(W) tCAS(W) Read-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time CAS to RAS hold time (write) CAS pulse width (write) Min 105 54 28 35 10 15 Max - - - - - - Min 115 58 30 38 10 15 -45 Max - - - - - - Min 120 60 30 40 12 15 -60 Max Unit - - - - - - ns ns ns ns ns ns 11 11 11 Notes
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AS4LC256K16EO
(R)
EDO page mode cycle
Std Symbol tPC tCAP tCP tPCM tCRW tRASP -35 Parameter Read or write cycle time (fast page) Access time from CAS precharge CAS precharge time (fast page) EDO page mode RMW cycle Page mode CAS pulse width (RMW) RAS pulse width Min 15 - 4 56 44 35 Max - 19 - - - 75K Min 17 - 5 58 46 45 -45 Max - 21 - - - 75K Min 25 - 6 60 50 60 -60 Max Unit - 23 - - - 75K ns ns ns ns ns ns Notes 14 13
Refresh cycle
Std Symbol tCSR tCHR tRPC tCPT -35 Parameter CAS setup time (CAS-before-RAS) CAS hold time (CAS-before-RAS) RAS precharge to CAS hold time CAS precharge time (CAS-before-RAS counter test) Min 10 8 0 8 Max - - - - Min 10 8 0 8 -45 Max - - - - Min 10 10 0 8 -60 Max Unit - - - - ns ns ns ns Notes 3 3
Output enable
Std Symbol tROH tOEA tOED tOEZ tOEH -35 Parameter RAS hold time referenced to OE OE access time OE to data delay Output buffer turnoff delay from OE OE command hold time Min 5 - 5 - 8 Max - 10 - 8 - Min 5 - 5 - 8 -45 Max - 10 - 8 - Min 5 - 8 - 8 -60 Max Unit - 10 - 8 - ns ns ns ns ns 8 Notes
Self refresh cycle
-35 Std Symbol Parameter tRASS tRPS tCHS RAS pulse width (CBR self refresh) RAS precharge time (CBR self refresh) CAS hold time (CBR self refresh) Min 100K 85 30 Max - - - Min 100K 85 30 -45 Max - - - Min 100K 85 30 -60 Max - - - Unit ns ns ns Notes
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AS4LC256K16EO
(R)
Notes
1 2 3 ICC1, ICC3, ICC4, and ICC6 depend on cycle rate. ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. An initial pause of 200 s is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks (greater than 8 ms). AC Characteristics assume tT = 5 ns. All AC parameters are measured with a load equivalent to two TTL loads and 60 pF, VIL (min) GND and VIH (max) VCC. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. Assumes three state test load (5 pF and a 380 Thevenin equivalent). Either tRCH or tRRH must be satisfied for a read cycle. tOFF (max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If tWS tWS (min) and tWH tWH (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. If tRWD tRWD (min), tCWD tCWD (min) and tAWD tAWD (min), the cycle is a read-write cycle and the data out will contain data read from the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate. These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles. Access time is determined by the longest of tCAA or tCAC or tCAP. tASC tCP to achieve tPC (min) and tCAP (max) values. These parameters are sampled and not 100% tested.
4 5 6 7 8 9 10 11
12 13 14 15
Key to switching waveform
Undefined/don't care Rising input Falling input
Read cycle waveform
tRC tRAS tRCD tRSH tRP
RAS
tCSH tCRP tASC tRCS tCAH tCAS
UCAS, LCAS
tRAD tASR tRAH tAR tRAL
Address
Row Address
Col Address
tRRH tRCH
WE
tROH
OE
tRAC tAA tOEA tCAC tCLZ tOEZ tOFF
I/O
Data Out
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AS4LC256K16EO
(R)
Upper byte read cycle waveform
tRC tRAS tRP
RAS
tRCD tCSH tCRP tCAS tRSH tCRP
UCAS
tCRP
LCAS
tRAH tRAD tASR tASC tRAL tCAH
Address
Row
tRCS
Column
tRCH tRRH tROH
WE OE
tOEA tRAC tAA tCAC tCLZ tOFF tOEZ
Upper I/O Lower I/O
Data Out
Lower byte read cycle waveform
tRAS tRC tRP
RAS
tRCD tCSH tCRP tCAS tRSH tCRP
LCAS
tCRP
UCAS
tRAH tRAD tASR tASC tRAL tCAH
Address WE
Row
tRCS
Column
tRRH tROH tRCH
OE Upper I/O
tOEA tRAC tAA tCAC tCLZ tOFF tOEZ
Lower I/O
Data Out
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AS4LC256K16EO
(R)
Early write cycle waveform
tRC tRAS tRP
RAS
tCSH tRSH tCRP tRCD tAWR tRAD tASC tASR tRAH tCAH tRAL tCAS
UCAS, LCAS
Address
Row Address
Col Address
tWCR tCWL tRWL tWP tWCS tWCH
WE
OE
tDHR tDS tDH
I/O
Data In
Upper byte early write cycle waveform
tRC tRAS tRP
RAS
tAWR tASR tRAH tRAD tRAL
Address
Row Address
tASC tRCD
Column Address
tCAH tRSH tCSH tCAS tRPC tCWL tWCS tRWL tWCR tWP tWCH tCRP
tCRP
UCAS
tCRP
LCAS
WE OE
tDHR tDS tDH
Upper I/O Lower I/O
Data In
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AS4LC256K16EO
(R)
Lower byte early write cycle waveform
tRAS tRC tRP
RAS
tRAD tASR tRAH tAWR tRAL
Address UCAS
Row Address
tCRP
Column Address
tRPC tASC tRCD tCSH tCAH tCAS tRSH tWCR tRWL tCWL tWCS tWP tWCH tCRP
tCRP
LCAS
WE OE Upper I/O
tDHR tDS tDH
Lower I/O
Data In
Write cycle waveform
tRC tRAS tRP
(OE controlled)
RAS
tCSH tCRP tRCD tRSH tCAS tRAL tAWR tRAD tASR tRAH tASC tCAH
UCAS, LCAS
Address
Row Address
Col Address
tWCR tCWL tWP tRWL
WE
tOEH
OE
tDHR tOED tDS tDH
I/O
Data In
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AS4LC256K16EO
(R)
Upper byte write cycle waveform
tRC tRAS tRP
(OE controlled)
RAS
tRAD tAWR tASR tRAH tRAL
Address
Row Address
tRCD tCRP
Column Address
tCSH tRSH tCAH tASC tCAS tCRP
UCAS
tCRP tRPC tCWL tRWL tWP
LCAS
WE
tOEH
OE
tDS tDH
Upper I/O Lower I/O
Data In
tOED
Lower byte write cycle waveform
tRC tRAS tRP
(OE controlled)
RAS
tRAD tASR tRAH tAWR tRAL
Address
Row Address
tRCD
Column Address
tCAH tCAS tCSH tACS tRSH tRPC tCWL tRWL tWP tCRP
tCRP
LCAS
tCRP
UCAS
WE
tOEH
OE Upper I/O
tDS tDH
Lower I/O
Data In
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AS4LC256K16EO
(R)
Read-modify-write cycle waveform
tRWC tRAS tRP tCAS tCRP tRCD tCSH tRSH
RAS
UCAS, LCAS
tRAD tASR tRAH
tAR tRAL tASC tCAH
Address
Row Address
Col Address
tRWD tAWD tRCS tCWD tOEA tOEZ tOED tRWL tCWL tWP
WE OE
tRAC
tAA tCAC tCLZ tDS tDH
I/O
Data Out
Data In
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AS4LC256K16EO
(R)
Upper byte read-modify-write cycle waveform
tRWC tRAS tRP
RAS
tCSH tRCD tCRP tCAS tRSH tCRP
UCAS
tCRP tRPC tACS tRAL tCAH
LCAS
tRAD tASR tRAH
Address
Row
Column Address
tRWD tAWD tRCS tCWD tOEA tOED tDS tCWL tRWL tWP
WE OE Upper Input
tCLZ tCAC tAA tRAC
Data In
tOEZ
Upper Output
Data Out
tOED
Lower Input Lower Output
Data Out
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AS4LC256K16EO
(R)
Lower byte read-modify-write cycle waveform
tRWC tRAS tRP
RAS
tCRP tRPC tCSH tRCD tCRP tCAS tRSH tCRP
UCAS
LCAS
tRAD tASR tACS tRAH tRAL tCAH
Address
Row
Column Address
tRWD tAWD tRCS tCWD tOEA tCWL tRWL tWP
WE OE Upper Input Upper Output
Data Out
tOED tDS
Lower Input
tRAC tAA tCAC tCLZ
Data In
tOEZ
Lower Output
Data Out
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AS4LC256K16EO
(R)
EDO page mode read cycle waveform
tRASP tRP
RAS
tCSH tCRP tRCD tCAS tCP tRSH tPC
UCAS, LCAS
tRAD tASR tRAH
tAR tASC
tCAH tRAL
Address WE
Row
Col Address
tRCS tRCH tOEA
Col Address
tRCS
Col Address
tRCH tOEA tRRH
OE
tRAC tCLZ tCAC tAA tCAC tCAP
I/O
Data Out
Data Out
EDO page mode byte read cycle waveform
tRASP tRP tRSH tCAS tCP tPC tCRP tCAS tRAH tRAD tASC tCAH tASC tCAH tPC tCP tRAL tASC tRPC tCRP
RAS
tCSH tCRP tRCD tCAS
UCAS
LCAS
tASR
tCAH
Address
Row
Column 1
tRCS tRCH tOEA
Column 2
tRCS tOEA tCAC tCLZ tAA tCAP
Column n
tRCS tRCH tOEA
WE OE
tOFF tOEZ
Lower I/O
tAA tRAC tCAC tCLZ tOFF tOEZ
Data Out 2
tAA tCAP tCAC tCLZ
tOFF tOEZ
Upper I/O
Data Out 1 Data Out n
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AS4LC256K16EO
(R)
EDO page mode early write cycle waveform
tRASP tRAH tRWL tRCD tCSH tCAS tASC tWCS tCP tRAL tPC tCAH tRSH
RAS
tCRP
UCAS, LCAS
tASR tRAD
tAR
Address
Row address
Col address
Col Address
Col Address
tCWL tWP tWCH tOEH
WE OE
tHDR tDS tDH tOED
I/O
Data In
Data In
Data In
EDO page mode byte early write cycle waveform
tRASP tRP tRSH tCAS tCP tPC tCRP tCAS tRAD tRAH tASR tASC tRAL tCAH tPC tRPC tCP
RAS
tCSH tCRP tRCD tCAS tCRP
UCAS
LCAS
tCAH tASC tCAH tASC
Address
Row
Column 1
Column 2
Column n
tRWL tWCH tWCS tWP tCWL
tWCH tWCS tWP tCWL
tWCH tWCS tWP tCWL
WE OE
tDS tDH
Lower I/O
tDS tDH
Data In 2
tDS tDH
Upper I/O
Data In 1 Data In n
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AS4LC256K16EO
(R)
EDO page mode read-modify-write cycle waveform
tRASP tRP
RAS
tPCM tCSH tRCD tCAS tCP tCRP
UCAS, LCAS Address
tASR
tRAD tRAH tCAH tCAH
tRAL tCAH
Row Ad
tRCS
Col Ad
tRWD tCWD tAWD
Col Ad
tCWL tCWD
Col Address
tRWL tCWD tAWD tCWL tWP
WE
tOEA tOEZ tAA tRAC tCLZ tCAC tDS tDH tDS tCLZ tCAC tCAP tCLZ tCAC tOED tOEA
OE
I/O
Data In Data Out
Data In Data Out
Data In Data Out
CAS-before-RAS refresh cycle waveform
tRC tRP tRAS
(WE = VIH)
RAS
tRPC tCPN tCSR tCHR
UCAS, LCAS
tOFF
I/O
RAS only refresh cycle waveform
tRC tRAS tRP tRPC
(WE = OE =VIH or VIL)
RAS
tCRP
UCAS, LCAS Address
tARS
tRAH
Row Address
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AS4LC256K16EO
(R)
EDO page mode byte read-modify-write cycle
tRASP tRP
RAS
tCSH tRCD tCRP tCAS tRSH tCAS
tCRP
UCAS
tPCM tCP tCAS tCP
LCAS
tRAD tRAH tASR tASC tCAH tCAH tAWD tASC tRAL tCAH tAWD tASC
Address
tRCS
R
C1
tAWD tCWD tRWD tWP
C2
Cn
tRWL tCWD tCWD tCWL tWP tOEA tOEA tOED tDS tCAP tDH tCWL tWP
tCWL
WE
tOEA
OE
tOED tDH tDS
Upper Input
tRAC tAA tCAC tCLZ
Data In 1
tOEZ
Data In n
tAA tCAC tCLZ tOEZ
Upper Output
Data Out 1
tOED tDH
Data Out n
Lower Input
tDS tAA tCAC tCLZ tOEZ
Data In 2
Lower Output
Data Out 2
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AS4LC256K16EO
(R)
Hidden refresh cycle (read) waveform
tRC tRAS tPR tCHR tRCD tRSH tCRP tRAS tRC tPR
RAS
tCRP
CAS
tRAD tRAH tASR tASC tAR
Address
Row
tRCS
Col Address
tRRH tOEA
WE OE
tRAC tAA tCAC tCLZ tOFF tOEZ
I/O
Data Out
Hidden refresh cycle (write) waveform
tRC tRAS tRP
RAS
tCRP tRCD tRSH
UCAS, LCAS
tRAD tRAH tASR tASC tRAL tCAH tAR
Address
Row Address
Col Address
tRWL tWCR tWP
tWCS
tWCH
WE
tDS tDHR tDH
I/O OE
Data In
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AS4LC256K16EO
(R)
CAS-before-RAS refresh counter test cycle waveform
tRAS tRSH tRP
RAS
tCSR tCHR tCPT tCAS
UCAS, LCAS
tCAH tRAL
Address
Col Address
tAA tCAC tCLZ tOFF
I/O Read Cycle
tRCS
Data Out
tRRH tRCH tOEA tROH
WE
OE
tRWL tCWL tWP tWCH tWCS
WE Write Cycle
tDH tDS
I/O OE
Data In
tRCS tCWD tAWD
tWP tCWL
WE Read-Write Cycle
tOEA tOED
OE
t AA tCLZ tCAC tDH tOEZ tDS
I/O
Data Out
Data In
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AS4LC256K16EO
(R)
CAS-before-RAS self refresh cycle
tRP tRASS tRPS
RAS
tRPC tCP tCSR tCHS tRPC
UCAS, LCAS
tCEZ
DQ
Typical DC and AC characteristics
1.5 1.4 Normalized access time 1.3 1.2 1.1 1.0 0.9 0.8 2.7 3.0 3.3 3.6 Supply voltage (V) 3.9 Normalized access time Ta = 25C
Normalized access time tRAC vs. supply voltage VCC
1.5 1.4
Normalized access time tRAC vs. ambient temperature Ta
100 90 Typical access time 80 70 60 50 40 30
Typical access time tRAC vs. load capacitance CL
1.3 1.2 1.1 1.0 0.9 0.8 -55 -10 35 80 Ambient temperature (C) 125
50
100 150 200 Load capacitance (pF)
250
70 60 Supply current (mA) 50 40 30 20 10 0.0 2.7
Typical supply current ICC vs. supply voltage VCC
70 60 50 40 30 20 10
Typical supply current ICC vs. ambient temperature Ta
35 30 Power-on current (mA) 25 20 15 10 5 0.0 2
Typical power-on current IPO vs. cycle rate 1/tRC
Supply current (mA) 3.0 3.3 3.6 Supply voltage (V)
3.9
0.0 -55
-10 35 80 125 Ambient temperature (C)
4 6 8 Cycle rate (MHz)
10
4/11/01; V.1.1
Alliance Semiconductor
P. 22 of 25
AS4LC256K16EO
(R)
35 30 Refresh current (mA) 25 20 15 10 5 0 2.7
Typical refresh current ICC3 vs. supply voltage VCC
Typical refresh current ICC3 vs. Ambient temperature Ta 35 30 25 20 15 10 5 Stand-by current (mA) 20 40 60 80 Ambient temperature (C) Refresh current (mA)
Typical TTL stand-by current ICC2 vs. supply voltage VCC 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 2.7 3.0 3.3 3.6 Supply voltage (V) 3.9
3.0 3.3 3.6 Supply voltage (V)
3.9
0 0.0
3.5 3.0 Stand-by current (mA) 2.5 2.0 1.5 1.0 0.5 0.0
Typical TTL stand-by current ICC2 vs. ambient temperature Ta
Output sink current (mA)
70 60 50 40 30 20 10
Typical output sink current IOL vs. output voltage VOL
Output source current (mA) 0.5 1.0 1.5 Output voltage (V)
70 60 50 40 30 20 10 0.0
Typical output source current IOH vs. output voltage VOH
0
20 40 60 Ambient temperature (C)
80
0.0 0.0
2.0
0.0
1.0 2.0 3.0 Output voltage (V)
4.0
35 EDO page mode current (mA) 30 25 20 15 10 5
Typical EDO page mode current ICC4 vs. ambient temperature Ta
EDO page mode current (mA) 0 20 40 60 Ambient temperature (C)
35 30 25 20 15 10 5
Typical EDO page mode current ICC4 vs. supply voltage VCC
0.0 80
0.0 2.7
3.0 3.3 3.6 Supply voltage (V)
3.9
4/11/01; V.1.1
Alliance Semiconductor
P. 23 of 25
AS4LC256K16EO
(R)
Package dimensions
44 43 42 41 40 39 38 37 36 35 32 31 30 29 28 27 26 25 24 23
c
44-pin TSOP II Min (mm) A Max (mm)
1.2 0.05 0.95
0.30
44-pin TSOP II
E He
A1 A2
b
1.05 0.45 18.54
10.29 11.96
1
2
3
4
5
6
7
8
9 10
13 14 15 16 17 18 19 20 21 22
D l
0-5
c D A2 E He
0.127 (typical) 18.28 10.03 11.56
A A1 b e
e
l
0.80 (typical) 0.40
0.60
40-pin SOJ
e D
40-pin SOJ 400 mil Min Max
E1 E2
Pin 1 B A A1 b A2 E c
Seating Plane
A A1 A2 B b c D E E1 E2 e
0.128 0.026 1.105 0.026 0.015 0.007 1.020 0.395 0.435
0.148 1.115 0.032 0.020 0.013 1.035 0.405 0.445
0.370 (typical)
0 050 (typical)
Capacitance
Parameter Input capacitance I/O capacitance Symbol CIN1 CIN2 CI/O Signals A0 to A8
= 1 MHz, Ta = room temperature, VCC = 3.3V 0.3V)
Test conditions Vin = 0V Vin = Vout = 0V Max 5 7 7 Unit pF pF pF
RAS, UCAS, LCAS, WE, OE Vin = 0V I/O0 to I/O15
4/11/01; V.1.1
Alliance Semiconductor
P. 24 of 25
AS4LC256K16EO
(R)
Ordering codes
Package \ Access time Plastic SOJ, 400 mil, 40-pin TSOP II, 400 mil, 40/44-pin 35 ns AS4LC256K16E0-35JC AS4LC256K16EO-35TC 45 ns AS4LC256K16E0-45JC AS4LC256K16EO-45TC 60 ns AS4LC256K16EO-60JC AS4LC256K16EO-60TC
Part numbering system
AS4LC 3.3V DRAM prefix 256K16E0 Device number -XX RAS access time X Package: J = SOJ T = TSOP II C Commercial temperature range, 0C to 70 C
4/11/01; V.1.1
Alliance Semiconductor
P. 25 of 25

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