 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ENHANCED 4-STAGE COUNTER/SHIFT REGISTER SY100S336A FEATURES s Max. shift frequency of 700MHz s Clock to Q delay max. of 1100ps s Sn to TC speed improved by 50% s Sn set-up and hold time reduced by more than 50% s IEE min. of -170mA s Industry standard 100K ECL levels s Internal 75K input pull-down resistors s Extended supply voltage option: VEE = -4.2V to -5.5V s Voltage and temperature compensation for improved noise immunity s 50% faster than Fairchild 300K at lower power s Function and pinout compatible with Fairchild F100K s Available in 24-pin CERPACK and 28-pin PLCC packages DESCRIPTION The SY100S336A is functionally the same as the SY100S336, but has Sn to TC speed and Sn set-up and hold times significantly improved, allowing for higher clock frequency when used as a cascaded multi-stage counter. The SY100S336A functions either as a modulo-16 up/ down counter or as a 4-bit bidirectional shift register and is designed for use in high-performance ECL systems. Three Select inputs (Sn) are provided for determining the mode of operation. The Function Table lists the available modes of operation. In order to allow cascading for multistage counters, two Count Enable controls (CEP, CET) are provided. The CET input also functions as the Serial Data input (S0) for a shift-up operation, while the D3 input serves as the Serial Data input for the shift-down operation. When the device is in the counting mode, the Terminal Count (TC) goes to a logical LOW when the count reaches 15 for count-up or reaches 0 for count-down. When in the shift mode, the TC output simply repeats the Q3 output. The flexiblity provided by the TC/Q3 output and the D0/ CET input allows these signals to be interconnected from one stage to the next higher stage for multistage counting or shift-up operations. The individual Presets (Pn) allow initialization of the counter by entering data in parallel to preset the counter. A logic HIGH on the Master Reset (MR) overrides all other inputs and asynchronously clears the flip-flops. An additional synchronous Clear is provided, as well as a complement function which synchronously inverts the contents of the flip-flops. All inputs have 75K pulldown resistors. PIN CONFIGURATIONS P2 P3 VEES Q3 Q3 D3 P1 11 10 9 8 7 6 5 P0 CP VEE VEES MR S0 S1 12 13 14 15 16 17 18 4 3 2 1 28 27 26 Q2 Q2 VCCA VCC VCC Q1 Q1 Top View PLCC J28-1 PIN NAMES Pin Function Clock Pulse Input Count Enable Parallel Input (Active LOW) Serial Data Input/Count Enable Trickle Input (Active LOW) Select Inputs Master Reset Input VEE Substrate VCCO for ECL Outputs Preset Inputs Serial Data Input Terminal Count Output Data Outputs Complementary Data Outputs 19 20 21 22 23 24 25 CEP D0/CET VEES S0 MR VEE TC Q0 Q0 S2 CP P0 S1 CP CEP S2 CEP D0/CET TC Q0 Q0 1 2 3 4 5 6 24 23 22 21 20 19 18 Top View Flatpack F24-1 17 16 15 14 D0/CET P1 P2 P3 D3 Q3 Q3 S0 -- S2 MR VEES VCCA P0 - P3 D3 TC Q0 -- Q3 Q0 -- Q3 13 7 8 9 10 11 12 Q1 VCC VCCA Q1 Q2 Q2 Rev.: G Amendment: /0 1 Issue Date: July, 1999 Micrel SY100S336A BLOCK DIAGRAM D3 D0/CET S0 CEP S1 S2 TC T Q0 T Q0 R T RC T T Q1 T T Q2 T R Q1 T TC R Q2 T TC T T Q3 T T R Q3 T TC CP MR P0 Q0 Q0 P1 Q1 Q1 P2 Q2 Q2 P3 Q3 Q3 2 Micrel SY100S336A TRUTH TABLE(1) Inputs MR L L L L L L L L L L L L H H H H H H H H H S2 L L L L H H H H H H H H L L L L H H H H H S1 L L H H L L L L H H H H L L H H L L L H H S0 L H L H L L L H L L L H L H L H L L H L H CEP X X X X L H X X L H X X X X X X X X X X X D0/CET X X X X L L H X L L H X X X X X L H X X X D3 X X X X X X X X X X X X X X X X X X X X X CP u u u u u X X u u X X X X X X X X X X X X Q0 Q0 Q0 L L L L L L L L L Q0 Q0 L Q0 P0 Q0 Q1 D0 Q1 P1 Q1 Q2 Q0 Outputs Q2 P2 Q2 Q3 Q1 Q3 P3 Q3 D3 Q2 TC L L D3 Q3* x Q3 Q3 L x H H Q3 Q3 Q3 L L L L L L L L L H H L L L L L H H H H Mode Preset (Parallel Load) Invert Shift Left Shift Right Count Down Count Down with CEP Not Active Count Down with CET Not Active Clear Count Up Count Up with CEP Not Active Count Up with CET Not Active Hold Asynchronous Master Reset (Q0-3) minus 1 Q1 Q1 L Q2 Q2 L (Q0-3) plus 1 Q1 Q1 Q1 L L L L L L L L L Q2 Q2 Q2 L L L L L L L L L NOTE: 1. H = High Voltage Level L = Low Voltage Level X = Don't Care u = LOW-to-HIGH Transition x = L if Q0 - Q3 = LLLL H if Q0 - Q3 LLLL = L if Q0 - Q3 = HHHH H if Q0 - Q3 HHHH * Before the clock, TC is Q3; after the clock, TC is Q2 DC ELECTRICAL CHARACTERISTICS VEE = -4.2V to -5.5V unless otherwise specified, VCC = VCCA = GND Symbol IIH IEE Parameter Input HIGH Current, All Inputs Power Supply Current Min. -- -170 Typ. -- -120 Max. 200 -60 Unit A mA Condition VIN = VIH (Max.) Inputs Open 3 Micrel SY100S336A AC ELECTRICAL CHARACTERISTICS CERPACK VEE = -4.2V to -5.5V unless otherwise specified, VCC = VCCA = GND TA = 0C Symbol fshift tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tS Parameter Shift Frequency Propagation Delay CP to Qn, Qn Propagation Delay CP to TC Propagation Delay MR to Qn, Qn Propagation Delay MR to TC Propagation Delay D0/CET to TC Propagation Delay Sn to TC Transition Time 20% to 80%, 80% to 20% Set-up Time D3 Pn D0/CET to CEP Sn MR (Release Time) Hold Time D3 Pn D0/CET to CEP Sn Pulse Width HIGH, CP, MR Min. 700 450 600 500 600 400 400 300 Max. -- 1200 1900 1400 1900 1200 1500 900 TA = +25C Min. 700 450 600 500 600 400 400 300 Max. -- 1200 1900 1400 1900 1200 1500 900 TA = +85C Min. 700 450 600 500 600 400 400 300 Max. -- 1200 1900 1400 1900 1200 1500 900 Unit MHz ps ps ps ps ps ps ps ps 800 800 700 1000 900 200 200 200 -200 -- -- -- -- -- -- -- -- -- -- 800 800 800 700 1000 900 200 200 200 -200 -- -- -- -- -- -- -- -- -- -- 800 800 800 700 1000 900 200 200 200 -200 -- -- -- -- -- -- ps -- -- -- -- 800 ps Condition tH tpw (H) 4 Micrel SY100S336A AC ELECTRICAL CHARACTERISTICS PLCC VEE = -4.2V to -5.5V unless otherwise specified, VCC = VCCA = GND TA = 0C Symbol fshift tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tS Parameter Shift Frequency Propagation Delay CP to Qn, Qn Propagation Delay CP to TC Propagation Delay MR to Qn, Qn Propagation Delay MR to TC Propagation Delay D0/CET to TC Propagation Delay Sn to TC Transition Time300 20% to 80%, 80% to 20% Set-up Time D3 Pn D0/CET to CEP Sn MR (Release Time) Hold Time D3 Pn D0/CET to CEP Sn Pulse Width HIGH, CP, MR Min. 700 450 600 500 600 400 400 900 Max. -- 1100 1800 1300 1800 1100 1500 300 TA = +25C Min. 700 450 600 500 600 400 400 900 Max. -- 1100 1800 1300 1800 1100 1500 300 TA = +85C Min. 700 450 600 500 600 400 400 900 Max. -- 1100 1800 1300 1800 1100 1500 ps ps 800 800 700 1000 900 200 200 200 -200 -- -- -- -- -- -- -- -- -- -- 800 800 800 700 1000 900 200 200 200 -200 -- -- -- -- -- -- -- -- -- -- 800 800 800 700 1000 900 200 200 200 -200 -- -- -- -- -- -- ps -- -- -- -- 800 ps Unit MHz ps ps ps ps ps ps Condition tH tpw (H) 5 Micrel SY100S336A TIMING DIAGRAMS DATA 0.7 0.1 ns 0.7 0.1 ns -0.95V 80% 50% 20% -1.69V CLOCK 1/fshift tPHL tPLH tpw (H) OUTPUT 50% tPLH tPHL OUTPUT tTLH tTHL Propagation Delay (Clock) and Transition Times 0.7 0.1 ns 0.7 0.1 ns -0.95V 80% 50% 20% -1.69V tS (RELEASE TIME) tpw (H) MR CLOCK 50% tPHL tPLH OUTPUT 50% tPLH tPHL 80% 50% 20% OUTPUT Propagation Delay (Reset) 6 Micrel SY100S336A TIMING DIAGRAMS 0.7 0.1 ns INPUT 0.7 0.1 ns -0.95V 80% 50% 20% -1.69V tPHL tPLH 80% 50% 20% tTLH tTHL OUTPUT Propagation Delay (Serial Data, Selects) INHIBIT COUNT -0.95V CEP 50% -1.69V ENABLE COUNT tH tS -0.95V D3, Pn, Sn 50% -1.69V tH tS -0.95V CLOCK 50% -1.69V Set-up and Hold Time NOTES: 1. VEE = -4.2V to -5.5V unless otherwise specified, VCC = VCCA = GND. 2. tS is the minimum time before the transition of the clock that information must be present at the data input. 3. tH is the minimum time after the transition of the clock that information must remain unchanged at the data input. PRODUCT ORDERING CODE Ordering Code SY100S336AFC SY100S336AJC SY100S336AJCTR Package Type F24-1 J28-1 J28-1 Operating Range Commercial Commercial Commercial 7 Micrel SY100S336A 24 LEAD CERPACK (F24-1) Rev. 03 8 Micrel SY100S336A 28 LEAD PLCC (J28-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA FAX + 1 (408) 980-9191 + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated 9 |
Price & Availability of SY100S336A
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |