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PRODUCT SPECIFICATION
PE4246
Product Description
The PE4246 is a high-isolation MOSFET RF Switch designed to cover a broad range of applications from DC to 5.0 GHz, and is non-reflective at both RF1 and RF2 ports. This SPST switch integrates a single-pin CMOS control interface, and provides low insertion loss while operating with extremely low bias from a single +3-volt supply. In a typical application, the high isolation PE4246 can replace multiple RF switches of lesser isolation performance. The PE4246 is manufactured in Peregrine's patented Ultra Thin Silicon (UTSi) CMOS process, offering the performance of GaAs with the economy and integration of conventional CMOS. Figure 1. Functional Schematic Diagram
SPST High-Isolation, 50 Absorptive MOSFET RF Switch
Features * Non-reflective 50-ohm RF switch * 50-ohm (0.25 watt) terminations * High isolation: 55 dB at 1 GHz, 48 dB at 3 GHz, typical * Low insertion loss: 0.8 dB at 1 GHz, 0.9 dB at 3 GHz * High linearity: +33 dBm input 1dB compression point * CMOS/TTL single-pin control * Single +3-volt supply operation * Extremely low bias: 33 A @ 3V Figure 2. Package Type
1 6 6-lead MLPM
3 x 3 mm
RF1 CTRL 50 50
RF2
2 3
5 4
Table 1. Electrical Specifications @ +25 C (ZS = ZL = 50 )
Parameter
Operation Frequency Operating Power Insertion Loss
1
Condition
Minimum
DC
Typical
Maximum
5000 30/24
Units
MHz dBm dB dB dB dB dB dB dB dB dB dBm dBm
CTRL=1/CTRL=0 DC-2 GHz 2-3 GHz 3-4 GHz 4-5 GHz DC-2 GHz 2-3 GHz 3-4 GHz 4-5 GHz DC-5 GHz
3
0.8 0.9 1.0 1.3 49 45 43 40 11 30 50 55 48 46 44 20 33
1.0 1.1 1.3 1.8
Isolation Return Loss Input 1 dB Compression Input IP3 Video Feedthrough Switching Time
2
DC-5 GHz DC-5 GHz
15 2
mVpp s
Notes: 1. Device linearity will begin to degrade below 1 MHz. 2. The DC transient at the output of the switch when the control voltage is switched from Low to High or High to Low in a 50 test set-up, measured with 1ns risetime pulses and 500 MHz bandwidth. 3. Note Absolute Maximum ratings in Table 3.
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Page 1 of 7
PE4246
Product Specification
Figure 3. Pin Configuration (Top View)
Device Description The PE4246 high-isolation SPST RF Switch is designed to support a variety of applications where high isolation performance is demanded and a nonreflective input and output is desired. This switch is able to replace multiple lesser performing switches in a very small 3x3 MLPM footprint. Table 5. Truth Table
VDD GND RF1
1 2 3
Exposed Solder Pad
(bottom side)
6 5 4
RF2 GND
CTRL
Table 2. Pin Descriptions
Pin No.
1 2 3 4 5 6
Control Voltage
CTRL = CMOS or TTL High CTRL = CMOS or TTL Low
1
Signal Path
RF1 to RF2 RF1 isolated from RF2
Pin Name
VDD GND RF1 CTRL GND RF2
Description
Nominal 3 V supply connection. Ground connection. RF port.
2 3
Control Logic The control logic input pin (CTRL) is typically driven by a 3-volt CMOS logic level signal, and has a threshold of 50% of VDD. For flexibility to support systems that have 5-volt control logic drivers, the control logic input has been designed to handle a 5volt logic HIGH signal. (A minimal current will be sourced out of the VDD pin when the control logic input voltage level exceeds VDD.) Electrostatic Discharge (ESD) Precautions When handling this UTSi device, observe the same precautions that you would use with other ESDsensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified. Latch-Up Avoidance Unlike conventional CMOS devices, UTSi CMOS devices are immune to latch-up.
CMOS or TTL logic level: High = RF1 to RF2 signal path Low = RF1 isolated from RF2 Ground connection. 3 RF port.
2
Notes: 1. A bypass capacitor should be placed as close as possible to the pin. 2. Both RF pins must be DC blocked by an external capacitor or held at 0 VDC. 3. The exposed pad must be soldered to the ground plane for proper switch performance.
Table 3. Absolute Maximum Ratings
Symbol
VDD VI TST TOP PIN VESD
Parameter/Condition
Power supply voltage Voltage on CTRL input Storage temperature Operating temperature Input power (50), CTRL=1/CTRL=0 ESD voltage (Human Body Model)
Min
-0.3 -0.3 -65 -40
Max
4.0 5.5 150 85 33/24 200
Unit
V V C C dBm V
Table 4. DC Electrical Specifications @ 25 C
Parameter
VDD Power Supply IDD Power Supply Current (VDD = 3V, VCNTL = 3V) Control Voltage High Control Voltage Low 0.7xVDD 0
Min
2.7
Typ
3.0 33
Max
3.3 40 5 0.3xVDD
Unit
V A V V
Copyright Peregrine Semiconductor Corp. 2003
File No. 70/0090~03A|
UTSi CMOS RFIC SOLUTIONS
Page 2 of 7
PE4246
Product Specification
Typical Performance Data @ -40 C to 85 C (Unless Otherwise Noted) Figure 4. Insertion Loss Figure 5. Input 1 dB Compression Point & IIP3
0 -40!C -0.5
60
60
50
Insertion Loss (dB) -1 85!C 25!C
IIP3
50
1dB Compression Point (dBm)
IIP3 (dBm)
-1.5
40
40
-2
30
-2.5
Input 1dB Compression
30
-3 0 1000 2000 3000 4000 5000
20 0 1000 2000 3000 4000
20 5000
Frequency (MHz)
Frequency (MHz)
Figure 6. Isolation
0
-20
Isolation (dB)
-40
-60
-80
-100 0 1000 2000 3000 4000 5000
Frequency (MHz)
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Copyright Peregrine Semiconductor Corp. 2003
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PE4246
Product Specification
Typical Performance Data @ +25 C Figure 7. RF1 Return Loss (CTRL = High) Figure 8. RF2 Return Loss (CTRL = High)
0
0
-5
-5
-10 Return Loss (dB) 0 1000 2000 3000 4000 5000 Return Loss (dB)
-10
-15
-15
-20
-20
-25
-25
-30
-30 0 1000 2000 3000 4000 5000
Frequency (MHz)
Frequency (MHz)
Figure 9. RF1 Return Loss (CTRL = Low)
Figure 10. RF2 Return Loss (CTRL = Low)
0
0
-5
-5
-10 Return Loss (dB) Return Loss (dB) 0 1000 2000 3000 4000 5000
-10
-15
-15
-20
-20
-25
-25
-30
-30
-35
-35 0 1000 2000 3000 4000 5000
Frequency (MHz)
Frequency (MHz)
Copyright Peregrine Semiconductor Corp. 2003
File No. 70/0090~03A|
UTSi CMOS RFIC SOLUTIONS
Page 4 of 7
PE4246
Product Specification
Evaluation Kit Information Evaluation Kit The SPST Switch Evaluation Kit board was designed to ease customer evaluation of the PE4246 SPDT switch. The RF1 port is connected through a 50 transmission line to the top left SMA connector, J1. The RF2 port is connected through a 50 transmission line to the top right SMA connector, J2. A through transmission line connects SMA connectors J3 and J4. This transmission line can be used to estimate the loss of the PCB over the environmental conditions being evaluated. The board is constructed of a two metal layer FR4 material with a total thickness of 0.031". The bottom layer provides ground for the RF transmission lines. The transmission lines were designed using a coplanar waveguide model with trace width of 0.0476", trace gaps of 0.030", dielectric thickness of 0.028", metal thickness of 0.0021" and R of 4.3. Note that the predominate mode for these transmission lines is coplanar waveguide with a ground plane. J5 and J6 provide a means for controlling DC and digital inputs to the device. J6-1 is connected to the device VDD input. J5-1 is connected to the device CNTL input. J5-2 and J6-2 are GND connections. A decoupling capacitor (100 pF) is provided on both CNTL and VDD traces. It is the responsibility of the customer to determine proper supply decoupling for their design application. Removing these components from the evaluation board has not been shown to degrade RF performance. Figure 11. Evaluation Board Layouts
Figure 12. Evaluation Board Schematic
J6-1 100 pF
Optional
VDD
RF2
J2
GND
GND
J1
RF1
CNTL
J5-1 100 pF
Optional
J3
J4
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Copyright Peregrine Semiconductor Corp. 2003
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PE4246
Product Specification
Figure 13. Package Drawing
6-lead MLPM
3.00 C L -A-B4
6 0.125
5
C L
PIN 1 MARK 4 4
3.00
0.10 C 1 0.10 C 2 3 0.125
10+2 -10 0.100 C 0.90 0.10 0.080 C
3
TOP VIEW
DETAIL C 0.025 0.025 0.70 0.05 0.20 0.05 SEATING PLANE -CDETAIL B
0.0250.025
SIDE VIEW
SEE DETAIL B
0.95 EXPOSED PAD
C L
0.35 +0.08 -0.02 0.10 0.05 C 3
0.17 MIN. CAB 0.29 +0.21 -0.08 EXPOSED SLUG/ HEAT SINK 0.24 +0.20 -0.08 0.125 0.17 0.30
1
2
SEE DETAIL A R 0.15 TYP
R0.127 TYP 1.21 0.10 0.605 0.05 THIS FEATURE APPLIES TO BOTH ENDS OF THE PKG. DETAIL A
EXPOSED METALIZED FEATURE EDGE OF PLASTIC BODY
EXPOSED (2X)
6
5
4
3
.20 MIN.
1.050.05 2.010.10
BOTTOM VIEW
1. DIMENSIONS AND TOLERANCES ARE PER ANSi Y14.5 2. DIMENSIONS ARE IN MILLIMETERS, ANGLES ARE IN DEGREES. 3 4 COPLANARITY APPLIES TO EXPOSED HEAT SLUG AS WELL AS THE TERMINALS. PROFILE TOLERANCE APPLIES TO PLASTIC BODY ONLY.
Table 6. Ordering Information
Order Code
4246-01 4246-02 4246-00
Part Marking
4246 4246 PE4246-EK
Description
PE4246-06MLP3x3-12800F PE4246-06MLP3x3-3000C PE4246-06MLP3x3-EK
Package
6-lead 3x3mm MLPM 6-lead 3x3mm MLPM Evaluation Board
Shipping Method
12800 units / Canister 3000 units / T&R 1 / Box
Copyright Peregrine Semiconductor Corp. 2003
File No. 70/0090~03A|
UTSi CMOS RFIC SOLUTIONS
Page 6 of 7
PE4246
Product Specification
Sales Offices
United States
Peregrine Semiconductor Corp.
6175 Nancy Ridge Drive San Diego, CA 92121 Tel 1-858-455-0660 Fax 1-858-455-0770
Japan
Peregrine Semiconductor K.K.
5A-5, 5F Imperial Tower 1-1-1 Uchisaiwaicho, Chiyoda-ku Tokyo 100-0011 Japan Tel: 03-3507-5755 Fax: 03-3507-5601
Europe
Peregrine Semiconductor Europe
Batiment Maine 13-15 rue des Quatre Vents F- 92380 Garches Tel 33-1-47-41-91-73 Fax 33-1-47-41-91-73
Australia
Peregrine Semiconductor Australia
8 Herb Elliot Ave. Homebush, NSW 2140 Australia Tel: 011-61-2-9763-4111 Fax: 011-61-2-9746-1501
For a list of representatives in your area, please refer to our Web site at: http://www.peregrine-semi.com
Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice.
The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user's own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine's products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. Peregrine products are protected under one or more of the following U.S. patents: 6,090,648; 6,057,555; 5,973,382; 5,973,363; 5,930,638; 5,920,233; 5,895,957; 5,883,396; 5,864,162; 5,863,823; 5,861,336; 5,663,570; 5,610,790; 5,600,169; 5,596,205; 5,572,040; 5,492,857; 5,416,043. Other patents are pending.
Preliminary Specification
The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a PCN (Product Change Notice).
Peregrine, the Peregrine logotype, Peregrine Semiconductor Corp., and UTSi are registered trademarks of Peregrine Semiconductor Corporation. Copyright (c) 2003 Peregrine Semiconductor Corp. All rights reserved.
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Copyright Peregrine Semiconductor Corp. 2003
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