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SY89838U
Precision 1:8 LVDS Clock Fanout Buffer with 2:1 Runt Pulse Eliminator Input MUX
General Description
The SY89838U is a low jitter, low skew, high-speed 1:8 fanout buffer with a unique, 2:1 differential input multiplexer (MUX) optimized for redundant source switchover applications. Unlike standard multiplexers, the SY89838U unique 2:1 Runt Pulse Eliminator (RPE) MUX prevents any short cycles or "runt" pulses during switchover. In addition, a unique fail-safe input protection prevents metastable conditions when the selected input clock fails to a DC voltage (voltage between the pins of the differential input drops below 100mV). The SY89838U distributes clock frequencies from 1kHz to 1.5GHz, guaranteed, over temperature and voltage. The differential input includes Micrel's unique, 3-pin input termination architecture that allows customers to interface to any differential signal (AC- or DCcoupled) as small as 100mV (200MvPP) without any level shifting or termination resistor networks in the signal path. The outputs are 350mV compatible LVDS with fast rise/fall times guaranteed to be less than 150ps. The SY89838U operates from a 2.5V 5% supply and is guaranteed over the full industrial temperature range of -40C to +85C. For applications that require 800mV LVPECL outputs, consider the SY89837U. The SY89838U is part of Micrel's high-speed, Precision Edge(R) product line. All support documentation can be found on Micrel's web site at: www.micrel.com.
Precision Edge(R)
Features
* Selects between two clocks, and provides 8 precision, low skew LVDS output copies * 2:1 MUX input provides a glitch-free, stable LVDS output * Guaranteed AC performance over temperature and supply voltage: - Wide operating frequency: 1kHz to >1.5GHz - <150ps tr/tf - <40ps output-to-output skew * Unique patent-pending input isolation design minimizes crosstalk * Fail-safe input prevents oscillation * Ultra-low jitter design: - <1psRMS random jitter - <1psRMS cycle-to-cycle jitter - <10psPP total jitter (clock) - <0.7psRMS MUX crosstalk induced jitter * Unique patent-pending input termination and VT pin accepts DC- and AC-coupled inputs (CML, PECL, LVDS) * 350mV LVDS output swing * Power supply 2.5V +5% * -40C to +85C industrial temperature range * Available in 32-pin (5mm x 5mm) MLF(R) package
Applications
* Redundant clock switchover * Failsafe clock protection
Markets
* * * * LAN/WAN Enterprise Servers ATE Test and Measurements
Precision Edge is a registered trademark of Micrel, Inc MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.
September 2006
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SY89838U
Typical Application
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SY89838U
Ordering Information(1)
Part Number SY89838UMG SY89838UMGTR(2)
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = +25C, DC Electrical only. 2. Tape and Reel.
Package Type MLF-32 MLF-32
Operating Range Industrial Industrial
Package Marking SY89838U with bar line Pb-Free indicator SY89838U with bar line Pb-Free indicator
Lead Finish NiPdAu Pb-Free NiPdAu Pb-Free
Pin Configuration
32-Pin MLF(R) (MLF-32)
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SY89838U
Pin Description
Pin Number 1, 3, 6, 8 Pin Name IN0, /IN0, IN1, /IN1 Pin Function Differential Inputs: These input pairs are the differential signal inputs to the device. These inputs accept AC or DC-coupled signals as small as 100mV (200mVPP). Each pin of a pair internally terminates to a VT pin through 50. Please refer to the "Input Interface Applications" section for more details. Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT0 and VT1 pins provide a center-tap to a termination network for maximum interface flexibility. See the "Input Interface Applications" section for more details. This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25k pull-up resistor and will default to a logic HIGH state if left open. Input threshold is VCC/2. Positive Power Supply: Bypass with 0.1F//0.01F low ESR capacitors as close to VCC pins as possible. Differential Outputs: These LVDS output pairs are a logic function of the IN0, IN1, and SEL inputs. Please refer to the truth table below for details. Unused output pairs must be terminated with 100 across the pair. Ground: Ground pin and exposed pad must be connected to the same ground plane. Power-On Reset (POR) Initialization capacitor. When using the multiplexer with RPE capability, this pin is tied to a capacitor to VCC. The purpose is to ensure the internal RPE logic starts up in a known state. See "Power-On Rest (POR) Description" section for more details regarding capacitor selection. If this pin is tied directly to VCC, the RPE function will be disabled and the multiplexer will function as a normal multiplexer. The CAP pin should never be left open. Reference Voltage: These outputs bias to VCC-1.2V. They are used for ACcoupling inputs (IN, /IN). Connect VREF_AC directly to the VT pin. Bypass with 0.01F low ESR capacitor to VCC. See "Input Interface Applications" section. Maximum sink/source current is 1.5mA.
2, 7
VT0, VT1
31 9, 19, 22, 32 30, 28, 26, 24, 18, 16, 14, 12, 29, 27, 25, 23, 17, 15, 13, 11 20, 21
SEL VCC Q0 - Q7, /Q0 - /Q7 GND, Exposed Pad
10
CAP
4, 5
VREF-AC0 VREF-AC1
Truth Table
Inputs IN0 0 1 X X /IN0 1 0 X X IN1 X X 0 1 /IN1 X X 1 0 SEL 0 0 1 1 Outputs Q 0 1 0 1 /Q 1 0 1 0
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SY89838U
Absolute Maximum Ratings(1)
Supply Voltage (VCC) ...........................-0.5V to +4.0V Input Voltage (VIN) .................................. -0.5V to VCC Input Current Source or sink current on IN, /IN.............. 50mA Termination Current Source or sink current on VT .................. 100mA VREF-AC Source or sink current .......................... 2mA Lead Temperature (soldering, 20 sec.) ..........+260C Storage Temperature (Ts)..................-65C to 150C
Operating Ratings(2)
Supply Voltage (VCC).................. +2.375V to +2.625V Ambient Temperature (TA)................ -40C to +85C Package Thermal Resistance(3) MLF(R) (JA) Still-Air ..................................................... 35C/W MLF(R) (JB) Junction-to-Board .................................... 16C/W
DC Electrical Characteristics(4)
TA = -40C to +85C, unless otherwise stated.
Symbol VCC ICC RIN RDIFF_IN VIH VIL VIN VDIFF_IN VIN_FSI VT_IN VREF-AC
Notes: 1. Permanent device damage may occur if the absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. Package Thermal Resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. JA and JB values are determined for a 4-layer board in still air, unless otherwise stated. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. VIN (max) is specified when VT is floating.
Parameter Power Supply Power Supply Current Input Resistance (IN-to-VT) Differential Input Resistance (IN-to-/IN) Input High Voltage (IN, /IN) Input Low Voltage (IN, /IN) Input Voltage Swing (IN, /IN) Differential Input Voltage Swing |IN-/IN| Input Voltage Threshold that Triggers FSI IN-to-VT (IN, /IN) Output Reference Voltage
Condition No load, max. VCC
Min 2.375
Typ 2.5 250
Max 2.625 350 55 110 VCC VIH-0.2 VCC
Units V mA V V V V
45 90 1.2 0 See Figure 1a. Note 5 See Figure 1b. 0.2 0.4
50 100
30
100 1.8
mV V V
VCC-1.3
VCC-1.2
VCC-1.1
2. 3. 4. 5.
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SY89838U
LVDS Outputs DC Electrical Characteristics(6)
VCC = +2.5V 5%; TA = -40C to + 85C; RL = 100 across output pair, or equivalent, unless otherwise stated.
Symbol VOUT VDIFF-OUT VOCM VOCM Parameter Output Voltage Swing (Q, /Q) Differential Output Voltage Swing |Q - /Q| Output Common Mode Voltage Change in Common Mode Voltage Condition See Figure 1a and 4a See Figure 1b See Figure 4b See Figure 4b Min 250 500 1.125 -50 Typ 325 650 1.275 +50 Max Units mV mV V mV
LVTTL/CMOS DC Electrical Characteristics(6)
VCC = +2.5V 5%; TA = -40C to + 85C, unless otherwise stated.
Symbol VIH VIL IIH IIL
Note: 1. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current
Condition
Min 2.0
Typ
Max 0.8
Units V V A A
-125 -300
30
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SY89838U
AC Electrical Characteristics(7)
VCC = +2.5V 5%; TA = -40C to +85C, RPE enabled, Input tr/tf 600ps (20% to 80%), RL = 100, unless otherwise stated. Symbol fMAX tpd Parameter Maximum Operating Frequency Differential Propagation Delay IN-to-Q SEL-to-Q SEL-to-Q tpd Tempco tskew tJitter Differential Propagation Delay Temperature Coefficient Output-to-Output Skew Part-to-Part Skew Note 9 Note 10 Note 11 Note 12 Note 13 Note 14 At full output swing. 40 80 VIN 250mV, Note 8 RPE enabled, see Timing Diagram RPE disabled (VIN = VCC/2) 115 20 40 200 1 1 10 0.7 150 500 700 950 17 1000 ps Cycles ps fs/oC ps ps psRMS psRMS psPP psRMS ps Condition RPE enabled Min 1.5 Typ 2.0 Max Units GHz
Clock
Random Jitter
Cycle-to-cycle Jitter Total Jitter
Crosstalk-Induced Jitter tR, tF
Notes: 1. 2. 3. 4. 5. 6. 7. 8.
Output Rise/Fall Time (20% to 80%)
High-frequency AC-parameters are guaranteed by design and characterization. Propagation delay is a function of rise and fall time at IN. See "Typical Operating Characteristics" for more details. Output-to-output skew is measured between two different outputs under identical transitions. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs. Random jitter is measured with a K28.7 character pattern, measured at 12
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SY89838U
Functional Description
RPE MUX and Fail-Safe Input The SY89838U is optimized for clock switchover applications where switching from one clock to another clock without runt pulses (short cycles) is required. It features two unique circuits: Runt-Pulse Eliminator (RPE) Circuit: The RPE MUX provides a "glitchless" switchover between two clocks and prevents any runt pulses from occurring during the switchover transition. The design of both clock inputs is identical (i.e., the switchover sequence and protection is symmetrical for both input pair, IN0 or IN1. Thus, either input pair may be defined as the primary input). If not required, the RPE function can be permanently disabled to allow the switchover between inputs to occur immediately. If the CAP pin is tied directly to VCC, the RPE function will be disabled and the multiplexer will function as a normal multiplexer. Fail-Safe Input (FSI) Circuit: The FSI function provides protection against a selected input pair that drops below the minimum amplitude requirement. If the selected input pair drops sufficiently below the 100mV minimum singleended input amplitude limit (VIN), or 200mV differentially (VDIFF_IN), the output will latch to the last valid clock state. RPE and FSI Functionality The basic operation of the RPE MUX and FSI functionality is described with the following four case descriptions. All descriptions are related to the true inputs and outputs. The primary (or selected) clock is called CLK1; the secondary (or alternate) clock is called CLK2. Due to the totally asynchronous relation of the IN and SEL signals and an additional internal protection against metastability, the number of pulses required for the operations described in cases 1-4 can vary within certain limits. Refer to "Timing Diagrams" for more detailed information. Case #1 Two Normal Clocks and RPE Enabled In this case the frequency difference between the two running clocks IN0 and IN1 must not be greater than 1.5:1. For example, if the IN0 clock is 500MHz, the IN1 clock must be within the range of 334MHz to 750MHz. If the SEL input changes state to select the alternate clock, the switchover from CLK1 to CLK2 will occur in three stages. * Stage 1: The output will continue to follow CLK1 for a limited number of pulses. * Stage 2: The output will remain LOW for a limited number of pulses of CLK2. * Stage 3: The output follows CLK2.
Stage 1
Stage 2
Stage 3
CLK1 CLK2 SEL
Select CLK 1 Select CLK 2
OUTPUT
Runt pulse eliminated from output 3 to 5 falling edges of CLK1 4 to 5 falling edges of CLK2
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Micrel, Inc. Case #2 Input Clock Failure: Switching from a selected clock stuck HIGH to a valid clock (RPE enabled) If CLK1 fails HIGH before the RPE MUX selects CLK2 (using the SEL pin), the switchover will occur in three stages.
SY89838U * Stage 1: The output will remain HIGH for a limited number of pulses of CLK2. * Stage 2: The output will switch to LOW and then remain LOW for a limited number of falling edges of CLK2. Stage 3: The output will follow CLK2.
Stage 1
Stage 2
Stage 3
CLK1 CLK2 SEL
Select CLK 1
Select CLK 2
OUTPUT
Runt pulse eliminated from output 14 to 16 falling edges of CLK2
Note:
Output shows extended clock cycle during switchover. Pulse width for both high and low of this cycle will always be greater than 50% of the CLK2 period.
Case #3 Input Clock Failure: Switching from a selected clock stuck Low to a valid clock (RPE enabled) If CLK1 fails LOW before the RPE MUX selects CLK2 (using the SEL pin), the switchover will occur in two stages.
* *
Stage 1: The output will remain LOW for a limited number of falling edges of CLK2. Stage 2: The output will follow CLK2.
Stage 1
Stage 2
CLK1 CLK2 SEL
Select CLK 1
Select CLK 2
13 to 17 falling edges of CLK2
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Micrel, Inc. Case #4 Input Clock Failure: Switching from the selected clock input stuck in an undetermined state to a valid clock input (RPE enabled) If CLK1 fails to an undetermined state (e.g., amplitude falls below the 100mV (VIN) minimum single-ended input limit, or 200mV differentially) before the RPE MUX selects CLK2 (using the SEL pin), the switchover to the valid clock CLK2 will occur either following Case #2 or Case #3, depending on the last valid state at the CLK1.
SY89838U If the selected input clock fails to a floating, static, or extremely low signal swing, including 0mV, the FSI function will eliminate any metastable condition and guarantee a stable output signal. No ringing and no undetermined state will occur at the output under these conditions. Please note that the FSI function will not prevent duty cycle distortions or runt pulses in case of a slowly deteriorating (but still toggling) input signal. Due to the FSI function, the propagation delay will depend on rise and fall time of the input signal and on its amplitude. Refer to "Typical Operating Characteristics" for more detailed information.
CLK1 CLK2 SEL
Select CLK 1
Select CLK 2
OUTPUT
as in case #2 as in case #3
Power-On Reset (POR) Description
The SY89838U includes an internal power-on reset (POR) function to ensure the RPE logic starts-up in a known logic state once the power-supply voltage is stable. An external capacitor connected between VCC and the CAP pin (pin 10) controls the delay for the power-on reset function. Calculation of the required capacitor value is based on the time the system power supply needs to power up to a minimum of 2.3V. The time constant for the internal power-on-reset must be greater than the time required for the power supply to ramp up to a minimum of 2.3V. The following formula describes this relationship: C(F)
t dPS ( ms ) 12( ms / F )
As an example, if the time required for the system power supply to power up past 2.3V is 12ms, the required capacitor value on pin 10 would be: C(F)
12ms 12( ms / F )
C(F) 1F
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SY89838U
Typical Operating Characteristics
VCC = 2.5V, GND = 0V, VIN 250mVpk, tr/tf 300ps, RL = 100 across output pair; TA = 25C, unless otherwise stated.
Propagation Delay Variation vs. Input Rise/Fall Time
1000 PROPAGATION DELAY (ps) 900 800 700 600 500 400 300 200 100 0 VIN = 200mVPK 0 100 200 300 400 500 600 INPUT RISE/FALL TIME (ps) tpd (max)
tpd (min)
Propagation Delay Variation vs. Input Rise/Fall Time
1000 PROPAGATION DELAY (ps) tpd (max) PROPAGATION DELAY (ps) 900 800 700 600 500 400 300 200 100 0 VIN = 400mVPK 0 100 200 300 400 500 600 INPUT RISE/FALL TIME (ps) 1000 900 800 700 600 500 400 300 200 100 0
Propagation Delay Variation vs. Input Rise/Fall Time
tpd (max)
tpd (min)
tpd (min)
VIN = 800mVPK 0 100 200 300 400 500 600 INPUT RISE/FALL TIME (ps)
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SY89838U
Singled-Ended and Differential Swings
VDIFF_IN, VDIFF_OUT 700 mV (typical) VIN, VOUT 350 mV (typical)
Figure 1a. Singled-Ended Voltage Swing
Figure1b. Differential Voltage Swing
Input Stage
Figure 2. Simplified Differential Input Stage
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SY89838U
Input Interface Applications
option: may connect VT to VCC Figure 3a. LVPECL Interface (DC-Coupled) Figure 3b. LVPECL Interface (AC-coupled) Figure 3c. CML Interface (DC-Coupled)
Figure 3d. CML Interface (AC-Coupled)
Figure 3e. LVDS Interface (DC-Coupled)
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SY89838U
LVDS Output Interface Applications
LVDS specifies a small swing of 325mV typical, on a nominal 1.2V common mode above ground. The common mode voltage has tight limits to permit large variations in ground between an LVDS driver and receiver. Also, change in common mode voltage, as a function of data input, is kept to a minimum, to keep EMI low.
50 VOUT VOH, VOL VOH, VOL 100 1% 50 VCOM VCOM
GND Figure 4a. LVDS Differential Measurement
GND Figure 4b. LVDS Common Mode Measurement
Related Product and Support Documentation
Part Number SY89837U Function Presision 1:8 LVPECL Fanout Buffer with 2:1 Runt Pulse Eliminator Input Mux MLFTM Application Note HBW Solutions New Products and Applications Data Sheet Link www.micrel.com/_PDF/HBW/SY89837u.pdf www.amkor.com/products/notes_papers/MLFAppNote.pdf www.micrel.com/product-info/products/solutions.shtml
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SY89838U
Package Information
32-Pin (5mm x 5mm) MLF(R) (MLF-32)
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SY89838U
PCB Thermal Consideration for 32-Pin MLF(R) Package (Always solder, or equivalent, the exposed pad to the PCB) Package Notes:
1. 2. 3. Package meets Level 2 qualification. All parts are dry-packaged before shipment. Exposed pads must be soldered to a ground for proper thermal management.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2005 Micrel, Incorporated.
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