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NBSG11 2.5V/3.3V SiGe 1:2 Differential Clock Driver with RSECL* Outputs
*Reduced Swing ECL
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The NBSG11 is a 1-to-2 differential fanout buffer, optimized for low skew and ultra-low JITTER. Inputs incorporate internal 50 W termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), CML, LVCMOS, LVTTL, or LVDS. Outputs are RSECL (Reduced Swing ECL), 400 mV.
MARKING DIAGRAM*
SG 11 LYW
* * * * * * *
Maximum Input Clock Frequency up to 12 GHz Typical Maximum Input Data Rate up to 12 Gb/s Typical 30 ps Typical Rise and Fall Times 125 ps Typical Propagation Delay RSPECL Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V RSNECL Output with RSNECL or NECL Inputs with Operating Range: VCC = 0 V with VEE = -2.375 V to -3.465 V RSECL Output Level (400 mV Peak-to-Peak Output), Differential Output Only 50 W Internal Input Termination Resistors
FCBGA-16 BA SUFFIX CASE 489
QFN-16 MN SUFFIX CASE 485G
SG11 ALYW
* * Compatible with Existing 2.5 V/3.3 V LVEP, EP, and LVEL Devices
A = Assembly Location L = Wafer Lot Y = Year W = Work Week *For further details, refer to Application Note AND8002/D
ORDERING INFORMATION
Device NBSG11BA NBSG11BAR2 Package 4x4 mm FCBGA-16 4x4 mm FCBGA-16 3x3 mm QFN-16 3x3 mm QFN-16 Shipping 100 Units / Tray 500 / Tape & Reel
NBSG11MN NBSG11MNR2
123 Units / Rail 3000 / Tape & Reel
Board NBSG11BAEVB
Description NBSG11BA Evaluation Board
(c) Semiconductor Components Industries, LLC, 2003
1
April, 2003 - Rev. 6
Publication Order Number: NBSG11/D
NBSG11
1 A
VTCLK
2
NC
3
NC
4
Q1
VEE 16 VTCLK
NC 15
NC 14
VCC 13 Exposed Pad (EP)
1 2 NBSG11 3 4
12 11 10 9
Q0 Q0 Q1 Q1
B
CLK
VEE
VCC
Q1
CLK
Q0
C
CLK
VEE
VCC
CLK VTCLK
D
VTCLK
NC
NC
Q0
5 VEE
6 NC
7 NC
8 VCC
Figure 1. BGA-16 Pinout (Top View)
Figure 2. QFN-16 Pinout (Top View)
Table 1. Pin Description
Pin BGA D1 C1 QFN 1 2 Name VTCLK CLK I/O ECL, CML, LVCMOS, LVDS, LVTTL Input ECL, CML, LVCMOS, LVDS, LVTTL Input RSECL Output RSECL Output RSECL Output RSECL Output Description Internal 50 W Termination Pin. See Table 2. Inverted Differential Input. Internal 75 kW to VEE and 36.5 kW to VCC.
B1
3
CLK
Noninverted Differential Input. Internal 75 kW to VEE.
A1 B2,C2 A2,A3,D2, D3 B3,C3 A4 B4 C4 D4 N/A
4 5,16 6,7,14,15 8,13 9 10 11 12 -
VTCLK VEE NC VCC Q1 Q1 Q0 Q0 EP
Internal 50 W Termination Pin. See Table 2. Negative Supply Voltage No Connect Positive Supply Voltage Inverted Differential Output 1. Typically Terminated with 50 W to VTT = VCC - 2 V Noninverted Differential Output 1. Typically Terminated with 50 W to VTT = VCC - 2 V Inverted Differential output 0. Typically Terminated with 50 W to VTT = VCC - 2 V Noninverted Differential Output 0. Typically Terminated with 50 W to VTT = VCC - 2 V Exposed Pad (Note 2)
1. The NC pins are electrically connected to the die and must be left open. 2. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad on package bottom (see case drawing) must be attached to a heat-sinking conduit. 3. In the differential configuration when the input termination pins (VTCLK, VTCLK) are connected to a common termination voltage, and if no signal is applied then the device will be susceptible to self-oscillation.
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VCC VTCLK 36.5 KW 50 W CLK CLK 50 W VTCLK VEE 75 KW 75 KW Q0 Q0 Q1 Q1
Figure 3. Logic Diagram
Table 2. Interfacing Options
INTERFACING OPTIONS CML LVDS AC-COUPLED RSECL, PECL, NECL LVTTL, LVCMOS CONNECTIONS Connect VTCLK and VTCLK to VCC Connect VTCLK and VTCLK together Bias VTCLK and VTCLK Inputs within (VIHCMR) Common Mode Range Standard ECL Termination Techniques An external voltage should be be applied to the unused complementary differential input. Nominal voltage is 1.5 V for LVTTL and VCC/2 for LVCMOS inputs.
Table 3. ATTRIBUTES
Characteristics Internal Input Pulldown Resistor (CLK, CLK) Internal Input Pullup Resistor (CLK) ESD Protection Moisture Sensitivity (Note 4) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 4. For additional information, see Application Note AND8003/D. Human Body Model Machine Model FCBGA-16 QFN-16 Oxygen Index: 28 to 34 Value 75 kW 36.5 kW > 2 kV > 100 V Level 3 Level 1 UL 94 V-0 @ 0.125 in 125
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Table 4. MAXIMUM RATINGS (Note 5)
Symbol VCC VEE VI VINPP Iout TA Tstg qJA Parameter Positive Power Supply Negative Power Supply Positive Input Negative Input Differential Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (Note 6) 0 LFPM 500 LFPM 0 LFPM 500 LFPM 1S2P (Note 6) 2S2P (Note 7) < 15 Seconds 16 FCBGA 16 FCBGA 16 QFN 16 QFN 16 FCBGA 16 QFN |D - D| Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V VCC - VEE w VCC - VEE < Continuous Surge 16 FCBGA 16 QFN 2.8 V 2.8 V VI VCC VI VEE Condition 2 Rating 3.6 -3.6 3.6 -3.6 2.8 |VCC - VEE| 25 50 -40 to +70 -40 to +85 -65 to +150 108 86 41.6 35.2 5.0 4.0 225 Units V V V V V V mA mA C C C/W C/W C/W C/W C/W C/W C
qJC Tsol
Thermal Resistance (Junction-to-Case) Wave Solder
5. Maximum Ratings are those values beyond which device damage may occur. 6. JEDEC standard multilayer board - 1S2P (1 signal, 2 power). 7. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
Table 5. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT VCC = 2.5 V; VEE = 0 V (Note 8)
-40 C Symbol IEE VOH VOUTPP VIH Characteristic Negative Power Supply Current Output HIGH Voltage (Note 9) Output Amplitude Voltage Input HIGH Voltage (Single-Ended) (Note 11) Input LOW Voltage (Single-Ended) (Note 12) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 10) Internal Input Termination Resistor Input HIGH Current (@ VIH, VIHMAX) Input LOW Current (@ VIL, VILMIN) Min 45 1450 350 VCC1435 mV VIH2.5 V 1.2 Typ 60 1530 410 VCC1000 mV* VCC1400 mV* Max 75 1575 525 VCC Min 45 1525 350 VCC1435 mV VIH2.5 V 1.2 25C Typ 60 1565 410 VCC1000 mV* VCC1400 mV* Max 75 1600 525 VCC 70C(BGA)/85C(QFN)** Min 45 1550 350 VCC1435 mV VIH2.5 V 1.2 Typ 60 1590 410 VCC1000 mV* VCC1400 mV* Max 75 1625 525 VCC Unit mA mV mV V
VIL
VIH150 mV 2.5
VIH150 mV 2.5
VIH150 mV 2.5
V
VIHCMR
V
RTIN IIH IIL
45
50 80 25
55 150 100
45
50 80 25
55 150 100
45
50 80 25
55 150 100
W mA mA
NOTE: SiGe circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 8. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to -0.965 V. 9. All loading with 50 W to VCC - 2.0 V. VOH/VOL measured at VIH/VIL. 10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 11. VIH cannot exceed VCC. 12. VIL always VEE. *Typicals used for testing purposes. **The device packaged in FCBGA-16 have maximum temperature specification of 70C and devices packaged in QFN-16 have maximum temperature specification of 85C.
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Table 6. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT VCC = 3.3 V; VEE = 0 V (Note 13)
-40 C Symbol IEE VOH VOUTPP VIH Characteristic Negative Power Supply Current Output HIGH Voltage (Note 14) Output Amplitude Voltage Input HIGH Voltage (Single-Ended) (Note 16) Input LOW Voltage (Single-Ended) (Note 17) Input HIGH Voltage Common Mode Range (Note 15) (Differential Configuration) Internal Input Termination Resistor Input HIGH Current (@ VIH, VIHMAX) Input LOW Current (@ VIL, VILMIN) Min 45 2250 350 VCC1435 mV VIH2.5 V 1.2 Typ 60 2330 410 VCC1000 mV* VCC1400 mV* Max 75 2375 525 VCC Min 45 2325 350 VCC1435 mV VIH2.5 V 1.2 25C Typ 60 2365 410 VCC1000 mV* VCC1400 mV* Max 75 2400 525 VCC 70C(BGA)/85C(QFN)** Min 45 2350 350 VCC1435 mV VIH2.5 V 1.2 Typ 60 2390 410 VCC1000 mV* VCC1400 mV* Max 75 2425 525 VCC Unit mA mV mV V
VIL
VIH150 mV 3.3
VIH150 mV 3.3
VIH150 mV 3.3
V
VIHCMR
V
RTIN IIH IIL
45
50 80 25
55 150 100
45
50 80 25
55 150 100
45
50 80 25
55 150 100
W mA mA
NOTE: SiGe Circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 13. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to -0.165 V. 14. All loading with 50 W to VCC - 2.0 V. VOH/VOL measured at VIH/VIL. 15. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 16. VIH cannot exceed VCC. 17. VIL always VEE. *Typicals used for testing purposes. **The device packaged in FCBGA-16 have maximum temperature specification of 70C and devices packaged in QFN-16 have maximum temperature specification of 85C.
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Table 7. DC CHARACTERISTICS, NECL OR RSNECL INPUT WITH NECL OUTPUT
VCC = 0 V; VEE = -3.465 V to -2.375 V (Note 18) -40 C Symbol IEE VOH VOUTPP VIH Characteristic Negative Power Supply Current Output HIGH Voltage (Note 19) Output Amplitude Voltage Input HIGH Voltage (Single-Ended) (Note 21) Input LOW Voltage (Single-Ended) (Note 22) Min 45 -1050 350 VCC1435 mV VIH2.5 V Typ 60 -970 410 VCC1000 mV* VCC1400 mV* Max 75 -925 525 VCC Min 45 -975 350 VCC1435 mV VIH2.5 V 25C Typ 60 -935 410 VCC1000 mV* VCC1400 mV* Max 75 -900 525 VCC 70C(BGA)/85C(QFN)** Min 45 -950 350 VCC1435 mV VIH2.5 V Typ 60 -910 410 VCC1000 mV* VCC1400 mV* Max 75 -875 525 VCC Unit mA mV mV V
VIL
VIH150 mV 0.0 55 150 100
VIH150 mV 0.0 55 150 100
VIH150 mV 0.0 55 150 100
V
VIHCMR RTIN IIH IIL
Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 20) Internal Input Termination Resistor Input HIGH Current (@ VIH, VIHMAX) Input LOW Current (@ VIL, VILMIN)
VEE+1.2 45 50 80 25
VEE+1.2 45 50 80 25
VEE+1.2 45 50 80 25
V W mA mA
NOTE: SiGe circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 18. Input and output parameters vary 1:1 with VCC. 19. All loading with 50 W to VCC - 2.0 V. VOH/VOL measured at VIH/VIL. 20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 21. VIH cannot exceed VCC. 22. VIL always VEE. *Typicals used for testing purposes. **The device packaged in FCBGA-16 have maximum temperature specification of 70C and devices packaged in QFN-16 have maximum temperature specification of 85C.
Table 8. AC CHARACTERISTICS for FCBGA-16
VCC = 0 V; VEE = -3.465 V to -2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V -40 C Symbol fmax tPLH, tPHL tSKEW Characteristic Maximum Frequency (See Figure 4. Fmax/JITTER) (Note 23) Propagation Delay to Output Differential Duty Cycle Skew (Note 24) Within-Device Skew (Note 25) Device-to-Device Skew (Note 26) RMS Random Clock Jitter fin < 10 GHz Peak-to-Peak Data Dependent Jitter fin < 10 Gb/s VINPP tr tf Input Voltage Swing/Sensitivity (Differential Configuration) (Note 27) Output Rise/Fall Times (20% - 80%) @ 1 GHz Q, Q 75 20 30 0.2 TBD 2600 55 75 20 30 1 0.2 TBD 2600 55 75 20 30 1 0.2 TBD 2600 55 mV ps 1 Min 10.709 90 Typ 12 125 3 6 25 160 15 15 50 Max Min 10.709 90 25C Typ 12 125 3 6 25 160 15 15 50 Max Min 10.709 90 70C Typ 12 125 3 6 25 160 15 15 50 Max Unit GHz ps ps
tJITTER
ps
23. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 W to VCC-2.0 V. For minimum fmax value of 10.709 GHz, output amplitude is approximately 200 mV (as shown in Figure 4, where output P-P spec is shown as a minimum/guarantee of around 150 mV). Input edge rates 40 ps (20% - 80%). 24. See Figure 5. tSKEW = |tPLH - tPHL| for a nominal 50% Differential Clock Input Waveform. 25. Within-Device skew is defined as identical transitions on similar paths through a device. 26. Device-to-device skew for identical transitions at identical VCC levels. 27. VINPP (MAX) cannot exceed VCC - VEE.
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Table 9. AC CHARACTERISTICS for QFN-16 VCC = 0 V; VEE = -3.465 V to -2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V
-40 C Symbol fmax tPLH, tPHL tSKEW Characteristic Maximum Frequency (See Figure 4. Fmax/JITTER) (Note 28) Propagation Delay to Output Differential Duty Cycle Skew (Note 29) Within-Device Skew (Note 30) Device-to-Device Skew (Note 31) RMS Random Clock Jitter fin < 10 GHz Peak-to-Peak Data Dependent Jitter fin < 10 Gb/s VINPP tr tf Input Voltage Swing/Sensitivity (Differential Configuration) (Note 32) Output Rise/Fall Times (20% - 80%) @ 1 GHz Q, Q 75 15 30 0.2 TBD 2600 55 75 20 30 1 0.2 TBD 2600 55 75 20 30 1 0.2 TBD 2600 55 mV ps 1 Min 10.5 90 Typ 12 125 3 6 25 160 15 15 50 Max Min 10.5 90 25C Typ 12 125 3 6 25 160 15 15 50 Max Min 10.5 90 85C Typ 12 125 3 6 25 160 15 15 50 Max Unit GHz ps ps
tJITTER
ps
28. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 W to VCC-2.0 V. For minimum fmax value of 10.5 GHz, output amplitude is approximately 200 mV (as shown in Figure 4, where output P-P spec is shown as a minimum/guarantee of around 150 mV). Input edge rates 40 ps (20% - 80%). 29. See Figure 5. tSKEW = |tPLH - tPHL| for a nominal 50% Differential Clock Input Waveform. 30. Within-Device skew is defined as identical transitions on similar paths through a device. 31. Device-to-device skew for identical transitions at identical VCC levels. 32. VINPP (MAX) cannot exceed VCC - VEE.
600 9.5 OUTPUT VOLTAGE AMPLITUDE (mV) 500 OUTPUT AMP. 400 OUTPUT P-P SPEC 8.5 7.5 6.5 5.5 4.5 3.5 2.5 1.5 0.5 -0.5 JITTERout ps (RMS)
300
200
100
OOUSSOOOOONOOOOONN OU SOO OON OO O O OON OOUSSOONNNNOOOOONN OU SOOOONN OO O USSOOOOONOOOOONN U SOO OON OO O O OON SSOONNNNOOOOONN SOOOONN OO O OOOONOOOOONN O OON OO O OOONOOOOONN OON OO O NOOONNNN N OO O ONNNNOONN OOOOOOO N OO N
RMS JITTER 0 1 2 3 4 5 6 7 8 9 INPUT FREQUENCY (GHz) 10 11 12
Figure 4. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin) at Ambient Temperature (Typical)
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CLK VINPP = VIH(CLK) - VIL(CLK) CLK Q VOUTPP = VOH(Q) - VOL(Q) Q tPLH tPHL
Figure 5. AC Reference Measurement
Q Driver Device Q 50 W 50 W
D Receiver Device D
VTT VTT = VCC - 2.0 V
Figure 6. Typical Termination for Output Driver and Device Evaluation (Refer to Application Note AND8020 - Termination of ECL Logic Devices)
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PACKAGE DIMENSIONS
FCBGA-16 BA SUFFIX PLASTIC 4X4 (mm) BGA FLIP CHIP PACKAGE CASE 489-01 ISSUE O
LASER MARK FOR PIN 1 IDENTIFICATION IN THIS AREA
-XD M
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z. 4. DATUM Z (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. DIM A A1 A2 b D E e S MILLIMETERS MIN MAX 1.40 MAX 0.25 0.35 1.20 REF 0.30 0.50 4.00 BSC 4.00 BSC 1.00 BSC 0.50 BSC
-YK E
M 0.20
3X FEDUCIAL FOR PIN A1 IDENTIFICATION IN THIS AREA A B C D
e
4
3
2
1
3
16 X
b 0.15 0.08
M M
S VIEW M-M
ZXY Z
5 0.15 Z A A2 -Z-
A1
16 X
4 DETAIL K
0.10 Z
ROTATED 90 _ CLOCKWISE
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PACKAGE DIMENSIONS
16 PIN QFN MN SUFFIX CASE 485G-01 ISSUE O
-XA M -YNOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION D APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A B C D E F G H J K L M N P R SEATING PLANE MILLIMETERS MIN MAX 3.00 BSC 3.00 BSC 0.80 1.00 0.23 0.28 1.75 1.85 1.75 1.85 0.50 BSC 0.875 0.925 0.20 REF 0.00 0.05 0.35 0.45 1.50 BSC 1.50 BSC 0.875 0.925 0.60 0.80 INCHES MIN MAX 0.118 BSC 0.118 BSC 0.031 0.039 0.009 0.011 0.069 0.073 0.069 0.073 0.020 BSC 0.034 0.036 0.008 REF 0.000 0.002 0.014 0.018 0.059 BSC 0.059 BSC 0.034 0.036 0.024 0.031
B N 0.25 (0.010) T 0.25 (0.010) T J R 0.08 (0.003) T E H G
5 8
C K -T-
L
4
9
F
1 12
16
13
P
D
NOTE 3 M
0.10 (0.004)
TXY
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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