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MJE13009
Preferred Device
SWITCHMODEt Series NPN Silicon Power Transistors
The MJE13009 is designed for high-voltage, high-speed power switching inductive circuits where fall time is critical. They are particularly suited for 115 and 220 V SWITCHMODE applications such as Switching Regulators, Inverters, Motor Controls, Solenoid/Relay drivers and Deflection circuits.
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* VCEO(sus) 400 V and 300 V * Reverse Bias SOA with Inductive Loads @ TC = 100_C * Inductive Switching Matrix 3 to 12 Amp, 25 and 100_C tc @ 8 A, * 700 V Blocking Capability * SOA and Switching Applications Information * Pb-Free Package is Available*
MAXIMUM RATINGS
Rating Collector-Emitter Voltage Collector-Emitter Voltage Emitter-Base Voltage Collector Current Base Current Emitter Current - Continuous - Peak (Note 1) - Continuous - Peak (Note 1) - Continuous - Peak (Note 1) Symbol VCEO(sus) VCEV VEBO IC ICM IB IBM IE IEM PD PD TJ, Tstg Value 400 700 9 12 24 6 12 18 36 2 16 100 800 -65 to +150 Unit Vdc Vdc Vdc Adc Adc Adc
12 AMPERE NPN SILICON POWER TRANSISTOR 400 VOLTS - 100 WATTS
100_C is 120 ns (Typ)
1
2
TO-220AB CASE 221A-09 STYLE 1 3
MARKING DIAGRAM
MJE13009G W W/_C W W/_C _C A Y WW G = Assembly Location = Year = Work Week = Pb-Free Package AY WW
Total Device Dissipation @ TC = 25_C Derate above 25C Total Device Dissipation @ TC = 25_C Derate above 25C Operating and Storage Junction Temperature Range
THERMAL CHARACTERISTICS
Characteristics Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case Maximum Lead Temperature for Soldering Purposes 1/8 from Case for 5 Seconds Symbol RqJA RqJC TL Max 62.5 1.25 275 Unit _C/W _C/W _C Device MJE13009
ORDERING INFORMATION
Package TO-220 TO-220 (Pb-Free) Shipping 50 Units / Rail 50 Units / Rail
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Pulse Test: Pulse Width = 5 ms, Duty Cycle 10%. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
MJE13009G
Preferred devices are recommended choices for future use and best overall value.
1
February, 2006 - Rev. 7
Publication Order Number: MJE13009/D
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2. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%. SWITCHING CHARACTERISTICS DYNAMIC CHARACTERISTICS ON CHARACTERISTICS (Note 2) SECOND BREAKDOWN OFF CHARACTERISTICS (Note 2)
ELECTRICAL CHARACTERISTICS (TC = 25_C unless otherwise noted)
Crossover Time
Voltage Storage Time
Inductive Load, Clamped (Table 1, Figure 13)
Fall Time
Storage Time
Rise Time
Delay Time
Resistive Load (Table 1)
Output Capacitance (VCB = 10 Vdc, IE = 0, f = 0.1 MHz)
Current-Gain - Bandwidth Product (IC = 500 mAdc, VCE = 10 Vdc, f = 1 MHz)
Base-Emitter Saturation Voltage (IC = 5 Adc, IB = 1 Adc) (IC = 8 Adc, IB = 1.6 Adc) (IC = 8 Adc, IB = 1.6 Adc, TC = 100_C)
Collector-Emitter Saturation Voltage (IC = 5 Adc, IB = 1 Adc) (IC = 8 Adc, IB = 1.6 Adc) (IC = 12 Adc, IB = 3 Adc) (IC = 8 Adc, IB = 1.6 Adc, TC = 100_C)
DC Current Gain (IC = 5 Adc, VCE = 5 Vdc) (IC = 8 Adc, VCE = 5 Vdc)
Second Breakdown Collector Current with base forward biased Clamped Inductive SOA with Base Reverse Biased
Emitter Cutoff Current (VEB = 9 Vdc, IC = 0)
Collector Cutoff Current (VCEV = Rated Value, VBE(off) = 1.5 Vdc) (VCEV = Rated Value, VBE(off) = 1.5 Vdc, TC = 100_C)
Collector-Emitter Sustaining Voltage (IC = 10 mA, IB = 0)
(VCC = 125 Vdc, IC = 8 A, IB1 = IB2 = 1.6 A, tp = 25 ms, Duty Cycle v 1%)
(IC = 8 A, Vclamp = 300 Vdc, IB1 = 1.6 A, VBE(off) = 5 Vdc, TC = 100_C)
Characteristic
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MJE13009
2 VCEO(sus)IIII - 400 Symbol VCE(sat) VBE(sat) IEBO ICEV Cob hFE IS/b - tsv fT td ts tr tf tc Min - - - - - - - 4 - - - - - - - 8 6 - - - 0.12 0.92 0.45 0.06 Typ 180 0.2 1.3 - - - - - - - - - - - - - See Figure 1 See Figure 2 Max 1 1.5 3 2 0.7 2.3 0.7 0.1 1.2 1.6 1.5 40 30 3 1 - - 1 1 5 - mAdc mAdc MHz Unit Vdc Vdc Vdc pF ms ms ms ms ms ms
MJE13009
100 50 IC, COLLECTOR CURRENT (AMP) 20 10 5 2 1 0.5 0.2 TC = 25C dc 100 m 14 10 m 12 IC, COLLECTOR (AMP) 10 8 6 4 2 500 0 0 100 200 3V 300 1.5 400 V 500 600 700 800 VBE(off) = 9 V 5V TC 100C IB1 = 2.5 A
1m s
0.1 0.05
0.02 0.01
THERMAL LIMIT BONDING WIRE LIMIT SECOND BREAKDOWN LIMCURVES APPLY BELOW RATED IT VCEO 5 7 20 30 200 300 10 50 70 100 VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)
VCEV, COLLECTOR-EMITTER CLAMP VOLTAGE (VOLTS)
Figure 1. Forward Bias Safe Operating Area
Figure 2. Reverse Bias Switching Safe Operating Area
The Safe Operating Area figures shown in Figures 1 and 2 are specified ratings for these devices under the test conditions shown. 1 0.8 SECOND BREAKDOWN DERATING
0.6 THERMAL DERATING
0.4
0.2 0
20
40
60
80
100
120
140
160
TC, CASE TEMPERATURE (C)
Figure 3. Forward Bias Power Derating
There are two limitations on the power handling ability of a transistor: average junction temperature and second breakdown. Safe operating area curves indicate IC - VCE limits of the transistor that must be observed for reliable operation; i.e., the transistor must not be subjected to greater dissipation than the curves indicate. The data of Figure 1 is based on TC = 25_C; T J(pk) is variable depending on power level. Second breakdown pulse limits are valid for duty cycles to 10% but must be derated when TC 25_C. Second breakdown limitations do not derate the same as thermal limitations. Allowable current at the voltages shown on Figure 1 may be found at any case temperature by using the appropriate curve on Figure 3. T J(pk) may be calculated from the data in Figure 4. At high case temperatures, thermal limitations will reduce the power that can be handled to values less than the limitations imposed by second breakdown. Use of reverse biased safe operating area data (Figure 2) is discussed in the applications information section.
r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED)
POWER DERATING FACTOR
1 0.7 0.5 0.3 0.2 0.1 0.07 0.05 0.03 0.02 0.01 0.01
D = 0.5 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE 0.02 0.05 0.1 0.2 0.5 1 2 ZqJC(t) = r(t) RqJC RqJC = 1.25C/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) ZqJC(t) 5 10 20 50 P(pk)
t1
t2
DUTY CYCLE, D = t1/t2 100 200 500 1.0 k
t, TIME (ms)
Figure 4. Typical Thermal Response [ZqJC(t)]
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MJE13009
VCE , COLLECTOR-EMITTER VOLTAGE (VOLTS) 50 30 20 2 1.6 IC = 1 A 1.2 3A 5A 8A 12 A
hFE , DC CURRENT GAIN
TJ = 150C
25C
0.8
10 7 5
- 55C VCE = 5 V 0.2 0.3 3 0.5 0.7 1 2 5 7 IC, COLLECTOR CURRENT (AMP) 10 20
0.4 0 0.05 0.07 0.1
TJ = 25C
0.2 0.3 0.5 0.7 1 IB, BASE CURRENT (AMP)
2
3
5
Figure 5. DC Current Gain
Figure 6. Collector Saturation Region
1.4 1.2 V, VOLTAGE (VOLTS) IC/IB = 3 V, VOLTAGE (VOLTS) TJ = -55C 1
0.7 0.6 0.5 0.4 0.3 0.2 0.1 25C - 55C IC/IB = 3
TJ = 150C
0.8 25C 0.6 0.4 0.2 0.3 0.5 0.7 1 2 3 5 7 10 20 IC, COLLECTOR CURRENT (AMP) 150C
0
0.2 0.3
0.5 0.7
1
2
3
5
7
10
20
IC, COLLECTOR CURRENT (AMP)
Figure 7. Base-Emitter Saturation Voltage
Figure 8. Collector-Emitter Saturation Voltage
10K VCE = 250 V IC, COLLECTOR CURRENT ( A) 1K TJ = 150C 125C 100C 10 75C 50C 1 25C 0.1 -0.4 REVERSE FORWARD -0.2 0 +0.2 +0.4 VBE, BASE-EMITTER VOLTAGE (VOLTS) +0.6 C, CAPACITANCE (pF)
4K 2K 1K 800 600 400 200 100 80 60 40 Cob Cib TJ = 25C
100
0.1
0.2 0.5 1 2 5 10 20 50 100 VR, REVERSE VOLTAGE (VOLTS)
200
500
Figure 9. Collector Cutoff Region
Figure 10. Capacitance
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MJE13009
Table 1. Test Conditions for Dynamic Performance
REVERSE BIAS SAFE OPERATING AREA AND INDUCTIVE SWITCHING +5 V 1N4933 0.001 mF TEST CIRCUITS 5V PW DUTY CYCLE 10% tr, tf 10 ns 68 1 k 33 MJE210 33 1N4933 2N2222 1 +5 V k 1k 2N2905 47 100 1/2 W MJE200 - VBE(off) VCC = 125 V RC = 15 W D1 = 1N5820 or Equiv. RB = W +10 V 25 ms RB IB D.U.T. IC Vclamp *SELECTED FOR 1 kV 5.1 k VCE 51 TUT RB D1 SCOPE RESISTIVE SWITCHING
VCC +125 V L MR826* RC
1N4933 0.02 mF 270
-4.0 V
NOTE PW and VCC Adjusted for Desired IC RB Adjusted for Desired IB1
CIRCUIT VALUES
Coil Data: Ferroxcube Core #6656 Full Bobbin (~16 Turns) #16
GAP for 200 mH/20 A Lcoil = 200 mH
VCC = 20 V Vclamp = 300 Vdc
TEST WAVEFORMS
IC ICM t1 VCE VCEM TIME
OUTPUT WAVEFORMS tf CLAMPED tf UNCLAMPED t2 t1 ADJUSTED TO OBTAIN IC t Lcoil (ICM) tf t1 VCC Vclamp t2 t2 Lcoil (ICM) Vclamp
Test Equipment Scope-Tektronics 475 or Equivalent
0 -8 V tr, tf < 10 ns Duty Cycle = 1.0% RB and RC adjusted for desired IB and IC
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MJE13009
APPLICATIONS INFORMATION FOR SWITCHMODE SPECIFICATIONS
INTRODUCTION
The primary considerations when selecting a power transistor for SWITCHMODE applications are voltage and current ratings, switching speed, and energy handling capability. In this section, these specifications will be discussed and related to the circuit examples illustrated in Table 2. (Note 3)
VOLTAGE REQUIREMENTS
Both blocking voltage and sustaining voltage are important in SWITCHMODE applications. Circuits B and C in Table 2 illustrate applications that require high blocking voltage capability. In both circuits the switching transistor is subjected to voltages substantially higher than VCC after the device is completely off (see load line diagrams at IC = Ileakage 0 in Table 2). The blocking capability at this point depends on the base to emitter conditions and the device junction temperature. Since the highest device capability occurs when the base to emitter junction is reverse biased (V CEV), this is the recommended and specified use condition. Maximum I CEV at rated VCEV is specified at a relatively low reverse bias (1.5 V) both at 25C and 100_C. Increasing the reverse bias will give some improvement in device blocking capability. The sustaining or active region voltage requirements in switching applications occur during turn-on and turn-off. If the load contains a significant capacitive component, high current and voltage can exist simultaneously during turn-on and the pulsed forward bias SOA curves (Figure 1) are the proper design limits. For inductive loads, high voltage and current must be sustained simultaneously during turn-off, in most cases, with the base to emitter junction reverse biased. Under these conditions the collector voltage must be held to a safe level at or below a specific value of collector current. This can be accomplished by several means such as active clamping, RC snubbing, load line shaping, etc. The safe level for these devices is specified as a Reverse Bias Safe Operating Area (Figure 2) which represents voltage-current conditions that can be sustained during reverse biased turn-off. This rating is verified under clamped conditions so that the device is never subjected to an avalanche mode. In the four application examples (Table 2) load lines are shown in relation to the pulsed forward and reverse biased SOA curves. In circuits A and D, inductive reactance is clamped by the diodes shown. In circuits B and C the voltage is clamped by
the output rectifiers, however, the voltage induced in the primary leakage inductance is not clamped by these diodes and could be large enough to destroy the device. A snubber network or an additional clamp may be required to keep the turn-off load line within the Reverse Bias SOA curve. Load lines that fall within the pulsed forward biased SOA curve during turn-on and within the reverse bias SOA curve during turn-off are considered safe, with the following assumptions: 1. The device thermal limitations are not exceeded. 2. The turn-on time does not exceed 10 ms (see standard pulsed forward SOA curves in Figure 1). 3. The base drive conditions are within the specified limits shown on the Reverse Bias SOA curve (Figure 2).
CURRENT REQUIREMENTS
An efficient switching transistor must operate at the required current level with good fall time, high energy handling capability and low saturation voltage. On this data sheet, these parameters have been specified at 8 amperes which represents typical design conditions for these devices. The current drive requirements are usually dictated by the V CE(sat) specification because the maximum saturation voltage is specified at a forced gain condition which must be duplicated or exceeded in the application to control the saturation voltage.
SWITCHING REQUIREMENTS
In many switching applications, a major portion of the transistor power dissipation occurs during the fall time (t fi ). For this reason considerable effort is usually devoted to reducing the fall time. The recommended way to accomplish this is to reverse bias the base-emitter junction during turn-off. The reverse biased switching characteristics for inductive loads are discussed in Figure 11 and Table 3 and resistive loads in Figures 13 and 14. Usually the inductive load component will be the dominant factor in SWITCHMODE applications and the inductive switching data will more closely represent the device performance in actual application. The inductive switching characteristics are derived from the same circuit used to specify the reverse biased SOA curves, (See Table 1) providing correlation between test procedures and actual use conditions.
3. For detailed information on specific switching applications, see ON Semiconductor Application Notes AN-719, AN-767.
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MJE13009
RESISTIVE SWITCHING PERFORMANCE
1K 700 500 t, TIME (ns) 300 200 tr VCC = 125 V IC/IB = 5 TJ = 25C t, TIME (ns) 2K ts 1K 700 500 300 200 td @ VBE(off) = 5 V 0.2 0.3 0.5 0.7 1 5 7 2 3 IC, COLLECTOR CURRENT (AMP) 10 20 100 0.2 0.3 tf 0.5 0.7 1 2 5 7 IC, COLLECTOR CURRENT (AMP) 10 20 VCC = 125 V IC/IB = 5 TJ = 25C
100 70 50
Figure 11. Turn-On Time
Figure 12. Turn-Off Time
IC 90% VCEM tsv trv tc 90% IB1 10% VCEM 90% IC tfi
Vclamp tti CURRENT 2 A/DIV
IC VCE VOLTAGE 50 V/DIV IC VCE TIME 20 ns/DIV
Vclamp IB
10% ICM
2% IC
TIME
Figure 13. Inductive Switching Measurements
Figure 14. Typical Inductive Switching Waveforms (at 300 V and 12 A with IB1 = 2.4 A and VBE(off) = 5 V)
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MJE13009
Table 2. Applications Examples of Switching Circuits CIRCUIT
SERIES SWITCHING REGULATOR Collector Current
LOAD LINE DIAGRAMS
TURN-ON (FORWARD BIAS) SOA ton 10 ms DUTY CYCLE 10% PD = 4000 W
2
TIME DIAGRAMS
24 A TC = 100C 12 A TURN- ON
IC
A
VCC VO
350 V
TURN- OFF VCC 400 V
1
TURN-OFF (REVERSE BIAS) SOA 1.5 V VBE(off) 9.0 V DUTY CYCLE 10% 700 V
1
VCE VCC
TIME
t
COLLECTOR VOLTAGE
TIME
t
RINGING CHOKE INVERTER Collector Current
VCC
VO N
B
TURN-ON (FORWARD BIAS) SOA TURN-ON ton 10 ms TURN-ON DUTY CYCLE 10% PD = 4000 W 2 TC = 100C 350 V TURN-OFF (REVERSE BIAS) SOA 12 A TURN-OFF 1.5 V VBE(off) 9.0 V TURN-OFF TURN-OFF DUTY CYCLE 10% TURN-ON 24 A VCC VCC + N(Vo) 400 V
1
IC toff t LEAKAGE SPIKE VCC t
ton VCE VCC+ N(Vo)
700 V
1
COLLECTOR VOLTAGE
PUSH-PULL INVERTER/CONVERTER
Collector Current
C
VCC
VO
TURN-ON (FORWARD BIAS) SOA TURN-ON ton 10 ms TURN-ON DUTY CYCLE 10% PD = 4000 W 2 TC = 100C 350 V TURN-OFF (REVERSE BIAS) SOA 12 A TURN-ON TURN-OFF 1.5 V VBE(off) 9.0 V TURN-OFF DUTY CYCLE 10% 24 A TURN-OFF VCC 400 V
1
IC ton VCE 2 VCC VCC toff t
2 VCC 700 V
1
COLLECTOR VOLTAGE SOLENOID DRIVER 24 A Collector Current TC = 100C 12 A
t
TURN-ON (FORWARD BIAS) SOA TURN-ON ton 10 ms TURN-ON DUTY CYCLE 10% PD = 4000 W 2 350 V TURN-OFF (REVERSE BIAS) SOA TURN-OFF 1.5 V VBE(off) 9.0 V TURN-OFF DUTY CYCLE 10% TURN-OFF TURN-ON VCC 400 V
1
IC ton VCE VCC toff t
VCC
D
SOLENOID
700 V
1
COLLECTOR VOLTAGE
t
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MJE13009
Table 3. Typical Inductive Switching Performance
In resistive switching circuits, rise, fall, and storage times have been defined and apply to both current and voltage waveforms since they are in phase. However, for inductive loads which are common to SWITCHMODE power supplies and hammer drivers, current and voltage waveforms are not in phase. Therefore, separate measurements must be made on each waveform to determine the total switching time. For this reason, the following new terms have been defined. tsv = Voltage Storage Time, 90% IB1 to 10% VCEM trv = Voltage Rise Time, 10-90% VCEM tfi = Current Fall Time, 90-10% ICM tti = Current Tail, 10-2% ICM tc = Crossover Time, 10% VCEM to 10% ICM An enlarged portion of the turn-off waveforms is shown in Figure 13 to aid in the visual identity of these terms.
IIIIIII I I I I I IIIIII IIIII IIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIIII IIIII IIIIIIIIIIIIIIIIIIIII II I I I I I IIIIIIIIIIIIIIIIIIIII IIII IIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I I IIII IIIII I IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIII IIIIII I II IIIIIIIIIIIIIIIIIIIII IIIII
IC AMP 3 5 8 TC _C tsv ns trv ns tfi ns tti ns tc ns 25 100 25 100 25 100 25 100 770 1000 630 820 720 920 640 800 100 230 72 100 55 70 20 32 150 160 26 55 27 50 17 24 200 200 10 30 2 8 2 4 240 320 100 180 77 120 41 54 12 NOTE: All Data recorded In the Inductive Switching Circuit In Table 1.
SWITCHING TIME NOTES For the designer, there is minimal switching loss during storage time and the predominant switching power losses occur during the crossover interval and can be obtained using the standard equation from AN222/D:
PSWT = 1/2 VCCIC(tc) f
Typical inductive switching waveforms are shown in Figure 14. In general, t rv + t fi ] t c. However, at lower test currents this relationship may not be valid. As is common with most switching transistors, resistive switching is specified at 25_C and has become a benchmark for designers. However, for designers of high frequency converter circuits, the user oriented specifications which make this a "SWITCHMODE" transistor are the inductive switching speeds (tc and tsv) which are guaranteed at 100_C.
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MJE13009
PACKAGE DIMENSIONS
TO-220AB CASE 221A-09 ISSUE AA
-T- B
4
SEATING PLANE
F T S
C
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. DIM A B C D F G H J K L N Q R S T U V Z INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 --- --- 0.080 BASE COLLECTOR EMITTER COLLECTOR MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 --- --- 2.04
Q
123
A U K
H Z L V G D N R J
STYLE 1: PIN 1. 2. 3. 4.
SWITCHMODE is a trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
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MJE13009/D

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