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HA-2539
Data Sheet May 2003 FN2896.5
600MHz, Very High Slew Rate Operational Amplifier
The Intersil HA-2539 represents the ultimate in high slew rate, wideband, monolithic operational amplifiers. It has been designed and constructed with the Intersil High Frequency Bipolar Dielectric Isolation process and features dynamic parameters never before available from a truly differential device. With a 600V/s slew rate and a 600MHz gain bandwidth product, the HA-2539 is ideally suited for use in video and RF amplifier designs, in closed loop gains of 10 or greater. Full 10V swing coupled with outstanding AC parameters and complemented by high open loop gain makes the devices useful in high speed data acquisition systems. For further design assistance please refer to Application Note AN541 (Using the HA-2539 Very High Slew Rate Wideband Operational Amplifiers) and Application Note AN556 (Thermal Safe-Operating-Areas For High Current Operational Amplifiers. For military grade product information, the HA-2539/883 data sheet is available upon request.
Features
* Very High Slew Rate . . . . . . . . . . . . . . . . . . . . . . 600V/s * Open Loop Gain. . . . . . . . . . . . . . . . . . . . . . . . . . . 15kV/V * Wide Gain-Bandwidth (AV 10). . . . . . . . . . . . . . 600MHz * Power Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . 9.5MHz * Low Offset Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 8mV * Input Voltage Noise . . . . . . . . . . . . . . . . . . . . . . 6nV/Hz * Output Voltage Swing . . . . . . . . . . . . . . . . . . . . . . . 10V * Monolithic Bipolar Dielectric Construction
Applications
* Pulse and Video Amplifiers * Wideband Amplifiers * High Speed Sample-Hold Circuits * RF Oscillators
Pinout
HA-2539 (PDIP) TOP VIEW
+IN 1 NC 2 V- 3 NC 4 NC 5 NC 6 NC 7 + 14 -IN
Part Number Information
PART NUMBER HA3-2539-5 TEMP. RANGE (oC) 0 to 75 PACKAGE 14 Ld PDIP PKG. NO. E14.3
NOTE: No-Connection (NC) leads may be tied to a ground plane for better isolation and heat dissipation.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
-
13 NC 12 NC 11 NC 10 +V 9 NC 8 OUTPUT
HA-2539
Absolute Maximum Ratings
Supply Voltage Between V+ and V- Terminals . . . . . . . . . . . . . 35V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . 33mARMS
Thermal Information
Thermal Resistance (Typical, Note 2) JA (oC/W) JC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 95 N/A Maximum Internal Quiescent Power Dissipation (Note 1) Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range HA-2539-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Maximum power dissipation with load conditions must be designed to maintain the maximum junction temperature below 150oC for the plastic package. By using Application Note AN556 on Safe Operating Area equations, along with the thermal resistances, proper load conditions can be determined. Heat sinking is recommended above 75oC. 2. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
VSUPPLY = 15V, RL = 1kW, CL < 10pF, Unless Otherwise Specified TEMP. (oC)
PARAMETER INPUT CHARACTERISTICS Offset Voltage
MIN
TYP
MAX
UNITS
25 Full
10.0 -
8 13 20 5 1 10 1 6
15 20 20 25 6 8 -
mV mV V/oC A A A A k pF V pA/Hz
Average Offset Voltage Drift Bias Current
Full 25 Full
Offset Current
25 Full
Input Resistance Input Capacitance Common Mode Range Input Current Noise (f = 1kHz, RSOURCE = 0) Input Voltage Noise (f = 1kHz, RSOURCE = 0) TRANSFER CHARACTERISTICS Large Signal Voltage Gain (Note 3) Common Mode Rejection Ratio (Note 4) Minimum Stable Gain Gain Bandwidth (Notes 5, 6)
25 25 Full 25
25
-
6
-
nV/Hz
25 Full Full
10 5 60
15 72
--
kV/V kV/V dB
25 25
10 -
600
-
V/V MHz
2
HA-2539
Electrical Specifications
VSUPPLY = 15V, RL = 1kW, CL < 10pF, Unless Otherwise Specified (Continued) TEMP. (oC)
PARAMETER OUTPUT CHARACTERISTICS Output Voltage Swing (Notes 3, 10) Output Current (Note 3) Output Resistance Full Power Bandwidth (Notes 3, 7) TRANSIENT RESPONSE (Note 8) Rise Time Overshoot Slew Rate Settling Time: 10V Step to 0.1% POWER REQUIREMENTS Supply Current Power Supply Rejection Ratio (Note 9) NOTES: 3. RL = 1k, VO = 10V. 4. VCM = 10.0V. 5. VO = 90mV. 6. AV = 10.
MIN
TYP
MAX
UNITS
Full
10.0 10 8.7
20 30 9.5
-
V
25 25 25
-
mA MHz
25 25 25 25
550 -
7 15 600 180
-
ns % V/s ns
Full Full
60
20 70
25 -
mA dB
Slew Rate 7. Full Power Bandwidth guaranteed based on slew rate measurement using: FPBW = ---------------------------- . 2V PEAK 8. Refer to Test Circuits section of data sheet. 9. VSUPPLY = +5V, -15V and +15V, -5V.
10. Guaranteed range for output voltage is 10V. Functional operation outside of this range is not guaranteed.
3
HA-2539 Test Circuits and Waveforms
IN + OUT 900
NOTES: 11. VS = 15V. 12. AV = +10. 13. CL 10pF.
100
FIGURE 1. TEST CIRCUIT
A
B
Vertical Scale: A = 0.5V/Div., B = 5.0V/Div. Horizontal Scale: 50ns/Div. FIGURE 2. LARGE SIGNAL RESPONSE
Vertical Scale: Input = 10mV/Div., Output = 50mV/Div. Horizontal Scale: 20ns/Div. FIGURE 3. SMALL SIGNAL RESPONSE NOTES: 14. AV = -10. 15. Load Capacitance should be less than 10pF.
V+
0.001F
200 INPUT + 0.001F
-
1F
OUTPUT <10pF PROBE MONITOR
16. It is recommended that resistors be carbon composition and that feedback and summing network ratios be matched to 0.1%. 17. SETTLE POINT (Summing Node) capacitance should be less than 10pF. For optimum settling time results, it is recommended that the test circuit be constructed directly onto the device pins. A Tektronix 568 Sampling Oscilloscope with S-3A sampling heads is recommended as a settle point monitor.
500
V1F 2k
SETTLE POINT
5k
FIGURE 4. SETTLING TIME CIRCUIT
4
HA-2539 Schematic Diagram
V+ R23 QP22 QP17 QP19 R24 VQP25 VQN1 R6 +INPUT QP8 QP23 QN21 R8 R9 QP3 -INPUT R21 Z1 R25 V+ R10 QN15 R16 QN13 QN29 QN16 V+ QN25 QN12 QP11 QP4 QN10 R7 QN2 C1 R QN7 QN9 R18 OUTPUT R19 R13 QP5 R5 R1 R2 QP18 QP6 QP28 R3 R4
R22
QN20 DZ1 QN14
DZ2
R11
R12
R14
R15
R17 V-
5
HA-2539 Typical Applications
R1 =5 R2 -R2 R1
SET AV = 1+ HA-2539 20 - 100pF 20 R2 + R1
R2 R1 ZIN +
SET AV =
= -3
FIGURE 5. FREQUENCY COMPENSATION BY OVERDAMPING
FIGURE 6. STABILIZATION USING ZIN
R5 1k INPUT R1 10k 3900pF C1 + HA-5170 R3 R2 1k C2
R4 10k 0.039F
HA-2539 + 1k
OUTPUT
FIGURE 7. REDUCING DC ERRORS; COMPOSITE AMPLIFIER
FIGURE 8. DIFFERENTIAL GAIN ERROR (3%) HA-2539 20dB VIDEO GAIN BLOCK
Typical Performance Curves
14 12 INPUT BIAS CURRENT (A) 10 OFFSET VOLTAGE 8 6 4 2 0 -80 -40 0 40 80 120 160 TEMPERATURE (oC) 4 3 2 1 0 7 RSOURCE = 0 6 |VIO| OFFSET VOLTAGE (mV) 5 25 VS = 15V 50 NOISE CURRENT (pA/Hz)
NOISE VOLTAGE (nV/Hz)
20
40
15
30
BIAS CURRENT
10
20
5
VOLTAGE NOISE
10 CURRENT NOISE 0 100K
0 10 100 1K FREQUENCY (Hz) 10K
FIGURE 9. INPUT OFFSET VOLTAGE AND BIAS CURRENT vs TEMPERATURE
FIGURE 10. INPUT NOISE VOLTAGE AND NOISE CURRENT vs FREQUENCY
6
HA-2539 Typical Performance Curves
+40V +30V +20V +10V 0V -10V -20V -30V -40V CMRR (dB) 100
(Continued)
80
60
40
20
Vertical Scale: 10mV/Div. Horizontal Scale: 50ms/Div. FIGURE 11. BROADBAND NOISE (0.1Hz TO 1MHz)
0 1K 10K 100K FREQUENCY (Hz) 1M 10M
FIGURE 12. COMMON MODE REJECTION RATIO vs FREQUENCY
100
100
80 PHASE
GAIN
0
60
40
90
40
20
135
20
0 -20 100
180 225 1K 10K 100K 1M 10M FREQUENCY (Hz) 100M
0
1K
10K
100K FREQUENCY (Hz)
1M
10M
FIGURE 13. POWER SUPPLY REJECTION RATIO vs FREQUENCY
FIGURE 14. OPEN LOOP GAIN/PHASE vs FREQUENCY
28 100 90 CLOSED LOOP GAIN (dB) 80 70 60 50 40 30 20 10 0 -10 100 1K 10K 100K 1M 10M 100M FREQUENCY (Hz) 0 1K 10K 100K 1M 10M 100M FREQUENCY (Hz) VS = 15V 24 OUTPUT VOLTAGE (VP-P) 20 16 12 8 4 VS = 5V VS = 10V VS = 15V
FIGURE 15. CLOSED LOOP FREQUENCY RESPONSE
FIGURE 16. OUTPUT VOLTAGE SWING vs FREQUENCY
7
PHASE (DEGREES)
80 PSRR (dB) GAIN (dB)
60
45
HA-2539 Typical Performance Curves
(Continued)
1.4 NORMALIZED PARAMETERS REFERRED TO VALUES AT 25oC 28 OUTPUT VOLTAGE SWING (VP-P) 24 20 16 12 8 4 0 0 200 400 600 800 RESISTANCE () 1K 1.2K 1.3 1.2 1.1 SLEW RATE 1.0 0.9 0.8 0.7 0.6 -80 BANDWIDTH
-40
0
40
80
120
160
TEMPERATURE (oC)
FIGURE 17. OUTPUT VOLTAGE SWING vs LOAD RESISTANCE
FIGURE 18. NORMALIZED AC PARAMETERS vs TEMPERATURE
28 10 OUTPUT VOLTAGE STEP (V) 8 6 4 2 0 -2 -4 -6 -8 -10 10mV 1mV 1mV SUPPLY CURRENT (mA) 10mV 24 20 16 12 8 4 0 -80 VS = 5V VS = 15V
0
40
80 120 160 SETTLING TIME (ns)
200
240
-40
0
40
80
120
160
TEMPERATURE (oC)
FIGURE 19. SETTLING TIME FOR VARIOUS OUTPUT STEP VOLTAGES
FIGURE 20. POWER SUPPLY CURRENT vs TEMPERATURE
8
HA-2539 Die Characteristics
DIE DIMENSIONS: 62 mils x 76 mils x 19 mils 1575m x 1930m x 483m METALLIZATION: Type: Al, 1% Cu Thickness: 16kA 2kA PASSIVATION: Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.) Silox Thickness: 12kA 2kA Nitride Thickness: 3.5kA 1.5kA SUBSTRATE POTENTIAL (POWERED UP): VTRANSISTOR COUNT: 30 PROCESS: Bipolar Dielectric Isolation
Metallization Mask Layout
+IN
V-
OUTPUT
V+
-IN
9
HA-2539 Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2
E14.3 (JEDEC MS-001-AA ISSUE D)
14 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-
MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 0 12/93
MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240
MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280
-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E
A A1 A2 B B1 C D D1 E
-C-
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm).
E1 e eA eB L N
0.100 BSC 0.300 BSC 0.115 14 0.430 0.150 -
2.54 BSC 7.62 BSC 10.92 3.81 14
2.93
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 10

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