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| TS4851 Mono 1W Speaker and Stereo 160mW Headset BTL Drivers with Digital Volume Control Operating from VCC = 3V to 5.5V Rail to rail input/output Speaker driver with 1 W output @ Vcc = 5V, THD+N = 1%, F = 1kHz, 8 load Headset drivers with 160 mW output @ Vcc = 5V, THD+N = 1%, F = 1kHz, 32 load Headset output is 30mW in stereo @ Vcc = 3V THD+N < 0.5% Max @ 20mW into 32 BTL, 50Hz < Frequency < 20kHz 32-step digital volume control from 34.5dB to +12dB +6dB power up volume and full standby 8 different output modes Pop & click reduction circuitry Low shutdown current (< 100nA) Thermal shutdown protection Flip-chip package 18 x 300m bumps Pin Connections (top view) TS485IJT - Flip-chip TS485EIJT - Lead free Flip-chip Pin Out (top view) Description The TS4851 is a low power audio amplifier that can drive either both a mono speaker or a stereo headset. To the speaker, it can deliver 400 mW (typ.) of continuous RMS output power into an 8 load with a 1% THD+N value. To the headset driver, the amplifier can deliver 30 mW (typ.) per channel of continuous average power into a stereo 32 bridged-tied load with 0.5% THD+N @ 3.3V. This device features a 32-step digital volume control and 8 different output selections. The digital volume and output modes are controlled through a three-digit SPI interface bus. R OUT< R OUT + R IN L IN PHONE IN SPKR OUT+ BYPASS GND VCC SPKR OUT CLK VCC GND L OUT + DATA L OUT - NC ENB Applications Mobile Phones Order Codes Part Number TS4851IJT TS4851EIJT Temperature Range -40, +85C Package Flip-Chip Lead free Flip-Chip Packaging Tape & Reel Marking A51 A51 J = Flip Chip Package - only available in Tape & Reel (JT)) March 2005 Revision 5 1/28 TS4851 Application Information 1 Application Information Figure 1: Application information for a typical application Table 1. External component description Component Cin Functional Description This is the input coupling capacitor. It blocks the DC voltage at, and couples the input signal to the amplifier's input terminals. Cin also creates a highpass filter with the internal input impedance Zin at Fc =1/ (2i x Zin x Cin). This is the Supply Bypass capacitor. It provides power supply filtering. This is the Bypass pin capacitor. It provides half-supply filtering. Cs CB 2/28 SPI Bus Interface TS4851 2 SPI Bus Interface Table 2. Pin description Pin DATA CLK ENB Functional Description This is the serial data input pin. This is the clock input pin. This is the SPI enable pin active at high level. 2.1 Description of SPI operation The serial data bits are organized into a field containing 8 bits of data as shown in Table 3. The DATA 0 to DATA 2 bits determine the output mode of the TS4851 as shown in Table 2. The DATA 3 to DATA 7 bits determine the gain level setting as illustrated by Table 3. For each SPI transfer, the data bits are written to the DATA pin with the least significant bit (LSB) first. All serial data are sampled at the rising edge of the CLK signal. Once all the data bits have been sampled, ENB transitions from logic-high to logic low to complete the SPI sequence. All 8 bits must be received before any data latch can occur. Any excess CLK and DATA transitions will be ignored after the height rising clock edge has occurred. For any data sequence longer than 8 bits, only the first 8 bits will get loaded into the shift register and the rest of the bits will be disregarded. Table 3. Bit allocation DATA LSB DATA 0 DATA 1 DATA 2 DATA 3 DATA 4 DATA 5 DATA 6 DATA 7 MODES Mode 1 Mode 2 Mode 3 gain 1 gain 2 gain 3 gain 4 gain 5 MSB Table 4. Output mode selection: G from -34.5dB to +12dB (by steps of 1.5dB) Output Mode # 0 1 2 3 4 5 6 7 1) DATA 2 0 0 0 0 1 1 1 1 DATA 1 0 0 1 1 0 0 1 1 DATA 0 0 1 0 1 0 1 0 1 SPKERout1 SD 6dBxP SD Gx(R+L) SD Gx(R+L) +6dBxP SD 6dBxP Rout SD SD 0dBxP SD GxR SD GxR+0dBxP GxR+0dBxP Lout SD SD 0dBxP SD GxL SD GxL+0dBxP GxL+0dBxP SD = Shutdown Mode, P = Phone in Input, R = Rin input and L = Lin input 3/28 TS4851 Table 5. Volume control settings K : Gain (dB) -34.5 -33.0 -31.5 -30.0 -28.5 -27.0 -25.5 -24.0 -22.5 -21.0 -19.5 -18.0 -16.5 -15.0 -13.5 -12.0 -10.5 -9.0 -7.5 -6.0 -4.5 -3.0 -1.5 0.0 1.5 3.0 4.5 6 7.5 9 10.5 12 SPI Bus Interface DATA 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DATA 6 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DATA 5 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DATA 4 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DATA 3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 4/28 SPI Bus Interface Figure 2: SPI timing diagram TS4851 5/28 TS4851 Absolute Maximum Ratings 3 Absolute Maximum Ratings Table 6. Key parameters and their absolute maximum ratings Symbol VCC Toper Tstg Tj Rthja Pd ESD ESD 1 Parameter Supply voltage Operating Free Air Temperature Range Storage Temperature Maximum Junction Temperature Flip Chip Thermal Resistance Junction to Ambient Power Dissipation Human Body Model Machine Model Latch-up Immunity Lead Temperature (soldering, 10sec) Lead Temperature (soldering, 10sec) for Lead-Free version 2 Value 6 -40 to + 85 -65 to +150 150 200 Internally Limited 2 100 200 250 260 Unit V C C C C/W kV V mA C 1) 2) All voltages values are measured with respect to the ground pin. Device is protected in case of over temperature by a thermal shutdown active @ 150C Table 7. Operating conditions Symbol VCC Vphin VRin/VLin TSD Rthja 1) Parameter Supply Voltage Maximum Phone In Input Voltage Maximum Rin & Lin Input Voltage Thermal Shut Down Temperature Flip Chip Thermal Resistance Junction to Ambient1 Value 3 to 5.5 GND to VCC GND to VCC 150 90 Unit V V V C C/W Device is protected in case of over temperature by a thermal shutdown active @ 150C 6/28 Electrical Characteristics TS4851 4 Electrical Characteristics Table 8. Electrical characteristics at VCC = +5V, GND = 0V, Tamb = 25C (unless otherwise specified) Symbol ICC Parameter Supply Current Output Mode 7, Vin = 0V, no load All other output modes, Vin = 0V, no load Standby Current Output Mode 0 Output Offset Voltage (differential) Vin = 0V "Logic low" input Voltage "Logic high" input Voltage Output Power SPKERout, RL = 8, THD = 1%, F = 1kHz Rout & Lout, RL = 32, THD = 0.5%, F = 1kHz Total Harmonic Distortion + Noise Rout & Lout, Po = 80mW, F = 1kHz, RL = 32 SPKERout, Po = 800mW, F = 1kHz, RL = 8 Rout & Lout, Po = 50mW, 20Hz < F < 20kHz, RL = 32 SPKERout, Po = 40mW, 20Hz < F < 20kHz, RL = 8 Signal To Noise Ratio (A-Weighted) Power Supply Rejection Vripple = 200mV Vpp, F = 217Hz, Input(s) Terminated 10 Ouput Mode 1 Ouput Mode 2 Ouput Mode 3 (G=+12dB) Ouput Mode 4 (G=+12dB) Ouput Mode 5 (G=+12dB) Ouput Mode 6, 7 (G=+12dB) Digital Gain Range - Rin & Lin no load Digital gain stepsize Stepsize G -22.5dB G < -22.5dB Phone In Gain, no load BTL gain from Phone In to SPKERout BTL gain from Phone In to Rout & Lout Phone In Input Impedance Rin & Lin Input Impedance (all gain setting) Enable Stepup Time - ENB Enable Hold Time - ENB Enable Low Time - ENB Data Setup Time- DATA Data Hold Time - DATA Clock Setup time - CLK Clock Logic High Time - CLK Clock Logic Low Time - CLK Clock Frequency - CLK Ratio1 Min. Typ. 8 4.5 0.1 5 Max. 11 6.5 Unit mA ISTANDBY Voo Vil Vih Po A 2 mV 0 1.4 800 80 1000 120 % 0.5 1 0.5 1 90 50 0.4 5 V V mW THD + N SNR PSRR dB dB 70 70 55 57 52 56 dB -34.5 1.5 -0.5 -1 6 0 20 50 +0.5 +1 dB +12 dB dB G Zin Zin tes teh tel tds tdh tcs tch tcl fclk 1) 15 37.5 20 20 30 20 20 20 50 50 DC 25 62.5 10 k k ns ns ns ns ns ns ns ns MHz Dynamic measurements [20 x log(rms(Vout)/rms(Vripple)]. Vripple is the superimposed sinus signal to Vcc @ F = 217Hz 7/28 TS4851 Electrical Characteristics Table 9. Electrical characteristics at VCC = +3V, GND = 0V, Tamb = 25C (unless otherwise specified) Symbol ICC Parameter Supply Current Output Mode 7, Vin = 0V,no load All other output modes, Vin = 0V,no load Standby Current Output Mode 0 Output Offset Voltage (differential) Vin = 0V "Logic low" input Voltage "Logic high" input Voltage Output Power SPKERout, RL = 8, THD = 1%, F = 1kHz Rout & Lout, RL = 32, THD = 0.5%, F = 1kHz Total Harmonic Distortion + Noise Rout & Lout, Po = 20mW, F = 1kHz, RL = 32 SPKERout, Po = 300mW, F = 1kHz, RL = 8 Rout & Lout, Po = 15mW, 20Hz < F < 20kHz, RL = 32 SPKERout, Po = 250mW, 20Hz < F < 20kHz, RL = 8 Signal To Noise Ratio (A-Weighted) Power Supply Rejection Ratio2 Vripple = 200mV Vpp, F = 217Hz, Input(s) Terminated 10 Ouput Mode 1 Ouput Mode 2 Ouput Mode 3 (G=+12dB) Ouput Mode 4 (G=+12dB) Ouput Mode 5 (G=+12dB) Ouput Mode 6, 7 (G=+12dB) Digital Gain Range - Rin & Lin no load Digital gain stepsize Stepsize error G -22.5dB G < -22.5dB Phone In Gain, no load BTL gain from Phone In to SPKERout BTL gain from Phone In to Rout & Lout Phone In Input Impedance 1 Rin & Lin Input Impedance (All Gain Setting) Enable Stepup Time - ENB Enable Hold Time - ENB Enable Low Time - ENB Data Setup Time- DATA Data Hold Time - DATA Clock Setup time - CLK Clock Logic High Time - CLK Clock Logic Low Time - CLK Clock Frequency - CLK 1 Min. Typ. 7.5 4.5 0.1 5 Max. 10 6.5 Unit mA ISTANDBY Voo Vil Vih Po A 2 mV 0 1.4 300 20 340 30 % 0.5 1 0.5 1 86 50 0.4 5 V V mW THD + N SNR PSRR1 dB dB 65 70 54 54 51 53 dB -34.5 1.5 +12 dB dB +0.5 +1 dB 6 0 20 50 G -0.5 -1 Zin Zin tes teh tel tds tdh tcs tch tcl fclk 1) 2) 15 37.5 20 20 30 20 20 20 50 50 DC 25 62.5 k k ns ns ns ns ns ns ns ns MHz 10 All PSRR data limits are guaranted by evaluation desgin test. Dynamic measurements [20 x log(rms(Vout)/rms(Vripple)]. Vripple is the superimposed sinus signal to Vcc @ F = 217Hz 8/28 Electrical Characteristics Table 10. Index of graphics Description THD + N vs. Output Power THD + N vs. Frequency Output Power vs. Power Supply Voltage PSRR vs. Frequency Frequency Response Signal to Noise Ratio vs. Power Supply Voltage Crosstalk vs. Frequency -3 dB Lower Cut Off Frequency vs. Input Capacitor Current Consumption vs. Power Supply Voltage Power Dissipation vs. Output Power Power Derating Curves -3 dB Lower Cut Off Frequency vs. Gain Setting TS4851 Figure Figures 3 to 12 Figures 13 to 22 Figures 23 to 30 Figures 31 to 40 Figures 41 to 44 Figures 45 to 48 Figures 49 to 50 Figures 51 to 52 Figure 53 Figures 54 to 57 Figure 58 Figure 59 Page page 10 to page 11 page 11 to page 13 page 13 to page 14 page 14 to page 16 page 16 page 17 page 18 page 18 page 18 page 18 to page 19 page 19 page 19 Note: In the graphs that follow, the abbreviations Spkout = Speaker Output, and HDout = Headphone Output are used. All measurements made with Cin = 220nF, Cb = Cs = 1F except in PSRR condition where Cs = 0. 9/28 TS4851 Figure 3: Spkout THD+N vs. output power (output modes 1, 7) 10 RL = 4 Output mode 1, 7 BW < 125 kHz Tamb = 25C 1 THD + N (%) Electrical Characteristics Figure 6: HDout THD+N vs. output power (output mode 2) 10 Vcc=5V F=20kHz Vcc=3V F=20kHz THD + N (%) 1 RL = 16 Output mode 2 BW < 125 kHz Tamb = 25C Vcc=5V F=20kHz Vcc=3V F=20kHz 0.1 Vcc=3V F=1kHz 0.1 Vcc=3V F=1kHz 0.01 1E-3 0.01 0.1 Output power (W) Vcc=5V F=1kHz 1 0.01 1E-3 0.01 Output power (W) 0.1 Vcc=5V F=1kHz Figure 4: Spkout THD+N vs. output power (output modes 1, 7) 10 RL = 8 Output mode 1, 7 BW < 125 kHz Tamb = 25C Vcc=5V F=20kHz Vcc=3V F=20kHz Figure 7: HDout THD+N vs. output power (output mode 2) 10 RL = 32 Output mode 2 BW < 125 kHz Tamb = 25C Vcc=5V F=20kHz Vcc=3V F=20kHz 1 THD + N (%) 1 THD + N (%) 0.1 0.1 Vcc=3V F=1kHz 0.01 1E-3 0.01 Vcc=3V F=1kHz 0.1 Vcc=5V F=1kHz 1 0.01 1E-3 0.01 Output power (W) Vcc=5V F=1kHz 0.1 Output power (W) Figure 5: Spkout THD+N vs. output power (output modes 1, 7) 10 RL = 16 Output mode 1, 7 BW < 125 kHz Tamb = 25C Vcc=5V F=20kHz Vcc=3V F=20kHz Figure 8: Spkout THD+N vs. output power (output mode 3, G=+12dB) 10 RL = 4 Out. mode 3; G = +12dB BW < 125 kHz Tamb = 25C Vcc=5V F=20kHz Vcc=3V F=20kHz 1 THD + N (%) THD + N (%) Vcc=5V F=1kHz 1 0.1 Vcc=3V F=1kHz 0.01 1E-3 0.01 0.1 0.1 1E-3 Vcc=3V F=1kHz 0.01 0.1 Vcc=5V F=1kHz 1 1 Output power (W) Output power (W) 10/28 Electrical Characteristics Figure 9: Spkout THD+N vs. output power (output mode 3, G=+12dB) 10 RL = 8 Out. mode 3; G = +12dB BW < 125 kHz Tamb = 25C Vcc=5V F=20kHz Vcc=3V F=20kHz THD + N (%) TS4851 Figure 12: HDout THD+N vs. output power (output mode 4, G=+12dB) 10 RL = 32 Output mode 4 G = +12dB BW < 125 kHz Tamb = 25C Vcc=5V F=20kHz Vcc=3V F=20kHz THD + N (%) 1 1 0.1 0.1 Vcc=3V F=1kHz 1E-3 0.01 Vcc=5V F=1kHz 0.1 1 0.01 1E-3 Vcc=3V F=1kHz Vcc=5V F=1kHz 0.01 Output power (W) 0.1 Output power (W) Figure 10: Spkout THD+N vs. output power (output mode 3, G=+12dB) 10 RL = 16 Output mode 3 G = +12dB BW < 125 kHz Tamb = 25C Vcc=5V F=20kHz Vcc=3V F=20kHz Figure 13: Spkout THD+N vs. frequency (output modes 1, 7) 10 RL = 4 Output mode 1, 7 BW < 125kHz Tamb = 25C 1 THD + N (%) 1 THD + N (%) Vcc=3V P=400mW Vcc=5V P=1.1W 0.1 Vcc=3V F=1kHz Vcc=5V F=1kHz 0.1 0.01 1E-3 0.01 0.1 1 0.01 100 1000 Frequency (Hz) 10000 Output power (W) Figure 11: HDout THD+N vs. output power (output mode 4, G=+12dB) 10 RL = 16 Output mode 4 G = +12dB BW < 125 kHz Tamb = 25C Vcc=5V F=20kHz Vcc=3V F=20kHz Figure 14: Spkout THD+N vs. frequency (output modes 1, 7) 10 RL = 8 Output mode 1, 7 BW < 125kHz Tamb = 25C 1 THD + N (%) 1 THD + N (%) Vcc=3V P=320mW Vcc=5V P=800mW 0.1 Vcc=3V F=1kHz Vcc=5V F=1kHz 0.01 1E-3 0.01 Output power (W) 0.1 0.1 0.01 100 1000 Frequency (Hz) 10000 11/28 TS4851 Figure 15: Spkout THD+N vs. frequency (output modes 1, 7) 10 RL = 16 Output mode 1, 7 BW < 125kHz Tamb = 25C 1 THD + N (%) Electrical Characteristics Figure 18: Spkout THD+N vs.frequency (output mode 3, G = +12 dB) 10 RL = 4 Output mode 3 G = +12dB BW < 125kHz Tamb = 25C THD + N (%) Vcc=3V P=150mW Vcc=5V P=550mW 1 Vcc=3V P=400mW Vcc=5V P=1.1W 0.1 0.1 0.01 100 1000 Frequency (Hz) 10000 100 1000 Frequency (Hz) 10000 Figure 16: HDout THD+N vs. frequency (output mode 2) 10 RL = 16 Output mode 2 BW < 125kHz Tamb = 25C 1 THD + N (%) Figure 19: Spkout THD+N vs. frequency (output mode 3, G = +12 dB) 10 RL = 8 Output mode 3 G = +12dB BW < 125kHz Tamb = 25C THD + N (%) Vcc=3V P=40mW 0.1 Vcc=5V P=220mW 1 Vcc=3V P=320mW Vcc=5V P=800mW 0.1 0.01 100 1000 Frequency (Hz) 10000 100 1000 Frequency (Hz) 10000 Figure 17: HDout THD+N vs. frequency (output mode 2) 10 RL = 32 Output mode 2 BW < 125kHz Tamb = 25C 1 THD + N (%) Figure 20: Spkout THD+N vs. frequency (output mode 3, G = +12 dB) 10 RL = 16 Output mode 3 G = +12dB BW < 125kHz 1 Tamb = 25C Vcc=3V P=180mW Vcc=3V P=20mW 0.1 Vcc=5V P=140mW THD + N (%) 0.1 Vcc=5V P=550mW 0.01 100 1000 Frequency (Hz) 10000 0.01 100 1000 Frequency (Hz) 10000 12/28 Electrical Characteristics Figure 21: HDout THD+N vs. frequency (output mode 4, G = +12 dB) 10 Output power at 10% THD + N (W) TS4851 Figure 24: Speaker output power vs. power supply voltage (output mode 1, 7) 2.4 F = 1kHz Output mode 1, 7 RL = 16 Output mode 4 G = +12dB BW < 125kHz 1 Tamb = 25C THD + N (%) 2.0 BW < 125kHz Tamb = 25C Vcc=3V P=40mW 1.6 1.2 4 8 16 0.1 Vcc=5V P=220mW 0.8 32 0.4 0.0 3.0 0.01 100 1000 Frequency (Hz) 10000 3.5 4.0 Vcc (V) 4.5 5.0 5.5 Figure 22: HDout THD+N vs. frequency (output mode 4, G = +12 dB) 10 Figure 25: Headphone output power vs. load resistor (output mode 2) 0.35 Output power at 1% THD + N (W) RL = 32 Output mode 4 G = +12dB BW < 125kHz 1 Tamb = 25C THD + N (%) 0.30 0.25 0.20 0.15 F = 1kHz Output mode 2 BW < 125kHz Tamb = 25C 16 Vcc=3V P=20mW 32 0.1 Vcc=5V P=140mW 64 0.10 0.05 0.00 3.0 0.01 100 1000 Frequency (Hz) 10000 3.5 4.0 Vcc (V) 4.5 5.0 5.5 Figure 23: Speaker output power vs. power supply voltage (output mode 1, 7) 2.0 Figure 26: Headphone output power vs. load resistor (output mode 2) 0.40 Output power at 10% THD + N (W) Output power at 1% THD + N (W) 1.6 F = 1kHz Output mode 1, 7 BW < 125kHz Tamb = 25C F = 1kHz 0.35 Output mode 2 BW < 125kHz 16 4 8 16 32 0.30 Tamb = 25C 0.25 0.20 0.15 0.10 0.05 0.00 3.0 3.5 4.0 Vcc (V) 4.5 5.0 5.5 64 32 1.2 0.8 0.4 0.0 3.0 3.5 4.0 Vcc (V) 4.5 5.0 5.5 13/28 TS4851 Figure 27: Speaker output power vs. power supply voltage (output mode 3) 2.0 Electrical Characteristics Figure 30: Headphone output power vs. load resistance (output mode 2) 0.40 F = 1kHz Output power at 10% THD + N (W) Output power at 1% THD + N (W) F = 1kHz Output mode 3 1.6 BW < 125kHz Tamb = 25C 0.35 Output mode 4 BW < 125kHz 0.30 Tamb = 25C 16 4 8 16 32 32 0.25 0.20 0.15 0.10 0.05 0.00 3.0 3.5 4.0 Vcc (V) 4.5 5.0 5.5 64 1.2 0.8 0.4 0.0 3.0 3.5 4.0 Vcc (V) 4.5 5.0 5.5 Figure 28: Speaker output power vs. power supply voltage (output mode 3) 2.4 Output power at 10% THD + N (W) Figure 31: Spkout PSRR vs. frequency (output modes 1, 7, input grounded) 0 Output mode 1, 7 -10 RL = 8 Vripple = 0.2Vpp -20 Tamb = 25C -30 2.0 1.6 F = 1kHz Output mode 3 BW < 125kHz Tamb = 25C 4 8 PSRR (dB) 1.2 16 0.8 32 0.4 0.0 3.0 -40 -50 -60 -70 -80 Vcc=5V Vcc=3V 3.5 4.0 Vcc (V) 4.5 5.0 5.5 -90 100 1000 10000 Frequency (Hz) 100000 Figure 29: Headphone output power vs. load resistor (output mode 4) 0.35 Figure 32: HDout PSRR vs. frequency (output mode 2, input grounded) 0 Output power at 1% THD + N (W) 0.30 0.25 0.20 0.15 0.10 0.05 F = 1kHz Output mode 4 BW < 125kHz Tamb = 25C 16 -10 -20 32 Output mode 2 RL = 32 Vripple = 0.2Vpp Tamb = 25C PSRR (dB) -30 -40 -50 -60 Vcc = 3V & 5V 64 -70 0.00 3.0 3.5 4.0 Vcc (V) 4.5 5.0 5.5 -80 100 1000 10000 Frequency (Hz) 100000 14/28 Electrical Characteristics Figure 33: Spkout PSRR vs. frequency (output mode 3, inputs grounded) 0 -10 -20 -30 PSRR (dB) TS4851 Figure 36: HDout PSRR vs. frequency (output mode 4, inputs grounded) 0 Output mode 4 -10 Vcc = +3V RL = 32 -20 Vripple=0.2Vpp Tamb = 25C G=+12dB G=+6dB PSRR (Hz) G=+6dB G=+12dB G=+9dB -40 -50 -60 -70 -80 -30 -40 G=-12dB -50 G=+9dB Output mode 3 Vcc = +5V RL = 8 Vripple = 0.2Vpp Tamb = 25 100000 G=-12dB G=-34.5dB G=0dB G=0dB -60 G=-34.5dB -70 100 1000 10000 Frequency (Hz) 100000 -90 100 1000 10000 Frequency (Hz) Figure 34: Spkout PSRR vs. frequency (output mode 3, inputs grounded) 0 -10 -20 Output mode 3 Vcc = +3V RL = 8 Vripple=0.2Vpp Tamb = 25C Figure 37: Spkout PSRR vs. frequency (output mode 5, inputs grounded) 0 -10 Output mode 5 Vcc = +5V RL = 8 Vripple=0.2Vpp Tamb = 25C G=+6dB G=+12dB G=+9dB G=-12dB G=0dB G=-34.5dB G=+12dB -20 PSRR (dB) -30 -40 PSRR (Hz) G=-34.5dB G=-12dB G=+6dB -30 -40 -50 -60 -70 G=+9dB -50 -60 -70 -80 100 G=0dB 1000 10000 Frequency (Hz) 100000 100 1000 10000 Frequency (Hz) 100000 Figure 35: HDout PSRR vs. frequency (output mode 4, inputs grounded) 0 -10 -20 Output mode 4 Vcc = +5V RL = 32 Vripple=0.2Vpp Tamb = 25C Figure 38: Spkout PSRR vs. frequency (output mode 5, inputs grounded) 0 -10 Output mode 5 Vcc = +3V RL = 8 Vripple=0.2Vpp Tamb = 25C G=+6dB G=+12dB G=+9dB G=-12dB G=0dB G=-34.5dB G=+12dB G=+6dB -20 PSRR (dB) -30 -40 -50 -60 -70 -80 PSRR (Hz) G=0dB G=-34.5dB 100000 G=+9dB G=-12dB -30 -40 -50 -60 -70 100 1000 10000 Frequency (Hz) 100 1000 10000 Frequency (Hz) 100000 15/28 TS4851 Figure 39: HDout PSRR vs. frequency (output modes 6, 7, inputs grounded) 0 Output mode 6, 7 -10 Vcc = +5V RL = 32 -20 Vripple=0.2Vpp Tamb = 25C -30 -40 -50 G=0dB -60 G=-34.5dB -70 100 1000 10000 100000 G=+6dB Electrical Characteristics Figure 42: HDout frequency response (output mode 2) 0 -2 G=+12dB G=+9dB Output level (dB) Vcc=3V Vcc=5V PSRR (Hz) G=-12dB -4 Output mode 2 RL = 32 Cin = 220 nF BW < 125 kHz Tamb = 25C -6 20 100 1000 Frequency (Hz) 10000 Frequency (Hz) Figure 40: HDout PSRR vs. freq., (output modes 6, 7, inputs grounded) 0 -10 -20 Output mode 6, 7 Vcc = +3V RL = 32 Vripple=0.2Vpp Tamb = 25C G=+6dB Figure 43: Spkout frequency response (output mode 3) 12 10 8 6 4 2 Output mode 3 RL = 8 G = +12dB Cin = 220 nF BW < 125 kHz Tamb = 25C Vcc=5V Vcc=3V -30 -40 -50 G=+9dB G=-12dB G=0dB -60 G=-34.5dB -70 100 1000 10000 Frequency (Hz) 100000 Output level (dB) G=+12dB PSRR (Hz) 0 20 100 1000 Frequency (Hz) 10000 Figure 41: Spkout frequency response (output mode 1, 7) 6 Figure 44: HDout frequency response (output mode 4) 12 10 4 Vcc=3V Vcc=5V Vcc=5V Vcc=3V Output level (dB) Output level (dB) 8 6 4 2 0 20 Output mode 4 RL = 32 G = +12dB Cin = 220 nF BW < 125 kHz Tamb = 25C 2 Output mode 1, 7 RL = 8 Cin = 220 nF BW < 125 kHz Tamb = 25C 0 20 100 1000 Frequency (Hz) 10000 100 1000 Frequency (Hz) 10000 16/28 Electrical Characteristics Figure 45: Spkout SNR vs. power supply voltage, unweighted filter, BW = 20 Hz to 20 kHz 100 98 96 94 92 SNR (dB) 90 88 86 84 82 80 78 76 1 2 3 4 Output mode 5 6 7 G=+12dB TS4851 Figure 47: HDout SNR vs. power supply voltage, unweighted filter, BW = 20 Hz to 20 kHz 100 Vcc=3V Vcc=5V RL = 8 Unweighted filter (20Hz to 20kHz) THD + N < 0.7% Tamb = 25C SNR (dB) 98 96 94 92 90 88 86 84 82 80 78 76 1 2 3 Vcc=3V Vcc=5V RL = 32 Unweighted filter (20Hz to 20kHz) THD + N < 0.7% Tamb = 25C G=+12dB 4 Output mode 5 6 7 Figure 46: Spkout SNR vs. power supply voltage, weighted filter A, BW = 20 Hz to 20 kHz 104 102 100 98 Figure 48: HDout SNR vs. power supply voltage, weighted filter A, BW = 20 Hz to 20 kHz 104 102 100 98 SNR (dB) SNR (dB) Vcc=3V Vcc=5V RL = 8 Weighted filter type A THD + N < 0.7% Tamb = 25C Vcc=3V Vcc=5V RL = 32 Weighted filter type A THD + N < 0.7% Tamb = 25C 96 94 92 90 88 86 1 2 3 4 Output mode 5 6 7 G=+12dB 96 94 92 90 88 86 1 2 3 4 Output mode 5 6 7 G=+12dB 17/28 TS4851 Figure 49: Crosstalk vs. frequency (output mode 4) 0 Lower -3dB Cut Off Frequency (Hz) Electrical Characteristics Figure 52: -3 dB lower cut off frequency vs. input capacitance Crosstalk Level (dB) Output mode 4 Vcc = 5V -20 RL = 32 G = +12dB Pout = 100mW BW < 125kHz -40 Tamb = 25C Lout -> Rout Rout -> Lout Rin & Lin Inputs All gain setting Tamb=25C 10 Typical Input Impedance Minimum Input Impedance Maximum Input Impedance -60 -80 20 100 1000 Frequency (Hz) 10000 1 0.1 Input Capacitor (F) 1 Figure 50: Crosstalk vs. frequency (output mode 4) 0 Output mode 4 Vcc = 3V -20 RL = 32 G = +12dB Pout = 20mW BW < 125kHz -40 Tamb = 25C Lout -> Rout Rout -> Lout Figure 53: Current consumption vs. power supply voltage 10 No loads 9 Tamb = 25C 8 7 6 Icc (mA) Mode 7 Crosstalk Level (dB) Mode 2, 4, 6 5 4 3 2 Mode 1, 3, 5 Reset state -60 -80 100 1000 Frequency (Hz) 10000 1 0 0 1 2 Vcc (V) 3 4 5 Figure 51: -3 dB lower cut off frequency vs. input capacitor 100 Lower -3dB Cut Off Frequency (Hz) Figure 54: Power dissipation vs. output power (speaker output) 1.4 Phone In Input Tamb=25C Power Dissipation (W) Vcc=5V 1.2 F=1kHz THD+N<1% 1.0 0.8 0.6 0.4 0.2 RL=16 0.0 0.0 RL=4 Typical Input Impedance Minimum Input Impedance 10 Maximum Input Impedance 1 Input Capacitor ( F) RL=8 0.1 0.2 0.4 0.6 0.8 1.0 1.2 Output Power (W) 1.4 1.6 18/28 Electrical Characteristics Figure 55: Power dissipation vs. output power (speaker output) 0.5 Vcc=3V F=1kHz 0.4 THD+N<1% TS4851 Figure 58: Power derating curves 100 Lower -3dB Cut Off Frequency (Hz) RL=4 Rin & Lin Inputs Input Impedance is Nominal Tamb=25C Cin=100nF Power Dissipation (W) Cin=220nF 0.3 10 0.2 RL=8 0.1 RL=16 0.0 0.0 0.1 0.2 0.3 0.4 0.5 Cin=1F Cin=470nF 1 -34.5 -20 Gain Setting (dB) 0 12 Output Power (W) Figure 56: Power dissipation vs. output power (headphone output, one channel) 0.4 Vcc=5V F=1kHz THD+N<1% 0.3 Figure 59: -3 dB lower cut off frequency vs. gain setting (output modes 3, 4, 5, 6, 7) Flip-Chip Package Power Dissipation (W) 1.4 1.2 1.0 0.8 0.6 0.4 No Heat sink 0.2 0.0 Heat sink surface = 125mm 2 Power Dissipation (W) 0.2 RL=16 0.1 RL=32 0.0 0.00 0.05 0.10 0.15 0.20 Output Power (W) 0.25 0 25 50 75 100 125 150 Ambiant Temperature ( C) Figure 57: Power dissipation vs. output power (headphone output one channel) 120 Vcc=3V F=1kHz 100 THD+N<1% 80 60 RL=16 Table 11. Output noise (all inputs grounded) Outp ut Mode 1 2 3 Unweighted Filter from 3V to 5V 23Vrms 20Vrms 70Vrms 53Vrms 79Vrms 60Vrms Weighted Filter (A) from 3V to 5V 20Vrms 17Vrms 60Vrms 45Vrms 67Vrms 51Vrms Power Dissipation (mW) 40 RL=32 20 0 4 5 0 10 20 30 40 50 Output Power (mW) 60 70 6 19/28 TS4851 Application Information 5 Application Information 5.1 BTL configuration principles The TS4851 integrates 3 monolithic power amplifier having BTL output. BTL (Bridge Tied Load) means that each end of the load is connected to two single-ended output amplifiers. Thus, we have: Single ended output 1 = Vout1 = Vout (V) Single ended output 2 = Vout2 = -Vout (V) and Vout1 - Vout2 = 2Vout (V) The output power is: Pout = ( 2 Vout RMS ) 2 (W ) RL For the same power supply voltage, the output power in BTL configuration is four times higher than the output power in single ended configuration. 5.2 Power dissipation and efficiency Hypotheses: l Voltage and current in the load are sinusoidal (Vout and Iout). l Supply voltage is a pure DC source (Vcc). Regarding the load we have: VOUT = V PEAK sin t (V) and VOUT IOUT = ---------------- (A) RL and VPEAK 2 POUT = ---------------------- (W) 2RL Then, the average current delivered by the supply voltage is: ICC AVG VPEA K = 2 ------------------- (A) RL The power delivered by the supply voltage is: Psupply = Vcc IccAVG (W) Then, the power dissipated by each amplifier is Pdiss = Psupply - Pout (W) Pdiss = 2 2 VCC RL POUT - POUT (W ) 20/28 Application Information and the maximum value is obtained when: Pdiss --------------------- = 0 POUT and its value is: TS4851 Pdiss max = 2 Vcc 2 2RL (W) Note: This maximum value is depends only on power supply voltage and load values. The efficiency is the ratio between the output power and the power supply: POUT VPEAK = ----------------------- = ---------------------Psup ply 4VCC The maximum theoretical value is reached when Vpeak = Vcc, so: ---- = 78.5% 4 The TS4851 has three independent power amplifiers. Each amplifier produces heat due to its power dissipation. Therefore, the maximum die temperature is the sum of each amplifier's maximum power dissipation. It is calculated as follows: l Pdiss speaker = Power dissipation due to the speaker power amplifier. l Pdiss head = Power dissipation due to the Headphone power amplifier l Total Pdiss = P diss speaker + Pdiss head1 + Pdiss head2 (W) In most cases, Pdiss head1 = Pdiss head2, giving: Total Pdiss = P diss speaker + 2Pdiss head (W) TotalP diss = POUT HEAD 2 2 VCC POUT SPEAKER +2 R L HEAD R L SPEAKER - POUT SPEAKER + 2 POUT HEAD (W ) [ ] The following graph (Figure 60) shows an example of the previous formula, with Vcc set to +5V, Rload speaker set to 8 and Rload headphone set to 16. Figure 60: Example of total power dissipation vs. speaker and headphone output power 21/28 TS4851 5.3 Low frequency response Application Information In low frequency region, the effect of Cin starts. Cin with Zin forms a high pass filter with a -3dB cut off frequency. FCL = 1 (Hz ) 2 Zin Cin Zin is the input impedance of the corresponding input: * * 20k for Phone In IHF input 50k for the 3 other inputs Note: For all inputs, the impedance value remains constant for all gain settings. This means that the lower cut-off frequency doesn't change with gain setting. Note also that 20k and 50k are typical values and there are tolerances around these values (see Electrical Characteristics on page 7). In Figures 39 to 41, you could easily establish the Cin value for a -3dB cut-off frequency required. 5.4 Decoupling of the circuit Two capacitors are needed to bypass properly the TS4851, a power supply bypass capacitor Cs and a bias voltage bypass capacitor Cb. Cs has especially an influence on the THD+N in high frequency (above 7kHz) and indirectly on the power supply disturbances. With 1F, you could expect similar THD+N performances like shown in the datasheet. If Cs is lower than 1F, THD+N increases in high frequency and disturbances on the power supply rail are less filtered. To the contrary, if Cs is higher than 1F, those disturbances on the power supply rail are more filtered. Cb has an influence on THD+N in lower frequency, but its value is critical on the final result of PSRR with input grounded in lower frequency: * * If Cb is lower than 1F, THD+N increases at lower frequencies and the PSRR worsens upwards. If Cb is higher than 1F, the benefit on THD+N and PSRR in the lower frequency range is small. 5.5 Startup time When the TS4851 is controlled to switch from the full standby mode (output mode 0) to another output mode, a delay is necessary to stabilize the DC bias. This delay depends on the Cb value and can be calculated by the following formulas. Typical startup time = 0.0175 x Cb (s) Max. startup time = 0.025 x Cb (s) (Cb is in F in these formulas) These formulas assume that the Cb voltage is equal to 0V. If the Cb voltage is not equal to 0V, the startup time will be always lower. The startup time is the delay between the negative edge of Enable input (see Description of SPI operation on page 3) and the power ON of the output amplifiers. Note: When the TS4851 is set in full standby mode, Cb is discharged through an internal switch.. The time to reach 0V of Cb voltage is about ms. 22/28 Application Information 5.6 Pop and Click performance TS4851 The TS4851 has internal Pop and Click reduction circuitry. The performance of this circuitry is closely linked with the value of the input capacitor Cin and the bias voltage bypass capacitor Cb. The value of Cin is due to the lower cut-off frequency value requested. The value of Cb is due to THD+N and PSRR requested always in lower frequency. The TS4851 is optimized to have a low pop and click in the typical schematic configuration (see page 2). Note: The value of Cs is not an important consideration as regards pop and click. 5.7 Notes on PSRR measurement What is the PSRR? The PSRR is the Power Supply Rejection Ratio. The PSRR of a device, is the ratio between a power supply disturbance and the result on the output. We can say that the PSRR is the ability of a device to minimize the impact of power supply disturbances to the output. How we measure the PSRR? The PSSR was measured according to the schematic shown in Figure 61. Figure 61: PSRR measurement schematic Principles of operation * * * The DC voltage supply (Vcc) is fixed. The AC sinusoidal ripple voltage (Vripple) is fixed. No bypass capacitor Cs is used. RMS PSRR = 20 x Log RMS ) The PSRR value for each frequency is: ( Output ) ( Vripple ( dB ) RMS is a rms selective measurement. 5.8 Power-On Reset When Power is applied to Vdd, an internal Power On Reset holds the TS4851 in a reset state until the Supply Voltage reached its nominal value. The Power On reset has a typical threshold at 1.8V. 23/28 TS4851 Package Information 6 Package Information Flip-chip - 18 bumps: TS4851JT Pin out (top view) 7 6 5 4 3 2 1 R OUTR OUT + R IN L IN PHONE IN SPKR OUT + GND L OUT + L OUT - VCC DATA NC VCC ENB SPKR OUT - BYPASS GND CLK A B C D E Note: The solder bumps are on the underside. Marking (top view): The following markings are present on the topside of the flip-chip: l The ST logo. l The part number: A51. l A 3-digit date code: YWW. l A dot marking the location of Pin1A. E Symbol for Lead-Free A51 YWW 24/28 Package Information TS4851 Footprint recommendation TS4851 =250m 866m 433m 75m Min 100m max. Track =400m 150m min. Non Solder mask opening 250m Pad in Cu 18m thickness with Flash NiAu (6m, 0.15m) Package mechanical data Symmetry axis 2440um Die size: 2170m x 2440m 30m Die height (including bumps): 600m 30m 2170um Symmetry axis Bumps diameter: 315m 50m Bumps height: 250m 40m Pitch: 500m 10m 750um 335um 500um 866um 354um 866um 600um 25/28 TS4851 Daisy Chain Samples 7 Daisy Chain Samples A daisy chain sample is a "dummy" silicon chip that can be used to test your flip-chip soldering process and connection continuity. The daisy chain sample features paired connections between bumps, as shown in the schematic below. On your PCB layout, you should design the bump connections such that they are complementary to the above schema (meaning that different pairs of bumps are connected on the PCB side). In this way, by simply connecting an ohmmeter between pin 1A and pin 5A, you can test the continuity of your soldering process. The order code for daisy chain samples is given below. Figure 62: Daisy chain sample mechanical data 2.44 mm 7 6 5 4 3 2 1 R OUTR OUT + R IN L IN PHONE IN SPKR OUT + GND L OUT L OUT + VCC DATA 2.17 mm NC VCC ENB SPKR OUT - BYPASS GND CLK A B C D E Order code for daisy chain samples Package Part Number TSDC02IJT Temperature Range J -40, +85C Marking * DC2 26/28 Tape & Reel Specification TS4851 8 Tape & Reel Specification Figure 63: Top view of tape and reel 1 1 A A User direction of feed Device orientation The devices are oriented in the carrier pocket with pin number 1A adjacent to the sprocket holes. 27/28 TS4851 Revision History 9 Revision History Date 01 July 2002 01 April 2003 01 April 2004 01 Jan. 2005 01 March 2005 Revision 1 2 3 4 5 First Release Curves inserted in the document Curves updated in the document Leadfree codification added in the document Realignment of curve data in the document Description of Changes Informatio n fu rnish ed is believe d to b e accurate a nd rel iab le. H owe ver, STMicro ele ctro nics assu mes no resp onsibility for th e con se que nces of u se o f su ch i nformatio n nor for any infringement of patents or other righ ts of third pa rti es w hich may re sult from its use . No lice nse is gra nted by imp lica ti on or o th erwise und er any pa te nt or paten t rig hts o f STMicro ele ctro nics. Speci fication s me ntion ed in th is pub lica ti on are su bje ct to chan ge witho ut n otice. Th is pub lica ti on supersed es and re places a ll in fo rmation p revio usly sup pli ed. STMi croelectronics produ cts are no t au th orize d fo r u se as critical co mpon ents in life su ppo rt devices or systems witho ut e xpress written a ppro val of STMicroelectroni cs. The ST log o is a registe red trade mark of STMicroe lectronics Al l other na mes are the pro perty of the ir respe ctive own ers (c) 200 5 STMicroel ectronics - All rights reserve d STMi croelectronics gro up o f compa nie s Au stra lia - Belgiu m - Brazil - C ana da - Chi na - Czech R epu blic - Finl and - France - Germany - Ho ng Kon g - Ind ia - Isra el - Italy- Jap an Mal aysia - Mal ta - Moro cco - Si nga pore - Spa in - Swed en - Switzerl and - United Kingdo m - Un ited States of America www.s t.c om 28/28 |
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