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| (R) DEVICE SPECIFICATION 2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP 2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP S2091 S2091 FEATURES * Supports 2.5 Gbps Data Rates * Fully differential for minimum jitter accumulation * TTL Bypass Select * High speed 50 source terminated outputs * 0.4W Typical power dissipation * 3.3V power supply * 20 Pin TSSOP functional and data bypasses to the next available disk drive. Normal mode is enabled with a High on the SEL pin and Bypass mode is enable by a Low on the SEL pin. Direct Attach Fibre Channel Disk Drives have an "LRC Interlock" signal defined to control the SEL function. A system diagram showing the S2091 in a single loop of a disk array is illustrated in Figure 2. The S2091 can be cascaded with the S3040 (Data retimer) for arrays of disk drives greater than 4. Table 1 is a truth table detailing the data flow through the S2091. Figure 3 shows a timing diagram of the data relationship in the S2091. The primary AC parameter of importance is the deterministic jitter or data eye degradation inserted by the port bypass circuit. The design for the S2091 minimized jitter accumulation by using high bandwidth, low skew fully differential circuits. This provides for symmetric rise and fall delays as well as noise rejection. GENERAL DESCRIPTION The S2091 is a Port Bypass Circuit (PBC). A single channel Fibre Channel PBC offers designers maximum flexibility in FC-AL disk architectures. The S2091 is designed to minimize jitter accumulation by providing a high bandwidth fully differential signal path. Port Bypass circuits are used to provide resiliency in Fibre Channel Arbitrated Loop (FC-AL) architectures. PBC's are used within FC-AL disk arrays to allow for resiliency and hot swapping of FC-AL drives. A Port-by-Pass Circuit is a 2:1 Multiplexer with two modes of operations: Normal and Bypass. In Normal mode, the disk drive is connected to the loop. In Bypass mode, the disk drive is either absent or non- Table 1. Truth Table SEL1 0 1 OUT IN DDI DDO IN IN Figure 1. S2091 Block Diagram DDO P/N DDI P/N SEL 1 IN P/N 0 PBC OUT P/N 1 S2091 2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP Figure 2. Functional Block Diagram Dual SC or DB-9 Optics or Copper normal FC-AL Disk Drive LRC Interlock 0 1 TX E_STORE RX S2091 Disk Storage bypass 0 1 Pulldown for Bypass in Absence of Disk Drive TX S2091 normal FC-AL Disk Drive LRC Interlock 0 1 TX E_STORE RX S2091 Disk Storage 2 2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP Figure 3. Timing Waveforms S2091 IN P/N DI P/N OUT P/N DO P/N T1, 2, 3 Figure 4. Differential Voltage Single-ended swing VP-P = 2 x single-ended swing 3 S2091 2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP Table 2. Pin Assignment and Descriptions Pin Name INP INN DDIP DDIN SEL Level Diff. LVPECL Diff. LVPECL LVTTL I/O I Pin# 7, 6 Description Differential inputs from the downstream PBC port. I 4, 3 Serial input from the local disk drive. I 11 A Low selects the "BYPASS" mode causing the output of the previous port to propagate to the next port or OUT. When High, this signal selects "NORMAL" mode which routes the previous port to the local output, DDO and routes the local input, DDI to the next port or OUT. Serial output driving the local disk drive. D DOP DDO N OUTP OUTN VCC Diff. CML Diff. CML O 19, 18 O 15, 14 Serial output driving the upstream PBC port. 1, 2, 10, Power Supply. 3.3V nominal. 12, 17, 20 5, 8, 9, 13, 16 Ground. Ground pins are phyisically attached to the die mounting surface, and are an important part of the thermal path. For best thermal performance, all ground pins should be connected to a ground plane, using multiple vias if possible. GND Figure 5. S2091 Pinout Package VCC VCC DDIN DDIP GND INN INP GND GND VCC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC DDOP DDON VCC GND OUTP OUTN GND VCC SEL 4 2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP Figure 6. 20 TSSOP Package S2091 Thermal Management Device S2091A ja (Still Air) 77 C/W jc 25 C/W 5 S2091 2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP Table 3. AC Characteristics (Over recommended operating conditions.) Parameter T R1 TF1 TR2 TF2 TR3 TF3 T1 T2 T3 Description Serial Data rise and fall time (IN to OUT) Serial Data rise and fall time (IN to DDO) Serial Data rise and fall time (DDI to OUT) Flow through propagation delay IN to OUT Flow through propagation delay IN to DDO Flow through propagation delay DDI to OUT Typ 105 Max 135 Units ps Conditions 20% to 80% tested on a sample basis. (100 line-to-line.) 20% to 80% tested on a sample basis. (100 line-to-line.) 20% to 80% tested on a sample basis. (100 line-to-line.) Delay with all circuits bypassed. 50 Ohm load. Delay with PBC in Normal or Bypass mode. 50 Ohm load. Delay with PBC in Normal mode. 50 Ohm load. RMS output jitter accumulated with valid 8B/10B code from IN to OUT PBC in bypass mode. Tested on a sample basis. Deterministic output jitter accumulated with valid 8B/10B code from IN to OUT, both PBC stages bypassed. Determined by simulation. Actual value not verified due to bandwidth limitation of test equipment. 105 135 ps 105 150 ps 1.15 1.15 1.15 1.4 1.4 1.4 ns ns ns TjitterRMS Random jitter accumulation (RMS) 2.2 4 ps TjitterDJ Deterministic jitter accumulation (p-p) 6 7 ps 6 2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP Table 4. DC Characteristics (Over recommended operating conditions.) Parameter VIH(ITL) VIL(ITL) IIH(ITL) IIL(ITL) VCC ICC PD VIN(DF) VOUTN(L_SO) VOUTN(OUT) 1. See Figure 4. S2091 Description Input HIGH voltage (SEL-TTL) Input LOW voltage (SEL-TTL) Input HIGH current (SEL-TTL) Input LOW current (SEL-TTL) Supply Voltage Supply Current Power Dissipation Receiver differential peak-to-peak input sensitivity, INP/N & DDIP/N DDOP/N output differential peak-topeak voltage swing OUTP/N output differential peak-topeak voltage swing Min 2.0 0 Typ Max VCC 0.8 50 Units V V A A V mA W mVp-p1 mVp-p1 mVp-p1 Conditions VIN = 2.4V VIN = 0.5V VCC = 3.30V 5% Outputs open, VCC = VCC max Outputs open, VCC = VCC max AC Coupled. Internally DC biased VCC - 0.65V 100 line-to-line 100 line-to-line -500 3.14 180 0.4 300 1000 1000 -50 3.47 230 .8 2000 1460 1460 Table 5. Absolute Maximum Ratings1 Parameter Power Supply Voltage (VCC) PECL DC Input Voltage (VINP) TTL DC Input Voltage (VINP) CML Output Current (IOUT), (DC output High) Case Temperature Under Bias (TC) Storage Temperature (TSTG) Static Discharge Voltage -55 -65 Min 0.5 -0.5 -0.5 Typ Max +4 VCC+0.5 VCC+0.5 90 125 150 1000 Units V V V mA C C V 1. CAUTION: Stresses listed under "Absolute Maximum Ratings" may be applied one at a time to devices without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability. Table 6. Recommended Operating Conditions1 Parameter Power Supply Voltage (VCC) Ambient Operating Temperature Range (T) Min +3.14 -40 Typ Max +3.47 +85 Units V C 1. AMCC guarantees the functional and parametric operation of the part under "Recommended Operating Conditions" (except where specifically noted in the AC and DC parametric tables). 7 S2091 2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP Input Structures Two input structures exist in this part; TTL and high speed, differential inputs. The LVTTL inputs will interface with any LVTTL outputs. The high speed, differential inputs can be AC coupled per the FC-PH specification. Therefore, the high speed, differential input buffers are biased at Vcc -0.65V. Refer to Figure 7 for high speed differential input termination. Figure 7. Input Termination Biased at Vcc -0.65V S2091 100 Figure 8. Output VCC 50 50 Backplane S2091 GND 8 2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP S2091 Ordering Information GRADE PART NO. PACKAGE S- Commercial 2091 A - 20 TSSOP X Grade XXXX X Part No. Package IS O 90 0 RT IFI Applied Micro Circuits Corporation * 6290 Sequence Dr., San Diego, CA 92121 Phone: (619) 450-9333 * (800) 755-2622 * Fax: (619) 450-9885 http://www.amcc.com AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright (R) 1998 Applied Micro Circuits Corporation September 24, 1998 E D 1 CE 9 |
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