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VL-FS-MGLS12032C-01 REV. A (MGLS12032C-LED04) NOV/2002
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DOCUMENT REVISION HISTORY 1: DOCUMENT REVISION FROM TO A DATE DESCRIPTION CHANGED BY CHECKED BY TOM LEE
2002.11.28
First Release PHILIP (Based on Test specification: CHENG VL-TS-MGLS12032C-01, REV. A, 2001.11.13).
VL-FS-MGLS12032C-01 REV. A (MGLS12032C-LED04) NOV/2002
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CONTENTS
Page No. 1. 2. 3. 4. 4.1 4.2 5. 5.1 5.2 5.3 GENERAL DESCRIPTION MECHANICAL SPECIFICATIONS INTERFACE SIGNALS ABSOLUTE MAXIMUM RATINGS ELECTRICAL MAXIMUM RATINGS (Ta=25C) ENVIRONMENTAL CONDITION ELECTRICAL SPECIFICATIONS TYPICAL ELECTRICAL CHARACTERISTICS TIMING SPECIFICATIONS TIMING DIAGRAM OF VDD AGAINST V0 4 4 6 7 7 7 8 8 9 10
VL-FS-MGLS12032C-01 REV. A (MGLS12032C-LED04) NOV/2002
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VARITRONIX LIMITED
Specification of LCD Module Type Item No.: MGLS12032C-01
1. General Description * * * * * 120 x 32 dots STN Positive Yellow Transflective Dot Matrix LCD Graphic Module. Viewing Angle: 6 O'clock direction. Driving scheme: 1/32 multiplexed drive, 1/6.7 bias. `Epson' SED1520 D0A (Die form) dot matrix LCD drivers or equivalent. Yellow-green LED04 backlight.
2.
Mechanical Specifications The mechanical detail is shown in Fig. 1 and summarized in Table 1 below. Table 1
Parameter Outline dimensions Effective viewing area Display format Dot size Dot spacing Dot pitch for characters Weight:
Specifications 84.0(W) x 44.0(H) x 14.0(D) MAX. 61.0(W) x 15.8(H) 120(H) x 32 (V) 0.43(W) x 0.39(H) 0.04(W) x 0.04(H) 0.47(W) x 0.43(H) TBD
Unit mm mm dots mm mm mm grams
VL-FS-MGLS12032C-01 REV. A (MGLS12032C-LED04) NOV/2002
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Figure 1: Specification Drawing
VL-FS-MGLS12032C-01 REV. A (MGLS12032C-LED04) NOV/2002
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3. Interface signals Table 2 Pin No. 1 2 3 4 Symbol VSS VDD V0 A0 Description Ground(0V) Power supply for logic (+5V) Power supply for LCD driver Data/Command Select Input 'High': Display data on DB0-DB7. 'Low' : Display control data on DB0-DB7. Chip interface with 68 family MPU: Read/Write control signal input pin. R/W = "High": Read control signals. R/W = "Low": Write control signals. For first LCD driver SED1520: Chip interfaced with 68 family MPU: Input. Active high. Enable clock signal input for the 68 family MPU. For second LCD driver SED1520: Chip interfaced with 68 family MPU: Input. Active high. Enable clock signal input for the 68 family MPU. No connection. Data input/output (LSB) Data input/output Data input/output Data input/output Data input/output Data input/output Data input/output Data input/output (MSB) Anode of LED backlight. Cathode of LED backlight.
5
R/W
6
E1
7
E2
8 9 10 11 12 13 14 15 16 A K
NC DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 LED+ LED-
VL-FS-MGLS12032C-01 REV. A (MGLS12032C-LED04) NOV/2002
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4. 4.1
Absolute Maximum Ratings Electrical Maximum Ratings(Ta = 25 C) Table 3
Parameter Symbol Min. Max. Unit Power Supply voltage (Logic) VDD - VSS -0.3 +8.0 V Power Supply voltage VLCD -0.3 +16.5 V (LCD drive) =VDD - V0 Input voltage Vin -0.3 VDD +0.3 V Note: The modules may be destroyed if they are used beyond the absolute maximum ratings. All voltage values are referenced to VSS = 0V.
4.2
Environmental Condition Table 4 Operating Storage Temperature Temperature (Topr) (Tstg) Min. Max. Min. Max. o -10 C 0C +50C +60C 95% max. RH for Ta 40C < 95% RH for Ta > 40C Frequency: 10 55 Hz Amplitude: 0.75 mm Duration: 20 cycles in each direction. Pulse duration : 11 ms Peak acceleration: 981 m/s2 = 100g Number of shocks : 3 shocks in 3 mutually perpendicular axes.
Item
Remark
Ambient Temperature Humidity Vibration (IEC 68-2-6) cells must be mounted on a suitable connector Shock (IEC 68-2-27) Half-sine pulse shape
Dry no condensation 3 directions
3 directions
VL-FS-MGLS12032C-01 REV. A (MGLS12032C-LED04) NOV/2002
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5. Electrical Specifications 5.1 Typical Electrical Characteristics At Ta = 25 C, VDD = 5V5%, VSS=0V. Table 5 Parameter Supply voltage (Logic) Supply voltage (LCD) Input signal voltage 1 for E,DB0-DB7,R/W,A0 Supply current (Logic & LCD) Supply current (LCD) Supply voltage of yellow-green LED04 backlight Symbol VDD -VSS VLCD =VDD -V0 VIH1 VIL1 IDD I0 VLED Conditions VDD = 5V, Note 1. "H" level " L" level All mode All mode, Note 1 Forward current =90mA Number of LED dies =18. Note (1) : There is tolerance in optimum LCD driving voltage during production and it will be within the specified range. Min. 4.75 8.8 2.0 0 3.9 Typ. 5.0 9.3 1.5 1.4 4.1 Max. 5.25 9.8 VDD 0.8 2.3 2.1 4.3 Unit V V V V mA mA V
VL-FS-MGLS12032C-01 REV. A (MGLS12032C-LED04) NOV/2002
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5.2
Timing Specifications At Ta = 0C to +50C, VDD = 5V5% ,VSS = 0V. Refer to Fig. 2, MPU bus read / write timing diagram (68 family MPU) Table 6 Signal Symbol A0,/CS,R/W tCYC6 A0,/CS,R/W tAW6 A0,/CS,R/W tAH6 DB0-DB7 tDS6 DB0-DB7 tDH6 DB0-DB7 tOH6 DB0-DB7 tACC6 E tEW E tEW tr, tf
Parameter System Cycle Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time Output Disable Time Access Time Enable Pulse Width(Read) Enable Pulse Width(Write) Rise & Fall Time
Condition CL=100pF CL=100pF -
Min. 1000 20 10 80 10 10 100 80 -
Max. 60 90 15
Unit ns ns ns ns ns ns ns ns ns ns
E1 or E2 (E)
A0, CS
Figure 2: MPU bus read / write timing diagram (68 family MPU)
VL-FS-MGLS12032C-01 REV. A (MGLS12032C-LED04) NOV/2002
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5.3 Timing Diagram of VDD against V0. Power on sequence shall meet the requirement of Figure 3, the timing diagram of VDD against V0.
VDD
95%
LOGIC SUPPLY VOLTAGE 0V 50ms(typical)
OV LCD SUPPLY VOLTAGE
V0
Figure 3: Timing diagram of VDD against V0. "Varitronix Limited reserves the right to change this specification." FAX:(852) 2343-9555. URL:http://www.varitronix.com - END -

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