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EL8178
Data Sheet March 29, 2007 FN7504.5
Micropower Single Supply Rail-to-Rail Input-Output (RRIO) Precision Op Amp
The EL8178 is a precision low power, operational amplifier. The device is optimized for single supply operation between 2.4V to 5V. This enables operation from one lithium cell or two Ni-Cd batteries. The input range includes both positive and negative rail. For power sensitive applications, the EL8178 has and EN pin that will shut the device down and reduce the supply current to 3A typ. In the active state, the EL8178 draws minimal supply current (55A) while meeting excellent DCaccuracy, noise, and output drive specifications.
Features
* Typical 55A supply current * 250V max offset voltage * Typical 1pA input bias current * 266kHz gain-bandwidth product * Single supply operation between 2.4V to 5.0V * Rail-to-rail input and output * Ground sensing * Output sources and sinks 26mA load current * Pb-free plus anneal available (RoHS compliant)
Ordering Information
PART NUMBER (Note) EL8178FWZ-T7 PART MARKING BBWA TAPE & REEL 7" (3k pcs) PACKAGE (Pb-free) PKG. DWG. #
Applications
* Battery- or solar-powered systems * 4mA to 20mA current loops * Handheld consumer products * Medical devices * Thermocouple amplifiers * Photodiode pre-amps * pH probe amplifiers
6 Ld SOT-23 MDP0038
EL8178FWZ-T7A BBWA EL8178FSZ EL8178FSZ-T7 8178FSZ 8178FSZ
7" 6 Ld SOT-23 MDP0038 (250 pcs) 97/Tube 8 Ld SO 7" (1k pcs) 8 Ld SO MDP0027 MDP0027
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinouts
EL8178 (6 LD SOT-23) TOP VIEW
OUT 1 VS- 2 IN+ 3 6 VS+ +5 EN 4 IN-
EL8178 (8 LD SO) TOP VIEW
NC 1 IN- 2 IN+ 3 VS- 4 + 8 EN 7 VS+ 6 OUT 5 NC
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2004-2007. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
EL8178
Absolute Maximum Ratings (TA = +25C)
Supply Voltage (VS) and Pwr-up Ramp Rate . . . . . . . . 5.5V, 1V/s Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V Current into IN+, IN-, and EN. . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Input Voltage . . . . . . . . . . . . . . . . . . . . . . . VS- - 0.5V to VS+ + 0.5V ESD Tolerance Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
Thermal Information
Thermal Resistance JA (C/W) 6 Ld SOT Package . . . . . . . . . . . . . . . . . . . . . . . . . 230 8 Ld SO Package . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Ambient Operating Temperature Range . . . . . . . . -40C to +125C Storage Temperature Range . . . . . . . . . . . . . . . . . -65C to +150C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . +125C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER VOS
VS+ = 5V, VS- = 0V, VCM = 2.5V, VO = 2.5V, TA = +25C unless otherwise specified. Boldface limits apply over the operating temperature range, -40C to +125C TEST CONDITIONS MIN -250 -450 TYP 50 MAX 250 450 3 1.1 See Figures 18 and 19 -25 -600 1 25 600 2.8 48 0.15 0 80 75 100 5 UNIT V V V/Mo V/C pA pA VP-P nV/Hz pA/Hz V dB dB 100 dB dB 400 V/mV V/mV 3 130 10 250 350 4.994 4.750 4.7 0.10 0.07 0.15 0.19 0.25 266 4.9975 4.875 mV mV mV V V V V/s V/s kHz
DESCRIPTION Input Offset Voltage
V OS -----------------Time V OS --------------T IB
Long Term Input Offset Voltage Stability Input Offset Drift vs Temperature Input Bias Current
eN
Input Noise Voltage Peak-to-Peak Input Noise Voltage Density
f = 0.1Hz to 10Hz fO = 1kHz fO = 1kHz Guaranteed by CMRR test VCM = 0V to 5V
iN CMIR CMRR
Input Noise Current Density Input Voltage Range Common-Mode Rejection Ratio
PSRR
Power Supply Rejection Ratio
VS = 2.4V to 5V
80 80
AVOL
Large Signal Voltage Gain
VO = 0.5V to 4.5V, RL = 100k to (VS+ + VS-)/2 VOL; Output low, RL = 100k to (VS+ + VS-)/2 VOL; Output low, RL = 1k to (VS+ + VS-)/2 VOH; Output high, RL = 100k to (VS+ + VS-)/2 VOH; Output high, RL = 1k to (VS+ + VS-)/2
100 100
VOUT
Maximum Output Voltage Swing
SR
Slew Rate
GBWP
Gain Bandwidth Product
fO = 100kHz
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FN7504.5 March 29, 2007
EL8178
Electrical Specifications
PARAMETER IS(ON) VS+ = 5V, VS- = 0V, VCM = 2.5V, VO = 2.5V, TA = +25C unless otherwise specified. Boldface limits apply over the operating temperature range, -40C to +125C (Continued) TEST CONDITIONS MIN 35 30 IS(OFF) ISC+ Supply Current, Disabled Short Circuit Output Sourcing Current RL = 10 to opposite supply 23 18 ISCShort Circuit Output Sinking Current RL = 10 to opposite supply 20 15 VS Minimum Supply Voltage Guaranteed by PSRR 2.2 2.4 2.4 VINH VINL IENH IENL EN Pin High Level EN Pin Low Level EN Pin Input Current EN Pin Input Current VEN = 5V VEN = 0V VS = 2.5V, TA = +25C, Unless Otherwise Specified
80 RL 10k VOUT = 0.2VP-P 0 GAIN (dB) GAIN (dB) VS = 1.25 -1 VS = 2.5V -2 VS = 1.0V -3 1k 10k 100k 1M 70 60 50 40 30 20 10 0 -10 -20 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) GAIN = 1 GAIN = 10 GAIN = 5 GAIN = 2 GAIN = 1k RL 10k VOUT = 0.2VP-P GAIN = 500 GAIN = 200 GAIN = 100
DESCRIPTION Supply Current, Enabled
TYP 55
MAX 75 85
UNIT A A A mA mA
3 31
5
26
mA mA V V V 0.8 V A A
2
0.25 -0.5
0.8
2.5 +0.5
Typical Performance Curves
1
FREQUENCY (Hz)
FIGURE 1. UNITY GAIN FREQUENCY RESPONSE at VARIOUS SUPPLY VOLTAGES
FIGURE 2. FREQUENCY RESPONSE at VARIOUS CLOSED LOOP GAINS
60 50 40 30 20 10 0 2 2.5 3 3.5 4 4.5 5 5.5 SUPPLY VOLTAGE (V) INPUT OFFSET VOLTAGE (V)
200 AV = -1 VCM = VDD/2 100
SUPPLY CURRENT (A)
0
-100
-200 -0.5
0.5
1.5
2.5
3.5
4.5
5.5
OUTPUT VOLTAGE (V)
FIGURE 3. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 4. INPUT OFFSET VOLTAGE vs OUTPUT VOLTAGE
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FN7504.5 March 29, 2007
EL8178 Typical Performance Curves
NORMALIZED INPUT OFFSET VOLTAGE (V) 250
(Continued) VS = 2.5V, TA = +25C, Unless Otherwise Specified (Continued)
100 80 60 0 45 PHASE 40 20 GAIN 90 135 180 PHASE SHIFT () CURRENT NOISE (pA/Hz)
150
50
-50
-150
GAIN (dB) 0.5 1.5 2.5 3.5 4.5 5.5
0 -20 10
-250 -0.5
100
1k
10k
100k
1M
COMMON-MODE INPUT VOLTAGE (V)
FREQUENCY (Hz)
FIGURE 5. INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE
FIGURE 6. OPEN LOOP GAIN AND PHASE vs FREQUENCY (RL = 1k)
100 90 80 70 GAIN (dB) 60 50 40 30 20 10 0 -10 10 100 1k 10k 100k 1M FREQUENCY (Hz) GAIN 180 PHASE 135 CMRR (dB) 90 PHASE SHIFT ()
10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90
VCM = 1VP-P RL = 100k AV = +1
-100 10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 7. OPEN LOOP GAIN AND PHASE vs FREQUENCY (RL = 100k)
FIGURE 8. CMRR vs FREQUENCY
VOLTAGE NOISE (nV/Hz)
VS = 1VP-P 0 RL = 100k -10 AV = +1 -20 PSRR (dB) -30 -40 -50 -60 -70 -80 -90 -100 10 100 1k 10k 100k 1M -PSRR +PSRR
10
1000
100
100 VOLTAGE
10
10
1
CURRENT 1 1 10 100 1k 10k FREQUENCY (Hz) 0.1 100k
FREQUENCY (Hz)
FIGURE 9. PSRR vs FREQUENCY
FIGURE 10. INPUT VOLTAGE AND CURRENT NOISE vs FREQUENCY
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FN7504.5 March 29, 2007
EL8178 Typical Performance Curves
(Continued) VS = 2.5V, TA = +25C, Unless Otherwise Specified (Continued)
20 VOLTAGE NOISE (500nV/DIV) 15 VOS DRIFT (V) 2.8VP-P 10 5 0 -5 -10 -15 0 TIME (1s/DIV) 500 1000 TIME (HOURS) 1500 1800
FIGURE 11. 0.1Hz TO 10Hz INPUT VOLTAGE NOISE
FIGURE 12. IVOS DRIFT (SOT-23 PACKAGE) vs TIME
18 13
75 n = 1500 70 65 MAX
VOS DRIFT (V)
8 3 -2 -7 -12
CURRENT (mA)
60 55 50
MEDIAN
MIN 45 40
0
500
1000 TIME (HOURS)
1500
35 -40
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
FIGURE 13. IVOS DRIFT (SOIC PACKAGE) vs TIME
FIGURE 14. ENABLED SUPPLY CURRENT vs TEMPERATURE, VS = 2.5V
5.0 n = 1500 4.5 CURRENT (mA) 4.0 3.5 3.0 MEDIAN 2.5 MIN 2.0 -40 -20 0 20 40 60 80 100 120 VIO (V) MAX
400 n = 1500 300 200 100 0 -100 -200 MIN -300 -400 -40 -20 0 20 40 60 80 100 120 MEDIAN MAX
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 15. DISABLED SUPPLY CURRENT vs TEMPERATURE, VS = 2.5V
FIGURE 16. VOS vs TEMPERATURE, VS = 2.5V
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FN7504.5 March 29, 2007
EL8178 Typical Performance Curves
800 600 400 VIO (V) 200 0 -200 -400 MIN -600 -800 -40 -20 0 20 40 60 80 100 120 MEDIAN IBIAS + (pA) MAX n = 1500
(Continued) VS = 2.5V, TA = +25C, Unless Otherwise Specified (Continued)
160 140 120 100 80 60 40 20 MIN 0 -20 -40 -20 0 20 40 60 80 100 120 MEDIAN MAX n = 1500
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 17. VOS vs TEMPERATURE, VS = 1.2V
FIGURE 18. IBIAS+ vs TEMPERATURE, VS = 2.5V
250 n = 1500 230 210 190 170 150 130 110 90 70 50 30 10 -10 -40 -20 0
130 125 MAX CMRR (dB) 120 115 110 105 100 95 90 MIN 20 40 60 80 TEMPERATURE (C) 100 120 85 80 -40 -20 0 20 40 60 MIN MEDIAN n = 1500 MAX
IBIAS -(pA)
MEDIAN
80
100
120
TEMPERATURE (C)
FIGURE 19. IBIAS- vs TEMPERATURE, VS = 2.5V
FIGURE 20. CMRR vs TEMPERATURE, V+ = 2.5V, 1.5V
130 125 120 PSRR (dB) 115 110 105 100 95 90 85 -40 -20 0 20 40 60 80 100 120 MIN MEDIAN VOUT (V) n = 1500 MAX
4.90 n = 1500 4.89 MAX 4.88 4.87 MEDIAN 4.86 4.85 MIN 4.84 -40 -20 0 20 40 60 80 100 120
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 21. PSRR vs TEMPERATURE 1.5V TO 2.5V
FIGURE 22. VOUT HIGH vs TEMPERATURE, VS = 2.5V, RL = 1k
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FN7504.5 March 29, 2007
EL8178 Typical Performance Curves
4.9984 4.9982 4.9980 4.9978 VOUT (V) 4.9976 4.9974 4.9972 4.9970 4.9968 4.9966 4.9964 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) MIN MEDIAN MAX VOUT (mV) n = 1500
(Continued) VS = 2.5V, TA = +25C, Unless Otherwise Specified (Continued)
190 180 170 160 150 140 MIN 130 120 110 100 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) MEDIAN n = 1500 MAX
FIGURE 23. VOUT HIGH vs TEMPERATURE, VS = 2.5V, RL = 100k
FIGURE 24. VOUT LOW vs TEMPERATURE, VS = 2.5V, RL = 1k
5.0 4.8 4.6 AVOL (V/mV) 4.4 VOUT (mV) 4.2 4.0 3.8 3.6 3.4 3.2 3.0 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) MIN n = 1500 MAX
510 n = 1500 460 410 MEDIAN 360 MEDIAN 310 260 210 160 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) MIN MAX
FIGURE 25. VOUT LOW vs TEMPERATURE, VS = 2.5V, RL = 100k
FIGURE 26. AVOL vs TEMPERATURE, RL = 100k, VO = 2V @ VS = 2.5V
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FN7504.5 March 29, 2007
EL8178 Pin Descriptions
SO PIN NUMBER 1 2 3 4 5 6 7 8 1 6 5 4 3 2 SOT-23 PIN NUMBER PIN NAME NC ININ+ VSNC OUT VS+ EN Circuit 3 Circuit 4 Circuit 2 Circuit 1 Circuit 1 Circuit 4 EQUIVALENT CIRCUIT No internal connection Amplifier's inverting input Amplifier's non-inverting input Negative power supply No internal connection Amplifier's output Positive power supply Amplifier's enable pin with internal pull-down; Logic "1" selects the disabled state; Logic "0" selects the enabled state.
VS+ VS+
CAPACITIVELY COUPLED ESD CLAMP
DESCRIPTION
VS+ ININ+ VS-
VS+ OUT
EN
VS-
VSVSCIRCUIT 3 CIRCUIT 4
CIRCUIT 1
CIRCUIT 2
Application Information
Introduction
The EL8178 is a rail-to-rail input and output (RRIO), micro-power, precision, single supply op amp with an enable feature. This amplifier is designed to operate from single supply (2.4V to 5.0V) or dual supply (1.2V to 2.5V) while drawing only 55A of supply current.The device achieves rail-to-rail input and output operation while eliminating the drawbacks of many conventional RRIO op amps.
Rail-to-Rail Output
A pair of complementary MOSFET devices achieves rail-to-rail output swing. The NMOS sinks current to swing the output in the negative direction, while the PMOS sources current to swing the output in the positive direction. The EL8178 with a 100k load swings to within 3mV of the supply rails.
Results of Over-Driving the Output
Caution should be used when over-driving the output for long periods of time. Over-driving the output can occur in three ways: 1. The input voltage times the gain of the amplifier exceeds the supply voltage by a large value. 2. The output current required is higher than the output stage can deliver. 3. Operating the device in Slew Rate Limit. These conditions can result in a shift in the Input Offset Voltage (VOS) as much as 1V/hr of exposer under these condition.
Rail-to-Rail Input
The PFET input stage of the EL8178 has an input common-mode voltage range that includes the negative and positive supplies without introducing offset errors or degrading performance like some existing rail-to-rail input op amps. Many rail-to-rail input stages use two differential input pairs: a long-tail PNP (or PFET) and an NPN (or NFET). Severe penalties result from using this topology. As the input signal moves from one supply rail to the other, the op amp switches from one input pair to the other causing changes in input offset voltage and an undesired change in the input offset current's magnitude and polarity. The EL8178 achieves rail-to-rail input performance without sacrificing important precision specifications and without degrading distortion performance. The EL8178's input offset voltage exhibits a smooth behavior throughout the entire common-mode input range.
Enable/Disable Feature
The EL8178 features an active low EN pin that when pulled up to at least 2V, disables the output and drops the ICC to a 3A. The EN pin has an internal pull down, so an undriven pin pulls to the negative rail, thereby enabling the op amp by default. For applications where the EN pin is not being used, it is recommended that the EN pin be permanently tie to ground. The high impedance output during disable allows for connecting multiple EL8178s together to implement a Mux Amp. The outputs are connected together and activating the appropriate EN pin selects the desired channel. If utilizing
8
FN7504.5 March 29, 2007
EL8178
non-unity gain op amp configurations, then the loading effects of the disabled amplifiers' feedback networks must be considered when evaluating the active amplifier's performance in Mux Amp configurations. Note that feed through from the IN+ to IN- pins occurs on any Mux Amp disabled channel where the input differential voltage exceeds 0.5V (e.g., active channel VOUT = 1V, while disabled channel VIN = GND), so the mux implementation is best suited for small signal applications. In any application where two or more amplifier outputs are muxed, use series IN+ resistors, or large value RFs in each amplifier to keep the feed through current low enough to minimize the impact on the active channel. See "Usage Implications" on page 9 for more details. EN Input Protection The EN input has internal ESD protection diodes to both the positive and negative supply rails, limiting the input voltage range to within one diode beyond the supply rails (see "Circuit 2" diagram on page 8). If the input voltage is expected to exceed VS+ or VS-, then an external series resistor should be added to limit the current to 5mA.
Output Current Limiting
The EL8178 has no internal current-limiting circuitry. If the output is shorted, it is possible to exceed the "Absolute Maximum Rating" for "operating junction temperature", potentially resulting in the destruction of the device.
Power Dissipation
It is possible to exceed the +150C maximum junction temperature (TJMAX) under certain load and power-supply conditions. It is therefore important to calculate TJMAX for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related as follows:
T JMAX = T MAX + ( JA xPDMAX ) (EQ. 1)
IN+ and IN- Input Protection
In addition to ESD protection diodes to each supply rail, the EL8178 has additional back-to-back protection diodes across the differential input terminals (see "Circuit 1" diagram on page 8). If the magnitude of the differential input voltage exceeds the diode's VF, then one of these diodes will conduct. For elevated temperatures, the leakage of the protection diodes (Circuit 1 pin description table) increases, resulting in the increase in Ibias as seen in Figures 18 and 19. Usage Implications If the input differential voltage is expected to exceed 0.5V, an external current limiting resistor must be used to ensure the input current never exceeds 5mA. For noninverting unity gain applications the current limiting can be via a series IN+ resistor, or via a feedback resistor of appropriate value. For other gain configurations, the series IN+ resistor is the best choice, unless the feedback (RF) and gain setting (RG) resistors are both sufficiently large to limit the input current to 5mA. Large differential input voltages can arise from several sources: 1) During open loop (comparator) operation. The IN+ and INinput voltages don't track. 2) When the amplifier is disabled but an input signal is still present. An RL or RG to GND keeps the IN- at GND, while the varying IN+ signal creates a differential voltage. Mux Amp applications are similar, except that the active channel VOUT determines the voltage on the IN- terminal. 3) When the slew rate of the input pulse is considerably faster than the op amp's slew rate. If the VOUT can't keep up with the IN+ signal, a differential voltage results, and visible distortion occurs on the input and output signals. To avoid this issue, keep the input slew rate below 0.2V/s, or use appropriate current limiting resistors. Large (>2V) differential input voltages can also cause an increase in disabled ICC.
where PDMAX is calculated using:
V OUTMAX PD MAX = V S x I SMAX + ( V S - V OUTMAX ) x --------------------------R
L
(EQ. 2)
where: * TMAX = Maximum ambient temperature * JA = Thermal resistance of the package * PDMAX = Maximum power dissipation of the amplifier * VS = Supply voltage * IMAX = Maximum supply current of the amplifier * VOUTMAX = Maximum output voltage swing of the application * RL = Load resistance
Proper Layout Maximizes Precision
To achieve the optimum levels of high input impedance (i.e., low input currents) and low offset voltage, care should be taken in the circuit board layout. The PC board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. Surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resistance on the board. When input leakage current is a paramount concern, the use of guard rings around the amplifier inputs will further reduce leakage currents. Figure 27 shows a guard ring example for a unity gain amplifier that uses the low impedance amplifier output at the same voltage as the high impedance input to eliminate surface leakage. The guard ring does not need to be a
FN7504.5 March 29, 2007
9
EL8178
specific width, but it should form a continuous loop around both inputs. For further reduction of leakage currents, mount components to the PC board using Teflon standoffs.
HIGH IMPEDANCE INPUT IN R4 100k R3 10k 10k VS+ + EL8178 VSV+
a low-cost coax cable. The EL8178 PMOS high impedance input senses the pH probe output signal and buffers it to drive the coax cable. Its rail-to-rail input nature also eliminates the need for a bias resistor network required by other amplifiers in the same application.
FIGURE 27. GUARD RING EXAMPLE FOR UNITY GAIN AMPLIFIER
R2 K TYPE THERMOCOUPLE
410V/C + 5V
Typical Applications
VS+ + EL8178 VS-
R1 100k + 3V COAX
FIGURE 29. THERMOCOUPLE AMPLIFIER
GENERAL PURPOSE COMBINATION pH PROBE
FIGURE 28. pH PROBE AMPLIFIER
A general-purpose combination pH probe has extremely high output impedance typically in the range of 10G to 12G. Low loss and expensive Teflon cables are often used to connect the pH probe to the meter electronics. Figure 28 details a low-cost alternative solution using the EL8178 and
Thermocouples are the most popular temperature sensing devices because of their low cost, interchangeability, and ability to measure a wide range of temperatures. In Figure 29, the EL8178 converts the differential thermocouple voltage into single-ended signal with 10X gain. The EL8178's rail-to-rail input characteristic allows the thermocouple to be biased at ground and permits the op amp to operate from a single 5V supply.
10
FN7504.5 March 29, 2007
EL8178 Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL "X"
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L 4 4
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. M 2/07
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FN7504.5 March 29, 2007
EL8178 SOT-23 Package Family
e1 A N 6 4
MDP0038
D
SOT-23 PACKAGE FAMILY MILLIMETERS SYMBOL A A1 SOT23-5 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 5 SOT23-6 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 6 TOLERANCE MAX 0.05 0.15 0.05 0.06 Basic Basic Basic Basic Basic 0.10 Reference Reference Rev. F 2/07 NOTES:
E1 2 3
E
A2 b c
0.20 C
0.15 C D 2X 5 e B b NX 1 2 3 2X 0.20 M C A-B D
D E E1 e e1 L L1 N
0.15 C A-B 2X C D
1
3
A2 SEATING PLANE 0.10 C NX A1
1. Plastic or metal protrusions of 0.25mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. This dimension is measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Index area - Pin #1 I.D. will be located within the indicated zone (SOT23-6 only).
(L1)
H
6. SOT23-5 version has no center lead (shown as a dashed line).
A
GAUGE PLANE c L 0 +3 -0
0.25
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN7504.5 March 29, 2007

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