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| 350 MHz Single-Supply (5 V) Triple 2:1 Multiplexers AD8188/AD8189 FEATURES Fully buffered inputs and outputs Fast channel-to-channel switching: 4 ns Single-supply operation (5 V) High speed 350 MHz bandwidth (-3 dB) @ 200 mV p-p 300 MHz bandwidth (-3 dB) @ 2 V p-p Slew rate: 1000 V/s Fast settling time: 7 ns to 0.1% Low current: 19 mA/20 mA Excellent video specifications: load resistor (RL) = 150 Differential gain error: 0.05% Differential phase error: 0.05 Low glitch All hostile crosstalk -84 dB @ 5 MHz -52 dB @ 100 MHz High off isolation: -95 dB @ 5 MHz Low cost Fast, high impedance disable feature for connecting multiple outputs Logic-shifted outputs FUNCTIONAL BLOCK DIAGRAM IN0A DGND IN1A VREF IN2A VCC VEE IN2B VEE 1 2 3 4 5 6 7 8 9 2 1 24 VCC OE SEL A/B VCC OUT0 VEE OUT1 VCC OUT2 VEE VCC 06239-001 LOGIC SELECT 23 22 ENABLE 0 21 20 19 18 17 16 15 14 IN1B 10 VEE 11 IN0B 12 DVCC AD8188/AD8189 13 Figure 1. APPLICATIONS Switching RGB in LCD and plasma displays RGB video switchers and routers GENERAL DESCRIPTION The AD8188 (G = 1) and AD8189 (G = 2) are high speed, single-supply, triple 2-to-1 multiplexers. They offer -3 dB small signal bandwidth of 350 MHz and -3 dB large signal bandwidth of 300 MHz, along with a slew rate in excess of 1000 V/s. With -84 dB of all hostile crosstalk and -95 dB off isolation, the parts are well suited for many high speed applications. The differential gain and differential phase error of 0.05% and 0.05 respectively, along with 0.1 dB flatness to 70 MHz, make the AD8188 and AD8189 ideal for professional and component video multiplexing. The parts offer 4 ns switching time, making them an excellent choice for switching video signals, while consuming less than 20 mA on a single 5 V supply (100 mW). Both devices have a high speed disable feature that sets the outputs into a high impedance state. This allows the building of larger input arrays while minimizing off-channel output loading. The devices are offered in a 24-lead TSSOP. 4.0 3.5 3.0 6.0 5.5 5.0 INPUT 4.5 4.0 3.5 3.0 OUTPUT 2.5 2.0 1.5 0 5 10 TIME (ns) 15 20 06239-002 INPUT VOLTAGE (V) 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 1.0 25 Figure 2. AD8189 Video Amplitude Pulse Response, VOUT = 1.4 V p-p, RL = 150 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved. OUTPUT VOLTAGE (V) AD8188/AD8189 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 Maximum Power Dissipation ..................................................... 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ...................................................................... 14 High Impedance Disable ........................................................... 14 Off Isolation ................................................................................ 14 Full Power Bandwidth vs. -3 dB Large Signal Bandwidth ... 14 Single-Supply Considerations................................................... 14 AC-Coupled Inputs.................................................................... 16 Tolerance to Capacitive Load.................................................... 16 Secondary Supplies and Supply Bypassing ............................. 16 Split-Supply Operation .............................................................. 16 Applications..................................................................................... 17 Single-Supply Operation ........................................................... 17 AC-Coupling............................................................................... 17 DC Restore .................................................................................. 19 High Speed Design Considerations ......................................... 20 Evaluation Board ............................................................................ 21 Schematics................................................................................... 23 Outline Dimensions ....................................................................... 24 Ordering Guide .......................................................................... 24 REVISION HISTORY 10/06--Revision 0: Initial Version Rev. 0 | Page 2 of 24 AD8188/AD8189 SPECIFICATIONS TA = 25C. For the AD8188, VS = 5 V, RL = 1 k to 2.5 V. For the AD8189, VS = 5 V, VREF = 2.5 V, RL = 150 to 2.5 V; unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth (Small Signal) -3 dB Bandwidth (Large Signal) 0.1 dB Flatness Slew Rate (10% to 90% Rise Time) Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Differential Gain Differential Phase All Hostile Crosstalk Channel-to-Channel Crosstalk, RTI Off Isolation Input Voltage Noise DC PERFORMANCE Voltage Gain Error Voltage Gain Error Matching VREF Gain Error Input Offset Voltage Input Offset Voltage Matching Input Offset Drift Input Bias Current VREF Bias Current (AD8189 Only) INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Voltage Range (About Midsupply) OUTPUT CHARACTERISTICS Output Voltage Swing Short-Circuit Current Output Resistance Output Capacitance POWER SUPPLY Operating Range Power Supply Rejection Ratio Quiescent Current Conditions VOUT = 200 mV p-p VOUT = 2 V p-p VOUT = 200 mV p-p VOUT = 2 V p-p, RL = 150 VIN = 1 V Step, RL = 150 3.58 MHz, RL = 150 3.58 MHz, RL = 150 5 MHz 100 MHz 5 MHz 5 MHz f = 100 kHz to 100 MHz No load Channel A to Channel B 1 k load TMIN to TMAX Channel A to Channel B Min AD8188/AD8189 Typ Max 350 300 70 1000 6/7.5 0.05 0.05 -84/-78 -52/-48 -90/-85 -84/-95 7/9 0.1 0.04 0.04 0.2/0.5 8.0 0.2 10/5 1.5 1.0 1.8/1.3 0.9/1.0 1.2 +0.9/-1.2 3.1/2.8 2.8/2.5 3.2/3.0 3.0/2.7 85 0.2/0.35 1000/600 1.5/2.0 5.5 -72/-61 -76/-72 18.5/19.5 3.5/4.5 15 3.6/4 4/3.8 0.3/0.6 0.2/0.2 0.6 6.5/7.0 5.0/5.5 4/4 Unit MHz MHz MHz V/s ns % Degrees dB dB dB dB nV/Hz % % % mV mV mV V/C A A M pF V V V p-p V p-p mA k pF V dB dB mA mA mA ns ns @ 100 kHz IN0A, IN0B, IN1A, IN1B, IN2A, IN2B VREF RL = 1 k RL = 150 Enabled @ 100 kHz Disabled @ 100 kHz Disabled 3.5 +PSRR, VCC = 4.5 V to 5.5 V, VEE = 0 V -PSRR, VEE = -0.5 V to +0.5 V, VCC = 5.0 V All channels on All channels off TMIN to TMAX, all channels on 50% logic to 50% output settling, INxA = +1 V, INxB = -1 V 50% logic to 50% output settling, input = 1 V Rev. 0 | Page 3 of 24 21.5/22.5 4.5/5.5 23 SWITCHING CHARACTERISTICS Channel-to-Channel Switching Time Enable-to-Channel On Time AD8188/AD8189 Parameter Disable-to-Channel Off Time Channel Switching Transient (Glitch) Output Enable Transient (Glitch) DIGITAL INPUTS Logic 1 Voltage Logic 0 Voltage Logic 1 Input Current Logic 0 Input Current Conditions 50% logic to 50% output settling, input = 1 V All channels grounded All channels grounded SEL A/B, OE SEL A/B, OE SEL A/B, OE = 2.0 V SEL A/B, OE = 0.5 V Min AD8188/AD8189 Typ Max 17/5 21/45 64/118 Unit ns mV mV V V nA A 1.6 0.6 45 2 Rev. 0 | Page 4 of 24 AD8188/AD8189 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage DVCC to DGND DVCC to VEE VCC to DGND IN0A, IN0B, IN1A, IN1B, IN2A, IN2B, VREF SEL A/B, OE Output Short-Circuit Operation Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering, 10 sec) 1 MAXIMUM POWER DISSIPATION 1 Rating 5.5 V 5.5 V 8.0 V 8.0 V VEE VIN VCC DGND VIN VCC Indefinite -40C to +85C -65C to +150C 300C The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175C for an extended period can result in device failure. While the AD8188/AD8189 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (150C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves shown in Figure 3. 2.5 Specification is for device in free air (TA = 25C). MAXIMUM POWER DISSIPATION (W) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2.0 1.5 1.0 THERMAL RESISTANCE JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance Package Type 24-Lead TSSOP1 1 0.5 0 10 20 30 40 50 60 70 80 90 JA 85 2 JC 20 Unit C/W AMBIENT TEMPERATURE (C) Figure 3. Maximum Power Dissipation vs. Temperature Maximum internal power dissipation (PD) should be derated for ambient temperature (TA) such that PD < (150C TA)/JA. 2 JA is on a 4-layer board (2s 2p). ESD CAUTION Rev. 0 | Page 5 of 24 06239-003 0 -50 -40 -30 -20 -10 AD8188/AD8189 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IN0A DGND IN1A VREF IN2A VCC VEE IN2B VEE 1 2 3 4 5 6 7 8 9 24 23 22 VCC OE SEL A/B VCC OUT0 19 VEE TOP VIEW (Not to Scale) 18 OUT1 17 16 15 14 13 AD8188/ AD8189 21 20 VCC OUT2 VEE VCC 06239-004 IN1B 10 VEE 11 IN0B 12 DVCC Figure 4. AD8188/AD8189 Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 6, 13, 17, 21, 24 7, 9, 11, 15, 19 8 10 12 14 16 18 20 22 23 Mnemonic IN0A DGND IN1A VREF IN2A VCC VEE IN2B IN1B IN0B DVCC OUT2 OUT1 OUT0 SEL A/B OE Description Input, High-ZIN. Routed to OUT0 when A is selected. Ground Reference for Digital Control Circuitry. Input, High-ZIN. Routed to OUT1 when A is selected. AD8188: Bypass point for internal reference. Does not affect dc level of output. AD8189: Input to reference buffers for all channels. Can be used to offset the outputs. Input, High-ZIN. Routed to OUT2 when A is selected. Positive Analog Supply. Nominally 5 V higher than VEE. Negative Analog Supply. Input, High-ZIN. Routed to OUT2 when B is selected. Input, High-ZIN. Routed to OUT1 when B is selected. Input, High-ZIN. Routed to OUT0 when B is selected. Positive Supply for Digital Control Circuitry. Referenced to DGND. Output. Can connect to IN2A, IN2B, or disable. Output. Can connect to IN1A, IN1B, or disable. Output. Can connect to IN0A, IN0B, or disable. Logic high selects the three A inputs. Logic low selects the three B inputs. Output Enable. Logic high enables the three outputs. Table 5. Truth Table SEL A/B 0 1 1 0 OE 0 0 1 1 OUT High-Z High-Z INxA INxB Rev. 0 | Page 6 of 24 AD8188/AD8189 TYPICAL PERFORMANCE CHARACTERISTICS 3 2 1 0 50 DUT 0.6 976 52.3 GAIN 0.5 0.4 1 0 GAIN 0.5 0.4 0.3 0.2 0.1 FLATNESS 0 -0.1 -0.2 10k -1 -2 -3 -4 -5 -6 0.1 -1 -2 -3 -4 -5 -6 0.1 FLATNESS 0.2 0.1 0 -0.1 -0.2 06239-005 1 10 100 1k 1 10 100 1k FREQUENCY (MHz) FREQUENCY (MHz) Figure 5. AD8188 Frequency Response, VOUT = 200 mV p-p, RL = 1 k 1 0 -1 Figure 8. AD8189 Frequency Response, VOUT = 200 mV p-p, RL = 150 1 0 NORMALIZED GAIN (dB) -2 GAIN (dB) -1 -2 -3 -4 -5 -6 0.1 -3 -4 -5 -6 -7 50 150 DUT 976 52.3 06239-006 1 10 FREQUENCY (MHz) 100 1k 1 10 FREQUENCY (MHz) 100 1k Figure 6. AD8188 Frequency Response, VOUT = 2 V p-p, RL = 1 k 1 0 -1 GAIN (dB) Figure 9. AD8189 Frequency Response, VOUT = 2 V p-p, RL = 150 1 +85C +25C NORMALIZED GAIN (dB) -40C +25C 0 -1 -2 -3 -4 -5 -6 0.1 +85C -40C -2 -3 -4 150 -5 50 DUT 976 52.3 06239-007 1 10 FREQUENCY (MHz) 100 1k 1 10 FREQUENCY (MHz) 100 1k Figure 7. AD8188 Large Signal Bandwidth vs. Temperature, VOUT = 2 V p-p, RL = 1 k Figure 10. AD8189 Large Signal Bandwidth vs. Temperature, VOUT = 2 V p-p, RL = 150 Rev. 0 | Page 7 of 24 06239-010 -6 0.1 06239-009 -8 0.1 06239-008 -0.3 10k FLATNESS (dB) 0.3 NORMALIZED FLATNESS (dB) NORMALIZED GAIN (dB) GAIN (dB) AD8188/AD8189 0 -10 -20 -30 CROSSTALK (dB) 0 -10 -20 -30 CROSSTALK (dB) 06239-011 -40 -50 -60 -70 -80 -90 -100 -110 0.1 1 10 FREQUENCY (MHz) 100 1k -40 -50 -60 -70 -80 -90 -100 1 10 FREQUENCY (MHz) 100 1k 06239-014 06239-016 06239-015 -110 0.1 Figure 11. AD8188 All Hostile Crosstalk vs. Frequency (Drive All INxA, Listen to Output with INxB Selected) 0 -10 -20 -30 CROSSTALK (dB) Figure 14. AD8189 All Hostile Crosstalk vs. Frequency (Drive All INxA, Listen to Output with INxB Selected) 0 -10 -20 -30 CROSSTALK (dB) -40 -50 -60 -70 -80 -90 -100 1 10 FREQUENCY (MHz) 100 1k 06239-012 -40 -50 -60 -70 -80 -90 -100 -110 -120 0.1 1 10 FREQUENCY (MHz) 100 1k -110 0.1 Figure 12. AD8188 Adjacent Channel Crosstalk vs. Frequency (Drive One INxA, Listen to an Adjacent Output with INxB Selected) 0 -10 -20 OFF ISOLATION (dB) Figure 15. AD8189 Adjacent Channel Crosstalk vs. Frequency (Drive One INxA, Listen to an Adjacent Output with INxB Selected) 0 -10 -20 -30 OFF ISOLATION (dB) -30 -40 -50 -60 -70 -80 -90 1 10 100 1k 06239-013 -40 -50 -60 -70 -80 -90 -100 -110 -120 1 10 100 1k -100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 13. AD8188 Off Isolation vs. Frequency (Drive Inputs with OE Tied Low) Figure 16. AD8189 Off Isolation vs. Frequency (Drive Inputs with OE Tied Low) Rev. 0 | Page 8 of 24 AD8188/AD8189 0 -10 -20 0 -10 -20 DISTORTION (dBc) -40 -50 -60 THIRD -70 -80 -90 06239-017 DISTORTION (dBc) -30 -30 -40 -50 THIRD -60 -70 -80 -90 SECOND SECOND 1 10 FREQUENCY (MHz) 100 1 10 FREQUENCY (MHz) 100 Figure 17. AD8188 THD vs. Frequency, VOUT = 2 V p-p, RL = 150 0 -10 -20 -30 Figure 20. AD8189 THD vs. Frequency, VOUT = 2 V p-p, RL = 150 0 -10 -20 PSRR (dBc) PSRR (dBc) -40 -50 -60 -70 -80 -PSRR -30 -PSRR -40 -50 -60 +PSRR -70 -80 0.01 +PSRR 06239-018 0.1 1 FREQUENCY (MHz) 10 100 0.1 1 FREQUENCY (MHz) 10 100 Figure 18. AD8188 PSRR vs. Frequency, RL = 150 20 18 16 14 20 18 16 14 Figure 21. AD8189 PSRR vs. Frequency, RL = 150 NOISE (nV/ Hz) 12 10 8 6 4 2 06239-019 NOISE (nV/ Hz) 12 10 8 6 4 2 0.1 1 10 100 1k 10k 0.1 1 10 100 1k 10k FREQUENCY (MHz) FREQUENCY (MHz) Figure 19. AD8188 Input Voltage Noise vs. Frequency Figure 22. AD8189 Input Voltage Noise vs. Frequency Rev. 0 | Page 9 of 24 06239-022 0 0.01 0 0.01 06239-021 -90 0.01 06239-020 -100 -100 AD8188/AD8189 10k 10k 1k 1k IMPEDANCE (k) 100 IMPEDANCE (k) 06239-023 100 10 10 1 1 1 10 FREQUENCY (MHz) 100 1k 1 10 FREQUENCY (MHz) 100 1k Figure 23. AD8188 Input Impedance vs. Frequency 1k 1k Figure 26. AD8189 Input Impedance vs. Frequency 100 IMPEDANCE () IMPEDANCE () 100 10 10 1 1 06239-024 1 10 FREQUENCY (MHz) 100 1k 1 10 FREQUENCY (MHz) 100 1k Figure 24. AD8188 Enabled Output Impedance vs. Frequency 10k Figure 27. AD8189 Enabled Output Impedance vs. Frequency 10k 1k 1k IMPEDANCE (k) 100 IMPEDANCE (k) 100 10 10 1 1 06239-025 1 10 FREQUENCY (MHz) 100 1k 1 10 FREQUENCY (MHz) 100 1k Figure 25. AD8188 Disabled Output Impedance vs. Frequency Figure 28. AD8189 Disabled Output Impedance vs. Frequency Rev. 0 | Page 10 of 24 06239-028 0.1 0.1 0.1 0.1 06239-027 0.1 0.1 0.1 0.1 06239-026 0.1 0.1 0.1 0.1 AD8188/AD8189 2.8 2.7 2.6 INPUT 3.3 2.8 2.7 2.6 INPUT 3.2 3.1 3.0 2.9 2.8 2.7 OUTPUT 2.6 2.5 2.4 2.3 0 5 10 TIME (ns) 15 20 06239-032 OUTPUT VOLTAGE (V) INPUT VOLTAGE (V) INPUT VOLTAGE (V) 2.5 2.4 2.3 2.2 OUTPUT 2.1 2.0 1.9 0 5 10 TIME (ns) 15 20 2.8 2.5 2.4 2.3 2.2 2.1 2.0 1.9 Figure 29. AD8188 Small Signal Pulse Response, VOUT = 200 mV p-p, RL = 1 k 3.0 2.5 2.0 INPUT 5.0 4.5 4.0 3.5 3.0 OUTPUT 2.5 2.0 1.5 1.0 25 4.0 3.5 3.0 06239-029 1.8 2.3 25 1.8 2.2 25 Figure 32. AD8189 Small Signal Pulse Response, VOUT = 200 mV p-p, RL = 150 k 6.0 5.5 5.0 4.5 4.0 OUTPUT 3.5 3.0 2.5 2.0 1.5 0 5 10 TIME (ns) 15 20 06239-033 OUTPUT VOLTAGE (V) INPUT VOLTAGE (V) 1.5 1.0 0.5 0 -0.5 -1.0 INPUT VOLTAGE (V) 2.5 2.0 1.5 1.0 0.5 0 -0.5 0 5 10 TIME (ns) 15 20 Figure 30. AD8188 Video Amplitude Pulse Response, VOUT = 700 mV p-p, RL = 1 k 4.0 3.5 3.0 2.5 INPUT 7.0 6.5 6.0 4.0 3.5 3.0 06239-030 -1.0 1.0 25 Figure 33. AD8189 Video Amplitude Pulse Response, VOUT = 1.4 V p-p, RL = 150 k 6.0 5.5 INPUT 5.0 OUTPUT VOLTAGE (V) 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 0 5 10 TIME (ns) 15 20 OUTPUT 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 OUTPUT 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 5 10 TIME (ns) 15 20 06239-031 Figure 31. AD8188 Large Signal Pulse Response, VOUT = 2 V p-p, RL = 1 k Figure 34. AD8189 Large Signal Pulse Response, VOUT = 2 V p-p, RL = 150 k Rev. 0 | Page 11 of 24 06239-034 1.0 25 -2.0 0 25 OUTPUT VOLTAGE (V) 5.5 2.5 4.5 INPUT VOLTAGE (V) INPUT VOLTAGE (V) OUTPUT VOLTAGE (V) INPUT OUTPUT VOLTAGE (V) AD8188/AD8189 OUTPUT (1mV/DIV) tSETTLED OUTPUT (1mV/DIV) tSETTLED 06239-035 t0 TIME (2ns/DIV) t0 TIME (2ns/DIV) Figure 35. AD8188 Settling Time (0.1%), VOUT = 2 V Step, RL = 1 k 2.3 1.8 SELECT A/B PULSE AMPLITUDE (V) Figure 38. AD8189 Settling Time (0.1%), VOUT = 2 V Step, RL = 150 2.0 1.5 SELECT A/B PULSE AMPLITUDE (V) 6.0 5.5 SEL A/B 5.0 OUTPUT AMPLITUDE (V) 5.5 5.0 4.5 4.0 3.5 OUTPUT 3.0 2.5 2.0 1.5 06239-039 1.3 0.8 0.3 -0.3 -0.8 -1.3 -1.8 -2.3 -2.8 0 5 10 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 4.5 4.0 3.5 OUTPUT 3.0 2.5 2.0 1.5 15 TIME (ns) 20 06239-036 1.0 25 -2.5 0 5 10 TIME (ns) 15 20 1.0 25 Figure 36. AD8188 Channel-to-Channel Switching Time, VOUT = 2 V p-p, INxA = 3.5 V, INxB = 1.5 V 2.0 3.0 2.0 Figure 39. AD8189 Channel-to-Channel Switching Time, VOUT = 2 V p-p, INxA = 3.0 V, INxB = 2.0 V 3.0 SELECT A/B PULSE AMPLITUDE (V) 1.5 SEL A/B 1.0 SELECT A/B PULSE AMPLITUDE (V) 2.9 OUTPUT AMPLITUDE (V) 1.5 SEL A/B 1.0 2.9 OUTPUT AMPLITUDE (V) 06239-040 2.8 2.8 0.5 2.7 0.5 2.7 0 OUTPUT 2.6 0 OUTPUT 2.6 -0.5 2.5 -0.5 2.5 0 5 10 15 20 25 TIME (ns) 30 35 40 45 06239-037 -1.0 2.4 50 -1.0 0 5 10 15 20 25 TIME (ns) 30 35 40 45 2.4 50 Figure 37. AD8188 Channel Switching Transient (Glitch), INxA = INxB = 0 V Figure 40. AD8189 Channel Switching Transient (Glitch), INxA = INxB = VREF = 0 V Rev. 0 | Page 12 of 24 OUTPUT AMPLITUDE (V) SEL A/B 06239-038 AD8188/AD8189 2.0 1.5 OE 5.5 5.0 2.0 1.5 OE 6.0 5.5 OE PULSE AMPLITUDE (V) OE PULSE AMPLITUDE (V) OUTPUT AMPLITUDE (V) 1.0 0.5 0 -0.5 -1.0 -1.5 OUTPUT 4.5 4.0 3.5 3.0 2.5 2.0 200 0.5 0 -0.5 -1.0 -1.5 -2.0 OUTPUT 4.5 4.0 3.5 3.0 2.5 2.0 200 06239-041 OUTPUT AMPLITUDE (V) OUTPUT AMPLITUDE (V) 06239-044 06239-043 1.0 5.0 0 20 40 60 80 100 120 140 160 180 0 20 40 60 80 100 120 140 160 180 TIME (ns) TIME (ns) Figure 41. AD8188 Enable On/Off Time, VOUT = 0 V to 1 V 1.5 3.0 2.0 Figure 43. AD8189 Enable On/Off Time, VOUT = 0 V to 1 V 3.0 2.9 1.5 2.9 OE OE PULSE AMPLITUDE (V) OE 1.0 2.8 OE PULSE AMPLITUDE (V) OUTPUT AMPLITUDE (V) 1.0 2.8 2.7 0.5 2.7 0.5 OUTPUT 2.6 0 OUTPUT -0.5 2.6 2.5 2.5 0 06239-042 0 5 10 15 20 25 TIME (ns) 30 35 40 45 2.4 50 -1.0 0 5 10 15 20 25 TIME (ns) 30 35 40 45 2.4 50 Figure 42. AD8188 Channel Enable/Disable Transient (Glitch) Figure 44. AD8189 Channel Enable/Disable Transient (Glitch) Rev. 0 | Page 13 of 24 AD8188/AD8189 THEORY OF OPERATION The AD8188 (G = 1) and AD8189 (G = 2) are single-supply, triple 2:1 multiplexers with TTL-compatible global input switching and output-enable control. Optimized for selecting between two RGB (red, green, blue) video sources, the devices have high peak slew rates, maintaining their bandwidth for large signals. Additionally, the multiplexers are compensated for high phase margin, minimizing overshoot for good pixel resolution. The multiplexers also have respectable video specifications and are superior for switching NTSC or PAL composite signals. The multiplexers are organized as three independent channels, each with two input transconductance stages and one output transimpedance stage. The appropriate input transconductance stages are selected via one logic pin (SEL A/B) such that all three outputs simultaneously switch input connections. The unused input stages are disabled with a proprietary clamp circuit to provide excellent crosstalk isolation between on and off inputs while protecting the disabled devices from damaging reverse base-emitter voltage stress. No additional input buffering is necessary, resulting in low input capacitance and high input impedance without additional signal degradation. The transconductance stage is a high slew rate, class AB circuit that sources signal current into a high impedance node. Each output stage contains a compensation network and is buffered to the output by a complementary emitter-follower stage. Voltage feedback sets the gain with the AD8188 configured as a unity gain follower, and the AD8189 configured as a gain-of-two amplifier with a feedback network. This architecture provides drive for a reverse-terminated video load (150 ) with low differential gain and phase errors, while consuming relatively little power. Careful chip layout and biasing result in excellent crosstalk isolation between channels. muxes. In this case, the proper load resistance for the off isolation calculation is the output impedance of an enabled AD8188, typically less than a 1/10 . FULL POWER BANDWIDTH VS. -3 dB LARGE SIGNAL BANDWIDTH Note that full power bandwidth for an undistorted sinusoidal signal is often calculated using the peak slew rate from the equation Full Power Bandwidth = Peak Slew Rate 2 x Sinusoid Amplitude The peak slew rate is not the same as the average slew rate. The average slew rate is typically specified as the ratio VOUT t measured between the 20% and 80% output levels of a sufficiently large output pulse. For a natural response, the peak slew rate can be 2.7 times larger than the average slew rate. Therefore, calculating a full power bandwidth with a specified average slew rate gives a pessimistic result. See the Specifications section for the large-signal bandwidth and average slew rate for both the AD8188 and AD8189 (large signal bandwidth is defined as the -3 dB point measured on a 2 V p-p output sine wave). Figure 17 and Figure 20 contain plots for the second- and thirdorder harmonic distortion. Specifying these three aspects of the signal path's large signal dynamics allows the user to predict system behavior for either pulse or sinusoid waveforms. SINGLE-SUPPLY CONSIDERATIONS The AD8188 and AD8189 offer superior large signal dynamics. The trade-off is that the input and output compliance is limited to ~1.3 V from either rail when driving a 150 load. The following sections address some challenges of designing video systems within a single 5 V supply. HIGH IMPEDANCE DISABLE The output-enable logic pin (OE) of the AD8188 and AD8189 controls whether the three outputs are enabled or disabled to a high impedance state. The high impedance disable allows larger matrices to be built by busing the outputs together. In the case of the AD8189 (G = 2), the reference buffers also disable to a state of high output impedance. This feature prevents the feedback network of a disabled channel from loading the output, which is valuable when busing together the outputs of several muxes. The AD8188 The AD8188 is internally wired as a unity-gain follower. Its inputs and outputs can both swing to within ~1.3 V of either rail. This affords the user 2.4 V of dynamic range at input and output that should be enough for most video signals, whether the inputs are ac- or dc-coupled. In both cases, the choice of output termination voltage determines the quiescent load current. For improved supply rejection, the VREF pin should be tied to an ac ground (the more quiet the supply, the better). Internally, the VREF pin connects to one terminal of an on-chip capacitor. The capacitor's other terminal connects to an internal node. The consequence of building this bypass capacitor on-chip is twofold. First, the VREF pin on the AD8188 draws no input bias current. (Contrast this to the case of the AD8189, where the VREF pin typically draws 2 A of input bias current.) Second, on the AD8188, the VREF pin can be tied to any voltage within the supply range. OFF ISOLATION The off isolation performance of the signal path is dependent upon the value of the load resistor, RL. For calculating off isolation, the signal path can be modeled as a simple high-pass network with an effective capacitance of 3 fF. Off isolation improves as the load resistance is decreased. In the case of the AD8188, off isolation is specified with a 1 k load. However, a practical application would likely gang the outputs of multiple Rev. 0 | Page 14 of 24 AD8188/AD8189 AD8188 MUX SYSTEM IN0A IN0B IN1A IN1B IN2A IN2B "C_BYPASS" VREF INTERNAL CAP BIAS REFERENCE 06239-045 5V 5V OUT0 1.3V VO_MAX = 3.7V OUT0 VOUT VO_MIN = 1.3V 1.3V GND A0 OUT1 OUT2 5V 5V VREF 1.6V VO_MAX = 3.4V VREF VO_MIN = 1.3V GND 06239-047 DIRECT CONNECTION TO ANY "QUIET" AC GROUND (FOR EXAMPLE, GND, VCC, AND VEE). 1.3V Figure 45. VREF Pin Connection for AD8188 (Differs from AD8189) Figure 47. Output Compliance of Main Amplifier Channel and Ground Buffer The AD8189 The AD8189 uses on-chip feedback resistors to realize the gainof-two function. To provide low crosstalk and a high output impedance when disabled, each set of 500 feedback resistors is terminated by a dedicated reference buffer. A reference buffer is a high speed op amp configured as a unity-gain follower. The three reference buffers, one for each channel, share a single, high impedance input, the VREF pin (see Figure 46). VREF input bias current is typically less than 2 A. A0 5V 1x 5V 500 5V GBUF 0 VFO 500 OUT0 * The signal at the VREF pin appears at each output. Therefore, VREF should be tied to a well bypassed, low impedance source. Using superposition, it is shown that VOUT = 2 x VIN - VREF B0 VREF VF-1 5V GBUF 1 500 5V GBUF 2 500 OUT1 VF-2 06239-046 500 500 OUT2 To maximize the output dynamic range, the reference voltage should be chosen with care. For example, consider amplifying a 700 mV video signal with a sync pulse 300 mV below black level. If the user decides to set VREF at black level to preferentially run video signals on the faster NPN transistor path, the AD8189 allows a reference voltage as low as 1.3 V + 300 mV = 1.6 V. If the AD8189 is used, the sync pulse is amplified to 600 mV. Therefore, the lower limit on VREF becomes 1.3 V + 600 mV = 1.9 V. For routing RGB video, an advantageous configuration is to employ +3 V and -2 V supplies, in which case VREF can be tied to ground. If system considerations prevent running the multiplexer on split supplies, a false ground reference should be employed. A low impedance reference can be synthesized with a second operational amplifier. Alternately, a well bypassed resistor divider can be used. Refer to the Applications section for further explanation and more examples. 5V 10k 100k 0.022F 100 OP21 1F FROM 1992 ADI AMPLIFIER APPLICATIONS GUIDE GND 1F VREF * Figure 46. Conceptual Diagram of a Single Multiplexer Channel, G = 2 This configuration has a few implications for single-supply operation: * On the AD8189, VREF cannot be tied to the most negative analog supply, VEE. The limits on reference voltage are (see Figure 47): VEE + 1.3 V < VREF x VCC - 1.6 V 1.3 V < VREF, 3.4 V on 0 V/5 V supplies Figure 48. Synthesis of a False Ground Reference Rev. 0 | Page 15 of 24 06239-048 AD8188/AD8189 5V SECONDARY SUPPLIES AND SUPPLY BYPASSING The high current output transistors are given their own supply pins (Pin 15, Pin 17, Pin 19, and Pin 21) to reduce supply noise on-chip and to improve output isolation. Because these secondary, high current supply pins are not connected on-chip to the primary analog supplies, VCC/VEE (Pin 6, Pin 7, Pin 9, Pin 11, Pin 13, and Pin 24), some care should be taken to ensure that the supply bypass capacitors are connected to the correct pins. At a minimum, the primary supplies should be bypassed. Pin 6 and Pin 7 can be a convenient place to accomplish this. Stacked power and ground planes are a convenient way to bypass the high current supply pins (see Figure 51). IN0A DGND IN1A VREF IN2A VCC 0.1F 1F VEE IN2B VEE IN1B VEE 06239-050 10k VREF 10k 1F Figure 49. Alternate Method for Synthesis of a False Ground Reference AC-COUPLED INPUTS Using ac-coupled inputs presents an interesting challenge for video systems operating from a single 5 V supply. In NTSC and PAL video systems, 700 mV is the approximate difference between the maximum signal voltage and black level. It is assumed that sync has been stripped. However, given the two pathological cases shown in Figure 50, a dynamic range of twice the maximum signal swing is required if the inputs are to be ac-coupled. A possible solution is to use a dc restore circuit before the mux. WHITE LINE WITH BLACK PIXEL +700mV VREF BLACK LINE WITH WHITE PIXEL +5V VSIGNAL VINPUT = VREF + VSIGNAL VREF ~ VAVG VREF IS A DC VOLTAGE SET BY THE RESISTORS GND VREF VAVG VAVG 06239-049 CAP MUST BE LARGE ENOUGH TO ABSORB TRANSIENT CURRENTS WITH MINIMUM BOUNCE. 1 24 VCC OE SEL A/B VCC OUT0 VEE OUT1 VCC OUT2 VEE DVCC VCC 06239-051 2 23 3 22 4 21 5 20 6 MUX1 19 7 18 -700mV 8 MUX2 17 9 16 10 MUX3 15 11 14 IN0B 12 13 Figure 50. Pathological Case for Input Dynamic Range TOLERANCE TO CAPACITIVE LOAD Op amps are sensitive to reactive loads. A capacitive load at the output appears in parallel with an effective resistance (REFF) of REFF = (RL || rO) Figure 51. Detail of Primary and Secondary Supplies SPLIT-SUPPLY OPERATION Operating from split supplies (for example, [+3 V/-2 V] or 2.5 V) simplifies the selection of the VREF voltage and load resistor termination voltage. In this case, it is convenient to tie VREF to ground. The logic inputs are internally level-shifted to allow the digital supplies and logic inputs to operate from 0 V and 5 V when powering the analog circuits from split supplies. The maximum voltage difference between DVCC and VEE must not exceed 8 V (see Figure 52). DIGITAL SUPPLIES (+5V) DVCC 8V MAX (0V) DGND (-2.5V) VEE 06239-052 where RL is the discrete resistive load, and rO is the open loop output impedance, approximately 15 for these muxes. The load pole (fLOAD) at f LOAD = 1 2 R EFF C L can seriously degrade phase margin and, therefore, stability. The old workaround is to place a small series resistor directly at the output to isolate the load pole. While effective, this ruse also affects the dc and termination characteristics of a 75 system. The AD8188 and AD8189 are built with a variable compensation scheme that senses the output reactance and trades bandwidth for phase margin, ensuring faster settling and lower overshoot at higher capacitive loads. ANALOG SUPPLIES (+2.5V) VCC Figure 52. Split-Supply Operation Rev. 0 | Page 16 of 24 AD8188/AD8189 APPLICATIONS SINGLE-SUPPLY OPERATION The AD8188/AD8189 are targeted mainly for use in singlesupply 5 V systems. For operating on these supplies, both VEE and DGND should be tied to ground, and the control logic pins should be referenced to ground. Normally, the DVCC supply needs to be set to the same positive supply as the driving logic. For dc-coupled, single-supply operation, it is necessary to set an appropriate input dc level that is within the specified range of the amplifier. For the unity-gain AD8188, the output dc level is the same as the input, while for the gain-of-two AD8189, the VREF input can be biased to obtain an appropriate output dc level. Figure 53 shows a circuit that provides a gain-of-two and is dc-coupled. The video input signals must have a dc bias from their source of approximately 1.5 V. This same voltage is applied to VREF of the AD8189. The result is that when the video signal is at 1.5 V, the output is also at the same voltage. This is close to the lower dynamic range of both the input and the output. When the input goes most positive, which is 700 mV above the black level for a standard video signal, it reaches a value of 2.2 V, and there is enough headroom for the signal. On the output side, the magnitude of the signal changes by 1.4 V, making the maximum output voltage 2.2 V + 1.4 V = 3.6 V. This is just within the dynamic range of the output of the part. If the input is biased at 2.5 V dc, the input signal can potentially go 700 mV both above and below this point. The resulting 1.8 V and 2.2 V are within the input signal range for single 5 V operation. Because the part is unity-gain, the outputs follow the inputs, and there is adequate range at the output as well. When the AD8188 is operated from a single supply of 5 V and ground, ac-coupling is often useful. This is particularly true when the input signals are a typical RGB source from a PC. These signals go all the way to ground at the most negative, outside of the AD8188 input range, when its negative supply is ground. The closest that the input can go to ground is typically 1.3 V. There are several basic methods for ac-coupling the inputs. They all consist of a series capacitor followed by a circuit for setting the dc operating point of the input and then the AD8188 input. If a termination is provided, it should be located before the series coupling capacitor. The different circuits vary in the means used to establish the dc operating point after the coupling capacitor. A straightforward way to do this is to use a voltage divider for each input. However, because there are six inputs altogether, 12 resistors are required to set all of the dc operating points. This means many components in a small space, but the circuit has the advantage of having the lowest crosstalk among any of the inputs. This circuit is shown in Figure 54. A circuit that uses the minimum number of resistors can be designed. First, create a node, VMID, which serves as the bias voltage for all of the inputs. Then, a single resistor is used to connect from each input (inside the ac-coupling capacitor) and VMID (see Figure 55). AC-COUPLING AD8188 When a video signal is ac-coupled, the amount of dynamic range required to handle the signal can potentially be double the amount required for dc-coupled operation. For the unitygain AD8188, there is still enough dynamic range to handle an ac-coupled, standard video signal with 700 mV p-p amplitude. 3V TO 5V 5V DVCC VCC REDA GRNA 0.7V MAX 2.2V 1.5V BLUA 5V 3.48k 1.5V IN0A IN1A AD8189 x2 OUT0 RED 3.0V OUT1 1.4V MAX GRN 1.5V BLACK LEVEL TYPICAL OUTPUT LEVELS (ALL 3 OUTPUTS) IN2A VREF x2 BLACK TYPICAL INPUT LEVELS 1.5k LEVEL (ALL 6 OUTPUTS) REDB GRNB BLUB IN0B x2 IN1B IN2B OUT2 BLU Figure 53. AD8189 DC-Coupled (Bypassing and Logic Not Shown) Rev. 0 | Page 17 of 24 06239-055 DGND VEE SEL A/B OE AD8188/AD8189 5V 5V RGB SOURCE A R G B 75 5V 0.1F 4.99k 4.99k 5V 4.99k 5V 0.1F 4.99k IN2A 4.99k HI = A LO = B 4.99k IN2B SEL A/B VREF DGND VEE OE HI = ENABLE LO = DISABLE 06239-053 5V 0.1F 0.1F 10F 75 4.99k 4.99k IN0A DVCC VCC 75 0.1F 5V 4.99k AD8188 4.99k IN0B + - OUT0 IN1A IN1B + - OUT1 75 4.99k 0.1F TO A/D, ETC. RGB SOURCE B R G B 75 + - OUT2 75 5V 0.1F 4.99k 0.1F Figure 54. AD8188 AC-Coupling Using Separate Voltage Dividers 5V 0.1F RGB SOURCE A R G B 0.1F 75 VMID 4.99k VMID 4.99k 0.1F V MID 4.99k 0.1F V MID 4.99k B 5V 100 100 0.1F 10F 0.1F VMID HI = A LO = B IN2A IN2B SEL A/B VREF DGND VEE OE HI = ENABLE LO = DISABLE 06239-054 5V 0.1F 10F 75 VMID 4.99k IN0A 0.1F VMID 4.99k IN0B DVCC VCC AD8188 + - 75 OUT0 IN1A IN1B + - OUT1 75 0.1F TO A/D, ETC. RGB SOURCE B R G 75 + - OUT2 75 Figure 55. AD8188 AC-Coupling Using a Single VMID Reference The circuit in Figure 55 can increase the crosstalk between inputs, because each input signal creates a small signal on VMID due to its nonzero impedance. There are several means to minimize this. First, make the impedance of the VMID divider small. Small resistor values lower the dc resistance, and good bypassing to ground minimizes the ac impedance. It is also possible to use a voltage regulator or another system supply voltage if it is the correct value. It should be close to the midsupply voltage of the AD8188. The second technique for minimizing crosstalk is to use large resistor values to connect from the inputs to VMID. The major factor limiting the value of these resistors is offset caused by the input bias current (IB) that must flow through these resistors to the AD8188 inputs. The typical IB for an AD8188 input is 1.5 A, which causes an offset voltage of 1.5 mV per 1 k of resistance. Rev. 0 | Page 18 of 24 AD8188/AD8189 These two techniques can also be combined. Typically, crosstalk between the RGB signals from the same source is less objectionable than crosstalk between two different sources. The former can cause a color or luminance shift, but spatially, everything is coherent. However, the crosstalk signals from two uncorrelated sources can create ghost images that are far more objectionable. A technique for minimizing crosstalk between two different sources is to create two separate VMID circuits. Then, the inputs from each source can be connected to their own VMID node, minimizing crosstalk between sources. input capacitors of the AD8189. The input points of the AD8189 are switched to a 1.5 V reference by the ADG786, which works in the following manner: * * AD8189 When using the gain-of-two AD8189 in a simple ac-coupled application, there is a dynamic range limitation at the output caused by its higher gain. At the output, the gain-of-two produces a signal swing of 1.4 V, but the ac-coupling doubles this required amount to 2.8 V. The AD8189 outputs can only swing from 1.4 V to 3.6 V on a 5 V supply, so there are only 2.2 V of dynamic signal swing available at the output. A standard means for reducing the dynamic range requirements of an ac-coupled video signal is to use a dc restore. This circuit works to limit the dynamic range requirements by clamping the black level of the video signal to a fixed level at the input to the amplifier. This prevents the video content of the signal from varying the black level, as happens in a simple ac-coupled circuit. The SEL A/B signal selects the A or B input to the AD8189. It also selects the switch positions in the ADG786 such that the same selected inputs are connected to VREF when EN is low. During the horizontal interval, all of the RGB input signals are at a flat black level. A logic signal that is low during HSYNC is applied to the EN of the ADG786. This closes the switches and clamps the black level to 1.5 V. At all other times, the switches are off and the node at the inputs to the AD8189 floats. There are two considerations for sizing the input coupling capacitors. One is the time constant during the H-pulse clamping. The other is the droop associated with the capacitor discharge due to the input bias current of the AD8189. For the former, it is better to have a small capacitor, but for the latter, a larger capacitor is better. The on resistance of the ADG786 and the coupling capacitor form the time constant of the input clamp. The ADG786 on resistance is 5 maximum. With a 0.1 F capacitor, a time constant of 0.5 s is created. Thus, a sync pulse of greater than 2.5 s causes less than 1% error. This is not critical because the black level from successive lines is very close and the voltage changes little from line to line. A rough approximation of the horizontal line time for a graphics system is 30 s. This varies depending on the resolution and the vertical rate. The coupling capacitor needs to hold the voltage relatively constant during this time, while the input bias current of the AD8189 discharges it. The change in voltage is IB times the line time divided by the capacitance. With an IB of 2.5 A, a line time of 30 s, and a 0.1 F coupling capacitor, the amount of droop is 0.75 mV. This is roughly 0.1% of the full video amplitude and is not observable in the video display. 3V TO 5V 5V DVCC VCC DC RESTORE After ac-coupling a video signal, it is necessary to use a dc restore to establish where the black level is. Usually, this appears at the end of a video signal chain. This dc restore circuit needs to have the required accuracy for the system. It compensates for all the offsets of the preceding stages. Therefore, if a dc restore circuit is to be used only for dynamic range limiting, it does not require great dc accuracy. A dc restore circuit using the AD8189 is shown in Figure 56. Two separate sources of RGB video are ac-coupled to the 0.1 F 5V VDD ADG786 S1A D1 S1B REDA GRNA BLUA 0.1F 0.1F 0.1F IN0A IN1A AD8189 x2 OUT0 RED IN2A 5V 3.48k 1.5k 1.5V 10F + VREF D2 0.1F S3A S3B VSS LOGIC EN A0 A1 A2 06239-056 S2A S2B VREF VREF x2 OUT1 GRN D3 REDB GRNB BLUB 0.1F 0.1F 0.1F IN0B x2 IN1B IN2B DGND VEE SEL A/B OUT2 BLU GND HSYNC OE 2.4V MIN 0.8V MIN SEL A/B Figure 56. AD8189 AC-Coupled with DC Restore Rev. 0 | Page 19 of 24 AD8188/AD8189 HIGH SPEED DESIGN CONSIDERATIONS The AD8188/AD8189 are extremely high speed switching amplifiers for routing the highest resolution graphic signals. Extra care is required in the circuit design and layout to ensure that the full resolution of the video is realized. First, the board should have at least one layer of a solid ground plane. Long signal paths should be referenced to a ground plane as controlled-impedance traces. All bypass capacitors should be very close to the pins of the part with minimum extra circuit length in the path. It is also helpful to have a large VCC plane on a circuit board layer that is closely spaced to the ground plane. This creates a low inductance interplane capacitance, which is very helpful in supplying the fast transient currents that the part demands during high resolution signal transitions. Rev. 0 | Page 20 of 24 AD8188/AD8189 EVALUATION BOARD An evaluation board has been designed and is offered for running the AD8188/AD8189 on a single supply. The inputs and outputs are ac-coupled and terminated with 75 resistors. For the AD8189, a potentiometer is provided to allow setting VREF at any value between VCC and ground. The logic control signals can be statically set by adding or removing a jumper. If a fast signal is required to drive the logic pins, an SMA connector can be used to deliver the signal, and a place for a termination resistor is provided. Figure 57. Component Side Board Layout Figure 58. Circuit Side Board Layout Rev. 0 | Page 21 of 24 06239-058 06239-057 AD8188/AD8189 Figure 59. Component Side Silkscreen Figure 60. Circuit Side Silkscreen Rev. 0 | Page 22 of 24 06239-060 06239-059 SCHEMATICS IN0A R4 75 C1 0.1F VREF VREF VCC VCC R23 1k OE AGND VREF 1 AGND AGND R15 4.99k R22 4.99k GND1 GND2 GND3 GND4 AGND AGND C10 0.1F C15 10F C4 0.1F R19* TBD W1 AGND VCC OE SEL A/B VCC OUT0 VEE OUT1 VCC OUT2 VEE DVCC VCC 13 14 15 16 17 18 19 20 21 22 23 24 VCC IN1A R5 75 AGND VCC AGND R1 VREF VCC R24 1k VREF C24 0.1F IN0A DGND IN1A VREF IN2A VCC VEE IN2B VEE IN1B VEE IN0B AGND C7 0.1F VCC 2 AGND C14 0.01F R20* TBD AGND R9 75 DUT CW AGND AGND C13 10F SEL A/B W2 AGND AGND C18 0.1F OUT0 R10* TBD AGND R11 75 AGND VCC R12* TBD C17 0.1F C16 10F AGND C19 0.1F OUT1 AGND AGND AGND AGND 4 5 6 3 R16 4.99k VCC IN2A AGND C3 0.1F 7 8 9 10 11 12 R6 75 C5 0.1F AGND VREF R17 4.99k C6 0.1F R18 4.99k AGND C8 0.1F VREF R21 4.99k VCC C12 0.1F AGND C9 0.1F VREF 06239-061 Figure 61. Single-Supply Evaluation Board AGND Rev. 0 | Page 23 of 24 IN2B AGND R7 75 AGND AD8188/ AD8189 VCC IN1B AGND R3 75 AGND AGND R13 75 R14* TBD AGND C20 0.1F OUT2 AGND IN0B AGND R8 75 AGND AD8188/AD8189 * R10, R12, R14, R19, AND R20 NOT INSTALLED ON EVALUATION BOARD FOR TEST PURPOSES. R1 IS NOT USED FOR AD8188. AD8188/AD8189 OUTLINE DIMENSIONS 7.90 7.80 7.70 24 13 4.50 4.40 4.30 1 12 6.40 BSC PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 0.10 COPLANARITY 1.20 MAX 8 0 0.75 0.60 0.45 SEATING PLANE 0.20 0.09 COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 62. 24-Lead Thin Shrink Small Outline Package [TSSOP] [RU-24] Dimensions shown in millimeters ORDERING GUIDE Model AD8188ARUZ 1 AD8188ARUZ-RL1 AD8188ARUZ-R71 AD8189ARUZ1 AD8189ARUZ-RL1 AD8189ARUZ-R71 AD8188Z-EVALZ1 AD8189Z-EVALZ1 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 24-Lead Thin Shrink Small Outline Package [TSSOP] 24-Lead Thin Shrink Small Outline Package [TSSOP], 13" Reel 24-Lead Thin Shrink Small Outline Package [TSSOP], 7" Reel 24-Lead Thin Shrink Small Outline Package [TSSOP] 24-Lead Thin Shrink Small Outline Package [TSSOP], 13" Reel 24-Lead Thin Shrink Small Outline Package [TSSOP], 7" Reel Evaluation Board Evaluation Board Package Option RU-24 RU-24 RU-24 RU-24 RU-24 RU-24 Z = Pb-free part. (c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06239-0-10/06(0) Rev. 0 | Page 24 of 24 |
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