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Data Sheet
OXU140CM USB On-The-Go Full Speed Host, High Speed Peripheral with Multi-Storage Interface
Features
SinglechipUSBOTGfullspeedhostandhighspeedperipheral controller Reducessystemcostandboardspace Minimizessystemdesigncomplexityandpower SimultaneousUSBhost,peripheral,and CEATA/MMC/SDinterfaceoperation USBperipheraltoCEATA/MMC/SDbridging CompatiblewiththeUSB2.0andOTGspecifications CEATA1.1commandsupportwithbuiltinflowcontrol MMC4.1compatible Configurable1/4/8bitdatabusatupto48MHzclock frequency Dualvoltage(3.3Vand1.8V)I/Osupport Integratedsmartclockcontrolforreducedpower consumption 3.3Vpowersupply,flexibleI/Ovoltageof1.65Vto3.6V (LVCMOS/TTL)tointerfacetoawiderangeofMCUs Lowpowersleepmodetominimizepowerconsumptionwhen notinuse Integratedonchipchargepump,supportsupto100mAof current,enablessupportforbroadrangeofUSBdevices Packaging 8x8mmBGA,100ball,RoHScompliant 14x14mmLQFP,128pin,RoHScompliant 16bitmemorymappedinterfacecangluelesslyinterfacetomost popularmicroprocessorsandDSPs Fastmicroprocessoraccesscycleanddouble/multibuffering supportforallfourtypesofUSBtransfers TwoDMA(slave)channelsupportforperipheralcontrollerand CEATA/MMC/SDcontrollerlowersCPUutilization IntegratedPLLsupportsexternalcrystalorcrystaloscillatorsof 12MHzor30MHz,forsystemflexibility
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OXU140CM Data Sheet
Oxford Semiconductor, Inc.
16KbytesofonchipSRAM,optimizedbuffersizefor performanceandcost USBperipheralallowsupto8bidirectionalendpointsand transferstoenablesupportformultifunctionsystems HostNegotiationProtocolandSessionRequestProtocol implementedinhardware Transactionschedulingandtransferlevelprotocolimplemented inhardware(includingdatatoggle,retry,andbandwidth management)forhighperformance
Device Overview
TheOxfordSemiconductorOXU140CMisasinglechipUSBOnTheGo (OTG)controllerthatincorporatesafullspeedhost,ahighspeed peripheralcontroller,andamultistorageinterfacethatsupportsthe followingtechnologies: Consumerelectronicsadvancedtechnologyattachment (CEATA)HDDs MultiMediaCard(MMC) SecureDigital(SD) Thehighspeedperipheralportoffershighdataratetransferstoand fromhostPCs.Thisisessentialfordevicessuchassmartphones, portablemediaplayers,caraudio/navigationunits,andpersonalstorage devices,wheremediatransfertimesgreatlyimpacttheuserexperience. Thefullspeedhostportenablestheconnectionofawiderangeof devices,suchasflashdrives,keyboards,mice,anddigitalstillcameras. TheOXU140CMlowpowerdesignisidealforextendingthebatterylife inmobileapplications. ThemultistorageinterfaceprovidesgluelesssupportforCEATAhard drives.Thisnewclassofdrivesisdesignedforlowerpincount,better powerutilization,andamoreefficientcommandprotocolthanexisting harddrives,makingitidealforportableapplications.Theinterfacealso supportsMMCandSDflashmemorydevices,providingadditional productflexibilityinmemorycapacityexpansion.TheOXU140CM implementsfastbridgingbetweentheUSBperipheralportandthe multistorageinterface,improvingdatatransferratesandminimizing CPUutilization. TheOXU140CMallowsforsimultaneoushostandperipheraloperation. Theportscanbeconfiguredinoneoftwomodes: OneOTGportandonefullspeedhostport Onehighspeedperipheralportandtwofullspeedhostports Themultistorageinterfacecanbeusedinconjunctionwitheithermode.
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OXU140CM Data Sheet
TheOXU140CMissupportedwithUSBdevicedriversandtheOxford SemiconductorUSBLinkTMproductsuite.TheUSBLinkhost,peripheral, andOTGstackshavebeenportedtoawidevarietyofrealtimeoperating systemincludingVxWorks(R),ThreadX(R),andNucleus(R). Inaddition,OxfordSemiconductoralsomakesavailablelowlevel controllerdriversforothernativeUSBstackssuchasthoseincludedwith Windows(R)CEandLinux(R)2.6.x. Figure1showsablockdiagramoftheOXU140CM.
Figure 1 OXU140CM Architectural Diagram
OSC1 OSC2
Clock/ Osc Pads and Clk Div
ENVREG Voltage Regulator VBus Control Circuit and Vbus Charge Pump VREGOUT VBUS /EXVBO
ACK[1:0] REQ[1:0] DMA Interface System Configuration & Control Registers
HNP/SRP Logic /RESET /CS /WR /RD INT GPIO A[14:1] D[15:0] USB Host Control Logic Host SIE & Root Hub Memory Blocks P Interface OTG XCVR USB Peripheral Controller USB Peripheral Controller Registers
ID
P_DM P_DP
DM1 DP1
TEST
Tes t Control
USB Host Controller Registers
USB Xcvr
DM2 DP2 /PO /OC M_CLK M_CMD M_DATA [7:0]
CE-ATA/ MMC/SD Controller
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OXU140CM Data Sheet
Oxford Semiconductor, Inc.
Development Support
TheOXU140CMproductsuiteincludestheUSBcontrolleraswellasthe protocolstacksandthedriversoftwarethatenableawidevarietyofUSB applications.Thisuniqueabilitytodeliveratotalhardwareandsoftware solutionsetsOxfordSemiconductorapartfromothersemiconductor companiesandbenefitscustomersby: Shorteningtimetomarket Reducingrisk Offeringasinglesourceforhardware&software,thereby reducingthenumberofsuppliersthecustomerhastodealwith OxfordSemiconductorisaMicrosoft(R)Windows(R)EmbeddedPartner andhasdevelopedhostandperipheralcontrollerdriversforWindows CE5.0.SimilarsoftwaresupportisalsoavailableforLinux(R)2.6.x. ForcustomersusinganRTOSsuchasVxWorks(R),ThreadX(R),Nucleus(R), OSE,LynxOS(R),andAMXTM,amongothers,OxfordSemiconductor offersitsUSBLinkhost,peripheralandOnTheGosoftwaresolutions. TheUSBLinkProductSuiteisamodularizedapproachtoprovidingUSB connectivityforawidevarietyofembeddedproducts.Duetoitsflexible architectureandbroadbasedsupportforUSBhost,peripheralandOTG applications,OxfordSemiconductorcantailortheUSBLinksoftware deliverablestomeeteachcustomer'sUSBrequirements. TheUSBLinksolutionsareconfigurableandcansupportsystemswith: Bigorlittleendianprocessors DMAornonDMAUSBcontrollers AwidevarietyofUSBcontrollers,includingtheOXU140CM Complextosimpleoperatingsystems OxfordSemiconductorhasovereightyearsofexperiencedeveloping embeddedUSBtechnology.ItsUSBLinksoftwarehasbeenportedto twentydifferentoperatingsystemsandawidevarietyofembedded architectures.USBLinkisshippinginmanymillionsofunits.
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OXU140CM Data Sheet
Electrical Characteristics
Tables1to11detailtherequiredoperatingconditionsforthedeviceand theDCandACelectricalcharacteristics.
Table 1 Absolute Maximum Device Ratings Symbol VDD3.3 VDD1.8 VDDW VI TS Parameter 3.3 V power supply 1.8 V power supply 1.8 V to 3.3 V wide-range I/O power supply DC input voltage Storage temperature Min -0.3 -0.3 -0.3 -0.3 -40 Max 4.0 2.16 4.0 4.0 +150 Unit V V V V C
Note:
Permanentdevicedamagemayoccurifabsolutemaximumratingsareexceeded.Functionalopera tionshouldberestrictedtothenormaloperatingconditionsspecifiedinthefollowingsection.Expo suretoabsolutemaximumratingconditionsforextendedperiodsmayaffectdevicereliability.
Table 2 Recommended Operating Conditions Symbol VDD3.3 VDD1.8 VDDW VI3.3 VIW TO Parameter 3.3 V power supply 1.8 V power supply 1.8 to 3.3 V wide-range I/O power supply DC input voltage of 3.3 V pins DC input voltage of wide-range pins Operating temperature Min 2.97 1.62 1.62 0 0 -40 Max 3.63 1.98 3.63 3.6 1.1*VDDW +85 Unit V V V V V C
Table 3 DC Characteristics, Full-Speed USB I/O Signals: DPN, DMN Symbol VDI VCM VOL VOH VCRS CIN Parameter Differential input sensitivity Differential comm. mode range Static output low Static output high Output signal crossover Input capacitance Condition |VI(DPN) -- VI(DMN)| (where N = 1 or 2) Min 0.2 0.8 0.0 2.8 1.3 2.5 0.3 3.6 2.0 20 Max Unit V V V V V pF
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OXU140CM Data Sheet
Oxford Semiconductor, Inc.
Table 4 DC Characteristics, High-Speed USB I/O Signals: DPP and DMP Only Symbol VHSDIFF VHSCM VHSSQ VHSIO VHSOL VHSOH VCHIRPK Parameter High-speed differential input sensitivity High-speed data signaling common mode range High-speed squelch detection threshold High-speed idle output voltage (differential) High-speed low-level output voltage (differential) High-speed high-level output voltage (differential) Chirp-K output voltage (differential) Squelch detected No squelch detected 150 -10 -10 -360 -900 10 10 400 -500 Condition |VI(DPP) -- VI(DMP)| Min 300 -50 500 100 Max Unit mV mV mV mV mV mV mV mV
Table 5 DC Characteristics, Logic Signals Symbol VOL VOH VIL VIH CIN COUT CBI IIN
Note:
Parameter Low-level output voltage High-level output voltage Low-level input voltage High-level input voltage Input capacitance Output capacitance Bi-directional capacitance Input leakage current VDDW = 3.3 V VDDW = 1.8 V VDDW = 3.3 V VDDW = 1.8 V VDDW = 3.3 V VDDW = 1.8 V
Condition
Min 2.4
0.75*VDDW
Max 0.4
Unit V V V
0.8 0.3*VDDW 2.0 0.7*VDDW 2.2 (typical) 2.2 (typical) 2.2 (typical)
V V V V pF pF pF A
No pull up or pull down
-10
10
Thecapacitanceslistedabovedonotincludepadcapacitanceandpackagecapacitance. Onecanestimatepincapacitancebyaddingpadcapacitanceofabout0.5pF;andthe packagecapacitance,whichisabout0.86pFmaxforQFPand0.42pFmaxforBGA.
Table 6 DC Characteristics, ID Resistance Symbol RB-PLUG-ID RA-PLUG-ID Parameter Resistance to ground on mini-B plug Resistance to ground on mini-A plug Condition Min 100 K 10 Max Unit
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OXU140CM Data Sheet
Table 7 DC Characteristics, Regulator Symbol RVout RIdrive Rtst
Note:
Parameter Output voltage Driving current Start-up time when enabled
Condition Driving current <= 100 mA VDD3.3A = 3.3 V Output voltage = 1.8 V VDD3.3A = 3.3 V RVout = 1.62 V (90%)
Min
Max 150
Unit V mA s
1.8 (typical)
25 (typical)
TheVDD3.3ApinthatcorrespondstotheregulatorsupplyisQFPpin106andBGApinB7.
Table 8 DC Characteristics, Charge Pump Symbol CVout VDD1.8 VDDW
Note:
Parameter Output voltage Driving current Start-up time when enabled
Condition Driving current <= 100 mA VCPSUPPLY = 3.3 V Output voltage = 5 V VCPSUPPLY = 3.3 V RVout = 4.5 V (90%)
Min 4.75
Max 5.07 100
Unit V mA s
400 (typical)
ThechargepumpsupplyVCPSUPPLYsuppliestheexternalcomponentsofthecharge pumpcircuit.
Table 9 AC Characteristics, High-Speed DPP and DMP Driver Characteristics Symbol tHSR tHSF RDRV Parameter High-speed differential rise time High-speed differential fall time Driver output impedance Equivalent resistance used as internal chip Condition Min 500 500 40.5 49.5 Max Unit ps ps
Table 10 AC Characteristics, Full-Speed DP1, DP2, DM1, DM2 Driver Characteristics Symbol tFR tFF tFRFM ZDRV Rise time Fall time TR/TF matching Driver output resistance Steady state drive with external 33 series resistor Parameter CL = 50 pF CL = 50 pF Condition Min 4 4 90 3 Max 20 20 110 9 Unit ns ns %
Table 11 AC Characteristics, Low-Speed DP1, DP2, DM1, DM2 Driver Characteristics Symbol tLR tLF tFRFM Rise time Fall time TR/TF matching Parameter Condition CL = 200 - 600 pF CL = 200 - 600 pF Min 75 75 80 Max 300 300 125 Unit ns ns %
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OXU140CM Data Sheet
Oxford Semiconductor, Inc.
Power Consumption
Table12givestypicalpowerconsumptionfiguresfortheOXU140CM.
Table 12 OXU140CM Power Consumption Condition Host operational current Peripheral operational current ENVREG = 1 High-speed, ENVREG = 1 Full-speed, ENVREG = 1 Host suspend state current Peripheral suspend state current MMC host operational current MMC host suspend current Power save state current ENVREG = 1 ENVREG = 1 ENVREG = 1 ENVREG = 1 ENVREG = 1 Min Max 30 75 50 150 (typical) 400 (typical) 45 150 (typical) 150 (typical) Unit mA mA mA A A mA A A
Theabovemeasurementsareattypicalprocesscornerandroom temperatureanddonotaccountforprocessandtemperaturevariations. Peripheraloperationalcurrentismeasuredwitha5mcablewith maximumswitchingandBULKOUTtransfersat400Mbpswith92.6% busutilizationduringonemicroframe.Theactualaveragecurrentin customerapplicationswillbelower. MMChostoperationcurrentismeasuredwith8bitat48MHzwriting 55AApatterntoanMMC4.1cardat15Mbpsthroughput.Theactual averageoperationalcurrentwillvarybaseonthedatapatternand throughputratessupportedbytheattacheddevice. ENVREG=1enablestheinternalvoltageregulator.
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OXU140CM Data Sheet
Pin Layout
TheOXU140CMissuppliedasa128pinLQFPpackageandasa100ball BGApackage.Figure2showsthechiplayoutofthe128pinLQFP package.
Figure 2 OXU140CM 128-Pin LQFP Package (Top View)
/CE3P3V_EN /CEMOT_EN PD_PMOS CLKCFG /EXVBO /OC XMODE
VDD3.3A
VDD3.3A
VDD3.3A
VOUT
VBUS
VDD1.8
VDD1.8
VDD3.3
VDD1.8
VBP
VSSA
VSSA
VSSA
EXT
DM1
DP1
/PO
VSS
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VSS DP2 NC NC DM2 VDD3.3 /CE1P8V_EN ENVREG VREGOUT VDD3.3A VSSA VSS VDD1.8 VDDW NC /RESET TEST GPIO DRQ0 ACK0 GPXA DRQ1 ACK1 GPXB VDDW INT D0 D1 D2 D3 VDD1.8 VSS 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 1 D4 2 D5 3 D6 4 D7 5 VDD1.8 6 VDDW 7 D8 8 D9 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 /WR /RD CECMD A1 A2 A3 A4 CEDAT0 CEDAT1 CEDAT2 CEDAT3 CEDAT4 VDD1.8 D10 D11 D12 D13 D14 D15 CECLK VDDW VSS VDDCE VSS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 OSC1 OSC2 VDD3.3A VSSA RREF NC DMP NC DPP NC VDD3.3A VSSA VSS VDD1.8 A5 /CS A12 A13 A14 A11 A10 A9 A8 A7 A6 VDDW VDDCE CEDAT7 CEDAT6 CEDAT5 VSS VDDCE
OXU140CM-LQBG
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VSS
NC
NC
NC
NC
NC
ID
9
OXU140CM Data Sheet
Oxford Semiconductor, Inc.
Table13liststheLQFPpinallocations.
Table 13 OXU140CM 128-Pin LQFP Pin Allocations (Sheet 1 of 3) Pin No. Pins 16 Type(1) Name Description
Processor Interface (39 pins) 1, 2, 3, 4, 7, 8, 9, 10, 12, 13, 14, 15, 123, 124, 125, 126 18, 19, 20, 21, 40, 41, 42, 43, 44, 45, 46, 47, 48, 50 16 17 49 122 MSBCT D0 - D15 16-bit data bus
14
MSI
A1 - A14
Address bus for direct address space
1 1 1 1
MSIU MSIU MSIU MOCT
/WR /RD /CS /INT
Write strobe Read strobe Chip select Interrupt to the MCU.This pin can be software configured as a driven output or open drain. Open drain is the default Hardware reset DMA request outputs to support two channels DMA acknowledge General purpose I/O Analog +3.3 V power Analog ground Digital +3.3 V power 1.8 V core power. VREGOUT may be used for the supplies Wide-range I/O +1.65 V to +3.6 V for the processor interface Wide-range I/O +1.65 V to +3.6 V for the media port Digital/wide-range I/O ground
112 118, 115 119, 116 114, 117, 120 54, 62, 90, 91, 94, 106 53, 61, 88, 89, 95, 107 75, 102 5, 24, 51, 66, 76, 85, 109, 127 6. 22, 39, 110, 121 23, 33, 38 11, 28, 34, 52, 65, 84, 97, 108, 128 58, 56
1 2 2 3 6 6 2 8 5 3 9
MSIVI MOCT MSI MSBC
/RESET DRQ1, DRQ0 ACK1, ACK0 GPIO, GPXA, GPXB VDD3.3A VSSA VDD3.3 VDD1.8 VDDW VDDCE VSS
General Purpose I/O (3 pins) Power & Ground (39 pins)
USB Interface (13 pins) 2 B DMP, DPP Data lines for USB peripheral port, which may serve as an OTG port in combination with host port 1. If not used, these two pins should be left floating Data lines for Host Port 1, which may serve as a USB host or an OTG port in combination with the peripheral port. If not used, these two pins should be left floating
73, 68
2
B
DM1, DP1
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OXU140CM Data Sheet
Table 13 OXU140CM 128-Pin LQFP Pin Allocations (Sheet 2 of 3) Pin 101, 98 60 93 No. Pins 2 1 1 Type(1) B B 5I DM2, DP2 RREF VBUS Name Description Data lines for Host Port 2, a dedicated USB host port. If not used, these two pins should be left floating Connect external reference resistor (12 K +/- 1%) to VSSA VBUS input used by the voltage comparators of the OTG port for connection. This pin should be left floating in a host-only application VBUS pulsing control. This pin is used only when Port 1 is an OTG port for a B-DEVICE. Turn on/off the external VBUS (5 V) for OTG operation (1:VBUS off, 0: VBUS on) when using the external charge pump Over current condition indicator for powered host ports Connected to the ID pin of the mini-AB connector for OTG applications. With the help of an internal pull-up resistor, this pin determines the chip's responsibility in an OTG application (0: A-device, 1:B-device) Turn on/off gang power for all host ports The state of this pin is used to indicate whether a 12 MHz or a 30 MHz crystal/oscillator is being used. CLKCFG -- Frequency 0--12-MHz crystal; 12-MHz 3.3 V oscillator input on OSC1 1--30-MHz crystal; 30-MHz 3.3 V oscillator input on OSC1 A 12-MHz or 30-MHz passive crystal should be connected across the two pins. Optionally, a 12 MHz or 30-MHz oscillator can be connected to OSC1 while keeping OSC2 unconnected SD/MMC/CE-ATA CLK output (0-48 MHz) SD/MMC/CE-ATA CMD SD/MMC/CE-ATA 1,4 or 8-bit data bus On/off control for MMC 3.3 V interface power On/off control for MMC 1.8 V interface power On/off control for HDD motor power Internal charge pump output for P-MOSFET (optional switch on the VOUT) Internal charge pump output for N-MOSFET Internal charge pump output voltage feedback pin
79 78
1 1
O O
VBP /EXVBO
77 81
1 1
IU IU
/OC ID
80 82
1 1
O I
/PO CLKCFG
Clock Interface (3 pins)
64 63
1 1
I O
OSC1 OSC2
MMC/CE-ATA (13 pins) 25 26 37, 36, 35, 32, 31, 30, 29, 27 67 103 74 87 92 86 1 1 8 1 1 1 1 1 1 MO MBUS MBUS O O O O O I CECLK CECMD CEDAT[7:0] /CE3P3V_EN /CE1P8V_EN /CEMOT_EN PD_PMOS EXT VOUT
Internal VBUS Charge Pump (3 pins)
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OXU140CM Data Sheet
Oxford Semiconductor, Inc.
Table 13 OXU140CM 128-Pin LQFP Pin Allocations (Sheet 3 of 3) Pin No. Pins 1 1 I O Type(1) Name Description
Internal Voltage Regulator (2 pins) 104 105 ENVREG VREGOUT Enables the internal voltage regulator if asserted. If not used, this pin should be tied to VSS Internal voltage regulator output of 1.8 V. If enabled, this output should be connected to the VDD1.8 supplies of the chip. If the regulator is disabled, this pin should be treated as another VDD1.8 supply input to the chip Xcrv test mode. This pin should be grounded for normal operation Factory test mode. This pin should be grounded or left floating (has an internal pull-down) for normal operation No connection. These pins should be left floating
Test (2 pins) 83 113 1 1 I ID XMODE TEST
Miscellaneous (11 pins) 55, 57, 59, 69, 70, 71 72, 96, 99, 100,111
NotetoTable13:
1
NC
1
Typekey:formatis[(L)(W_)X(Y)(_Z(T))]wherethefollowingconventionsapply:
L--Logic Level M
(2)
W--Tolerance 5 5V 3.3 V I O B
2 3
X--Type Input Output Bidirectional U D
Y--Pull Pull up Pull down None
Z--Drive C
(3)
T--Tristate T Tristate Normal
Multi-voltage: 3.3 V CMOS 2.5 V CMOS 1.8 V CMOS Schmitt Trigger
S
Programto3.3V,2.5V,or1.8VbysettingtheVIOvoltagelevel. Programto2mA,4mA,6mA,8mA,10mA,12mA,14mA,or16mA.
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OXU140CM Data Sheet
Figure3showsthechiplayoutofthe100ballBGApackage.
Figure 3 OXU140CM 100-Ball BGA Package (Top View)
10 9 8
7 6 5 4 3 2 1
DP2
VSSA
VBUS
VSSA
ID
/OC
/EXVBO
/CPE3P3V_EN
V SSA
OSC 2
DM2
/CPE1P8V_EN
VDD3.3A
VOUT
CLKCFG
/PO
/CEMOT_EN
DP 1
DP P
V DD3.3A
VREGOUT
ENVREG
VDD3.3A
EXT
XMODE
VBP
DM 1
DM P
V DD3.3A
OSC 1
GPIO
VDD3.3A
VSSA
V DD3.3
PD_PMOS
V DD1.8
V DD1.8
V SSA
A5
R REF
TEST
NC (GP12)
/RESET
V DD3.3
VSS
VSS
A 14
A 12
A 13
/CS
GPXA
DRQ0
DRQ 1
V DDW
VDDW
VSS
V DDCE
A9
A 11
A 10
ACK 0
ACK1
GPX B
/INT
D12
V DD1.8
CEDAT2
A6
A7
A8
D1
D0
D3
D10
D 13
/WR
A1
CEDAT 0
CEDAT 7
CEDAT 6
D5
D2
D8
D11
D 14
A2
A4
CECLK
CEDAT 1
CEDAT 4
D7
D4
D6
D9
D 15
/RD
A3
CECMD
CEDAT 3
CEDAT 5
A
B
C
D
E
F
G
H
J
K
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OXU140CM Data Sheet
Oxford Semiconductor, Inc.
Table 14liststheBGApinallocations. Table 14 OXU140CM 100-Ball BGA Pin Allocations (Sheet 1 of 3) Pin No. Pins 16 Type(1) Name Description
Processor Interface (39 pins) B3, A3, B2, C3, B1, A2, C1, A1, C2, D1, D3, D2, E4, E3, E2, E1 G3, F2, G1, G2, J7, H4, J4, K4, H5, K5, J5, H6, J6, G6 F3 F1 K6 D4 MSBCT D0 - D15 16-bit data bus
14
MSID
A1 - A14
Address bus for direct address space
1 1 1 1
MSIU MSIU MSIU MOCT
/WR /RD /CS /INT
Write strobe Read strobe Chip select Interrupt to the MCU.This pin can be software configured as a driven output or open drain. Open drain is the default Hardware reset DMA request outputs to support two channels DMA acknowledge General purpose I/O Analog +3.3 V power Analog ground Digital +3.3 V power 1.8 V core power. VREGOUT may be used for the supplies Wide-range I/O +1.65 V to +3.6 V for the processor interface Wide-range I/O +1.65 V to +3.6 V for the media port Digital/wide-range I/O ground Data lines for USB peripheral port, which may serve as an OTG port in combination with host port 1. If not used, these two pins should be left floating Data lines for Host Port 1, which may serve as a USB host or an OTG port in combination with the peripheral port. If not used, these two pins should be left floating
C6 C5, B5 B4, A4 A7, A5, C4 B7, C8, C9, J8, K9 B10, C7, D10, H7, J10 D6, D7 F4, F7, G7 D5. E5 G5 E6, F5, F6 H8 J9
1 2 2 3 5 5 2 3 2 1 3 2
MSIU MOCT MSI MSBC
/RESET DRQ1, DRQ0 ACK1, ACK0 GPIO, GPXA, GPXB VDD3.3A VSSA VDD3.3 VDD1.8 VDDW VDDCE VSS
General Purpose I/O (3 pins) Power & Ground (21 pins)
USB Interface (13 pins) B DMP, DPP
G8, H9
2
B
DM1, DP1
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OXU140CM Data Sheet
Table 14 OXU140CM 100-Ball BGA Pin Allocations (Sheet 2 of 3) Pin A9, A10 K7 C10 No. Pins 2 1 1 Type(1) B B 5I DM2, DP2 RREF VBUS Name Description Data lines for Host Port 2, a dedicated USB host port. If not used, these two pins should be left floating Connect external reference resistor (12 K +/- 1%) to VSSA VBUS input used by the voltage comparators of the OTG port for connection. This pin should be left floating in a host-only application VBUS pulsing control. This pin is used only when Port 1 is an OTG port for a B-DEVICE. Turn on/off the external VBUS (5 V) for OTG operation (1:VBUS off, 0: VBUS on) when using the external charge pump Over current condition indicator for powered host ports Connected to the ID pin of the mini-AB connector for OTG applications. With the help of an internal pull-up resistor, this pin determines the chip's responsibility in an OTG application (0: A-device, 1:B-device) Turn on/off gang power for all host ports The state of this pin is used to indicate whether a 12 MHz or a 30 MHz crystal/oscillator is being used. CLKCFG -- Frequency 0--12-MHz crystal; 12-MHz 3.3 V oscillator input on OSC1 1--30-MHz crystal; 30-MHz 3.3 V oscillator input on OSC1 A 12-MHz or 30-MHz passive crystal should be connected across the two pins. Optionally, a 12 MHz or 30-MHz oscillator can be connected to OSC1 while keeping OSC2 unconnected SD/MMC/CE-ATA 1,4 or 8-bit data bus On/off control for MMC 3.3 V interface power On/off control for MMC 1.8 V interface power On/off control for HDD motor power SD/MMC/CE-ATA CLK output (0-48 MHz) SD/MMC/CE-ATA CMD Internal charge pump output for P-MOSFET (optional switch on the VOUT) Internal charge pump output for N-MOSFET Internal charge pump output voltage feedback pin
F8 G10
1 1
O O
VBP /EXVBO
F10 E10
1 1
P5IU IU
/OC ID
F9 E9
1 1
O I
/PO CLKCFG
Clock Interface (3 pins)
K8 K10
1 1
I O
OSC1 OSC2
MMC/CE-ATA (13 pins) J3, K3, K1, K2, J1, G4, J2, H3 H10 B9 G9 H2 H1 E7 D8 D9 8 1 1 1 1 1 1 1 1 MBUS O O O MO MBUS O O I CEDAT[7:0] /CE3P3V_EN /CE1P8V_EN /CEMOT_EN CECLK CECMD PD_PMOS EXT VOUT
Internal VBUS Charge Pump (3 pins)
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OXU140CM Data Sheet
Oxford Semiconductor, Inc.
Table 14 OXU140CM 100-Ball BGA Pin Allocations (Sheet 3 of 3) Pin No. Pins 1 1 I O Type(1) Name Description
Internal Voltage Regulator (2 pins) B8 A8 ENVREG VREGOUT Enables the internal voltage regulator if asserted. If not used, this pin should be tied to VSS Internal voltage regulator output of 1.8 V. If enabled, this output should be connected to the VDD1.8 supplies of the chip. If the regulator is disabled, this pin should be treated as another VDD1.8 supply input to the chip Xcrv test mode. This pin should be grounded for normal operation Factory test mode. This pin should be grounded or left floating (has an internal pull-down) for normal operation No connection. These pins should be left floating
Test (2 pins) E8 A6 1 1 I ID XMODE TEST
Miscellaneous (1 pin) B6
NotetoTable14:
1
1
NC
Typekey:formatis[(L)(W_)X(Y)(_Z(T))]wherethefollowingconventionsapply:
L--Logic Level M
(2)
W--Tolerance 5 5V 3.3 V I O B
2 3
X--Type Input Output Bidirectional U D
Y--Pull Pull up Pull down None
Z--Drive C
(3)
T--Tristate T Tristate Normal
Multi-voltage: 3.3 V CMOS 2.5 V CMOS 1.8 V CMOS Schmitt Trigger
S
Programto3.3V,2.5V,or1.8VbysettingtheVIOvoltagelevel. Programto2mA,4mA,6mA,8mA,10mA,12mA,14mA,or16mA.
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Oxford Semiconductor, Inc.
OXU140CM Data Sheet
Package Layout
Figure4showsthepackagelayoutforthe128pinLQFPpackage.
Figure 4 128-Pin LQFP Package
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17
OXU140CM Data Sheet
Oxford Semiconductor, Inc.
Figure5showsthelayoutforthe100ballTFBGA.
Figure 5 100-Ball TFBGA Package
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Oxford Semiconductor, Inc.
OXU140CM Data Sheet
Figure 5 100-Ball TFBGA Package (continued)
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OXU140CM Data Sheet
Oxford Semiconductor, Inc.
Ordering Information
ThefollowingconventionsareusedtoidentifyOxfordSemiconductor products:
OXU140CM - LQBG Green (RoHS compliant) Revision Package Type: LQ Part Number 128-Pin LQFP
OXU140CM - PBBG Green (RoHS compliant) Revision Package Type: PB Part Number 100-Ball TF-BGA
Contacting Oxford Semiconductor Revision Information
SeetheOxfordSemiconductorwebsite(http://www.oxsemi.com)for furtherdetailsaboutOxfordSemiconductordevices,oremail sales@oxsemi.com.
Table15documentstherevisionsofthisguide.
Table 15 Revision Information Revision Jul 06 First publication Modification
USBLinkisatrademarkofOxfordSemiconductor,Inc. VxWorksisaregisteredtrademarkofWindRiverSystems. ThreadXisaregisteredtrademarkofExpressLogic,Inc. NucleusisaregisteredtrademarkofMentorGraphicsCorporation. SymbianOSisaregisteredtrademarkofSymbianLtd. WindowsisatrademarkofMicrosoft,Inc.,registeredintheUSandothercountries. LynxOSisaregisteredtrademarkofLynuxWorks,Inc. AMXisatrademarkofKADAKProductsLTD. LinuxisaregisteredtrademarkofLinusTorvalds. Allothertrademarksarethepropertyoftheirrespectiveowners.
(c) Oxford Semiconductor, Inc. 2006 The content of this paper is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by Oxford Semiconductor, Inc. Oxford Semiconductor, Inc. assumes no responsibility or liability for any errors or inaccuracies that may appear in this paper.
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