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| DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM DESCRIPTION M2S12D20TP is a 4-bank x 33,554,432-word x 4-bit, M2S12D30TP is a 4-bank x 16,777,216-word x 8-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobes, and output data and data strobe are referenced on both edges of CLK. The M2S12D20/30TP achieve very high speed data rate up to 133MHz, and are suitable for main memory in computer systems. FEATURES - Vdd=Vddq=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions - Commands are entered on each positive CLK edge; - data and data mask are referenced to both edges of DQS - 4 bank operations are controlled by BA0, BA1 (Bank Address) - /CAS latency- 2.0/2.5 (programmable) - Burst length- 2/4/8 (programmable) - Burst type- sequential / interleave (programmable) - Auto precharge / All bank precharge is controlled by A10 - 8192 refresh cycles /64ms (4 banks concurrent refresh) - Auto refresh and Self refresh - Row address A0-12 / Column address A0-9,11-12(x4)/ A0-9,11(x8) SSTL_2 Interface - 400-mil, 66-pin Thin Small Outline Package (TSOP II) - JEDEC standard - Low Power for the Self Refresh Current ICC6 :4mA (-75L,-10L) Operating Frequencies Speed Grade CL=2 * -75 / -75L -10 / -10L 100MHz 100MHz Clock Rate CL=2.5 * 133MHz 125MHz * CL = CAS(Read) Latency Contents are subject to change without notice. MITSUBISHI ELECTRIC -1- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM PIN CONFIGURATION(TOP VIEW) x4 x8 VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC NC VDDQ NC NC VDD NC NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD NC NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 66pin TSOP(II) 60 59 58 57 56 55 400mil width 54 53 x 52 51 875mil length 50 49 48 0.65mm 47 46 Lead Pitch 45 44 43 ROW 42 41 A0-12 40 Column 39 A0-9,11-12(x4) 38 37 A0-9,11 (x8) 36 35 34 VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS NC VREF VSS DM /CLK CLK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC NC VSSQ DQS NC VREF VSS DM /CLK CLK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS CLK,/CLK CKE /CS /RAS /CAS /WE DQ0-7 DQS DM Vref : Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Data I/O : Data Strobe : Write Mask : Reference Voltage A0-12 BA0,1 Vdd VddQ Vss VssQ : Address Input : Bank Address Input : Power Supply : Power Supply for Output : Ground : Ground for Output MITSUBISHI ELECTRIC -2- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM PIN FUNCTION SYMBOL TYPE DESCRIPTION Clock: CLK and /CLK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CLK and negative edge of /CLK. Output (read) data is referenced to the crossings of CLK and /CLK (both directions of crossing). Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE becomes asynchronous input. Self refresh is maintained as long as CKE is low. Chip Select: When /CS is high, any command means No Operation. Combination of /RAS, /CAS, /WE defines basic commands. A0-12 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specified by A0-12. The Column Address is specified by A0-9,11-12(x4) and A0-9,11(x8). A10 is also used to indicate precharge option. When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, all banks are precharged. Bank Address: BA0,1 specifies one of four banks to which a command is applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands. Data Input/Output: Data bus Data Strobe: Output pin during Read operation, input during Write operation. Edge-aligned with read data, placed at the centered of write data to capture the write data. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with the input data during a WRITE operations. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. CLK, /CLK Input CKE Input /CS /RAS, /CAS, /WE Input Input A0-12 Input BA0,1 DQ0-7(x8), DQ0-3(x4) Input Input / Output DQS Input / Output DM Input Vdd, Vss VddQ, VssQ Vref Power Supply Power Supply Input Power Supply for the memory array and peripheral circuitry. VddQ and VssQ are supplied to the Output Buffers only. SSTL_2 reference voltage. MITSUBISHI ELECTRIC -3- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM DQ0 - 7 DQS BLOCK DIAGRAM DLL I/O Buffer QS Buffer Memory Array Bank #0 Memory Array Bank #1 Memory Array Bank #2 Memory Array Bank #3 Mode Register Control Circuitry Address Buffer Clock Buffer A0-12 BA0,1 CLK /CLK CKE Control Signal Buffer /CS /RAS /CAS /WE DM Type Designation Code M 2 S 12 D 3 0 This rule is applied to only Synchronous DRAM family. TP -75 L Power Grade L:Low power, (blank):standard Speed Grade 10: 125MHz@CL=2.5,100MHz@CL=2.0 75: 133MHz@CL=2.5,100MHz@CL=2.0 Package Type TP: TSOP(II) Process Generation (blank):1st gen. Function Reserved for Future Use Organization 2 n 2: x4, 3: x8 DDR Synchronous DRAM Density 12: 512M bits Interface V:LVTTL, S:SSTL_3, _2 Memory Style (DRAM) Mitsubishi Main Designation MITSUBISHI ELECTRIC -4- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM BASIC FUNCTIONS The M2S12D20/30TP provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and precharge option, respectively. Refer to the command truth table for the detailed definition of commands. /CLK CLK /CS /RAS /CAS /WE CKE A10 Chip Select : L=select, H=deselect Command Command Command Refresh Option @refresh command Precharge Option @precharge or read/write command define basic commands Activate (ACT) [/RAS =L, /CAS =/WE =H] ACT command activates one row in an idle bank indicated by BA. Read (READ) [/RAS =H, /CAS =L, /WE =H] READ command starts burst read from the active bank indicated by BA. First output data appears after /CAS latency. When A10 =H in this command, the bank is deactivated after the burst read (autoprecharge, READA) Write (WRITE) [/RAS =H, /CAS =/WE =L] WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is defined by burst length. When A10 =H in this command, the bank is deactivated after the burst write (auto-precharge, WRITEA) Precharge (PRE) [/RAS =L, /CAS =H, /WE =L] PRE command deactivates the active bank indicated by BA. This command also terminates burst read /write operation. When A10 =H in this command, all banks are deactivated (precharge all, PREA ). Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H] REFA command starts auto-refresh cycle. Refresh addresses including bank address are generated internally. After this command, the banks are precharged automatically. MITSUBISHI ELECTRIC -5- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM COMMAND TRUTH TABLE COMMAND Deselect No Operation Row Address Entry & Bank Activate Single Bank Precharge Precharge All Banks Column Address Entry & Write Column Address Entry & Write with Auto-Precharge Column Address Entry & Read Column Address Entry & Read with Auto-Precharge Auto-Refresh Self-Refresh Entry Self-Refresh Exit Burst Terminate Mode Register Set MNEMONIC DESEL NOP ACT PRE PREA WRITE CKE n-1 H H H H H H CKE n X X H H H H /CS H L L L L L /RAS X H L L L H /CAS X H H H H L /WE BA0,1 X H H L L L X X V V X V A10 /AP X X V L H L A0-9, note 11-12 X X V X X V WRITEA H H L H L L V H V READ H H L H L H V L V READA REFA REFS REFSX TERM MRS H H H L L H H H H L H H H H L L L H L L L H L L X H H L L L L X H H L H H H X H L L V X X X X X L H X X X X X L V X X X X X V 1 2 H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number NOTE: 1. Applies only to read bursts while autoprecharge is disabled; this command is undefined (and should not be used) during read bursts while autoprecharge is enabled, as well as write bursts. 2. BA0-BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register;BA0=1 , BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-codes to be written to the selected Mode Register. MITSUBISHI ELECTRIC -6- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM FUNCTION TRUTH TABLE Current State IDLE /CS /RAS /CAS /WE Address H X X XX L L L L L L L ROW ACTIVE H L L L L L L L L READ(AutoPrecharge Disabled) H L L L L L L L L H H H L L L L X H H H H L L L L X H H H H L L L L H H L H H L L X H H L L H H L L X H H L L H H L L H L X H L H L X H L H L H L H L X H L H L H L H L X BA BA, CA, A10 BA, RA BA, A10 Command DESEL NOP TERM READ / WRITE ACT PRE / PREA Action NOP NOP ILLEGAL ILLEGAL Bank Active, Latch RA NOP Auto-Refresh Mode Register Set NOP NOP NOP Begin Read, Latch CA, Determine Auto-Precharge Begin Write, Latch CA, Determine Auto-Precharge Bank Active / ILLEGAL Precharge / Precharge All ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) Terminate Burst Terminate Burst, Latch CA, Begin New Read, Determine AutoPrecharge ILLEGAL Bank Active / ILLEGAL Terminate Burst, Precharge ILLEGAL ILLEGAL 4 5 5 2 2 Notes X REFA Op-Code, ModeMRS Add X DESEL X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 NOP TERM READ / READA WRITE / WRITEA ACT PRE / PREA 2 X REFA Op-Code, ModeMRS Add X DESEL X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 NOP TERM READ / READA WRITE / WRITEA ACT PRE / PREA 3 2 X REFA Op-Code, ModeMRS Add MITSUBISHI ELECTRIC -7- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM FUNCTION TRUTH TABLE (continued) Current State WRITE(AutoPrecharge Disabled) /CS /RAS /CAS /WE Address H X X XX L H H HX L H H L BA L L L L L L READ with Auto-Precharge H L L L L L L L L WRITE with Auto-Precharge H L L L L L L L L H H L L L L X H H H H L L L L X H H H H L L L L L L H H L L X H H L L H H L L X H H L L H H L L H BA, CA, A10 L BA, CA, A10 H BA, RA L BA, A10 HX Op-Code, ModeL Add XX HX L BA H L H L H L X H L H L H L H L BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, ModeAdd X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, ModeAdd Command DESEL NOP TERM READ / READA WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TERM READ / READA WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TERM READ / READA WRITE / WRITEA ACT PRE / PREA REFA MRS Action NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL Terminate Burst, Latch CA, Begin Read, Determine Auto-Precharge Terminate Burst, Latch CA, Begin Write, Determine Auto-Precharge Bank Active / ILLEGAL Terminate Burst, Precharge ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL ILLEGAL for Same Bank ILLEGAL for Same Bank Bank Active / ILLEGAL Precharge / ILLEGAL ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL ILLEGAL for Same Bank ILLEGAL for Same Bank Bank Active / ILLEGAL Precharge / ILLEGAL ILLEGAL ILLEGAL 6 6 2 2 Notes 3 3 2 7 7 2 2 MITSUBISHI ELECTRIC -8- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM FUNCTION TRUTH TABLE (continued) /CS /RAS /CAS /WE Address H X X XX L H H HX L H H L BA L H L X BA, CA, A10 L L H H BA, RA L L H L BA, A10 L L L HX Op-Code, ModeL L L L Add H X X XX ROW L H H HX ACTIVATING L H H L BA L H L X BA, CA, A10 L L H H BA, RA L L H L BA, A10 L L L HX Op-Code, ModeL L L L Add H X X XX WRITE REL H H HX COVERING L H H L BA L H L X BA, CA, A10 L L H H BA, RA L L H L BA, A10 L L L HX Op-Code, ModeL L L L Add Current State PRECHARGING Command DESEL NOP TERM READ / WRITE ACT PRE / PREA REFA MRS DESEL NOP TERM READ / WRITE ACT PRE / PREA REFA MRS DESEL NOP TERM READ / WRITE ACT PRE / PREA REFA MRS Action NOP (Idle after tRP) NOP (Idle after tRP) ILLEGAL ILLEGAL ILLEGAL NOP (Idle after tRP) ILLEGAL ILLEGAL NOP (Row Active after tRCD) NOP (Row Active after tRCD) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP NOP ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Notes 2 2 2 4 2 2 2 2 2 2 2 2 MITSUBISHI ELECTRIC -9- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM FUNCTION TRUTH TABLE (continued) Current State /CS /RAS /CAS /WE Address REFRESHING H X X XX L H H HX L H H L BA L H L X BA, CA, A10 L L H H BA, RA L L H L BA, A10 L L L HX Op-Code, ModeL L L L Add H X X XX MODE REGISTER L H H HX SETTING L H H L BA L H L X BA, CA, A10 L L H H BA, RA L L H L BA, A10 L L L HX Op-Code, ModeL L L L Add Command DESEL NOP TERM READ / WRITE ACT PRE / PREA REFA MRS DESEL NOP TERM READ / WRITE ACT PRE / PREA REFA MRS Action NOP (Idle after tRC) NOP (Idle after tRC) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP (Row Active after tRSC) NOP (Row Active after tRSC) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Notes ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation NOTES: 1. All entries are valid only when CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of specific bank. 3. Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. 6. Refer to Read with Auto-Precharge in page 23. 7. Refer to Write with Auto-Precharge in page 25. ILLEGAL = Device operation and/or data-integrity are not guaranteed. MITSUBISHI ELECTRIC -10- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM FUNCTION TRUTH TABLE for CKE Current State SELFREFRESHING CKE n-1 CKE n H L L L L L L POWER DOWN H L L ALL BANKS IDLE H H H H H H H L H ANY STATE other than listed above H L L X H H H H H L X H L H L L L L L L X H L H L /CS X H L L L L X X X X X L H L L L L X X X X X /RAS X X H H H L X X X X X L X H H H L X X X X X /CAS X X H H L X X X X X X L X H H L X X X X X X /WE X X H L X X X X X X X H X H L X X X X X X X Address X X X X X X X X X X X X X X X X X X X X X X INVALID Exit Self-Refresh (Idle after tRC) Exit Self-Refresh (Idle after tRC) ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self-Refresh) INVALID Exit Power Down to Idle NOP (Maintain Self-Refresh) Refer to Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer to Current State =Power Down Refer to Function Truth Table Begin CLK Suspend at Next Cycle Exit CLK Suspend at Next Cycle Maintain CLK Suspend 3 3 2 2 2 2 2 2 2 2 Action Notes 1 1 1 1 1 1 1 ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care NOTES: 1. Low to High transition of CKE re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command except EXIT. 2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State. 3. Must be legal command. MITSUBISHI ELECTRIC -11- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM SIMPLIFIED STATE DIAGRAM POWER APPLIED POWER ON PREA PRE CHARGE ALL REFS SELF REFRESH MRS REFSX REFA MODE REGISTER SET MRS IDLE AUTO REFRESH CKEL CKEH Active Power Down CKEL ACT CKEH POWER DOWN ROW ACTIVE WRITE WRITE WRITEA READA READ READ READ BURST STOP WRITE READ TERM WRITEA READA READA WRITEA PRE PRE PRE READA PRE CHARGE Automatic Sequence Command Sequence MITSUBISHI ELECTRIC -12- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM POWER ON SEQUENCE The following power on sequences are necessary to guarantee the proper operations of the DDR SDRAM. 1. Apply VDD before or at the same time as VDDQ 2. Apply VDDQ before or at the same time as VTT & Vref 3. Maintain stable conditions for 200us after stable power and CLK are supplied, assert NOP or DSEL 4. Issue precharge command for all banks of the device 5. Issue EMRS to program proper functions 6. Issue MRS to configure the Mode Register and to reset the DLL 7. Issue 2 or more Auto Refresh commands 8. Maintain stable conditions for 200 cycle After these sequence, the DDR SDRAM is in the idle state and ready for normal operation. MODE REGISTER Burst Length, Burst Type and /CAS Latency can be programmed by configuring the mode register (MRS). The mode register stores these data until the next MRS command, which may be issued when both banks are in idle state. After tRSC from an MRS command, the DDR SDRAM is ready to accept the new command. BA1 BA0 A12 A11 A10 A9 0 0 0 0 0 0 A8 DR A7 0 A6 A5 A4 A3 A2 BT A1 BL A0 CLK /CLK /CS /RAS /CAS /WE BA0 BA1 LTMODE A12-A0 V Latency Mode CL 000 001 010 011 100 101 110 111 /CAS Latency R R 2 R R R 2.5 R NO YES Burst Length 0 0 0 0 1 1 1 1 BL 00 01 10 11 00 01 10 11 BT=0 R 2 4 8 R R R R BT=1 R 2 4 8 R R R R Burst Type DLL Reset 0 1 0 1 Sequential Interleaved R: Reserved for Future Use MITSUBISHI ELECTRIC -13- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM EXTENDED MODE REGISTER DLL disable / enable mode can be programmed in setting the extended mode register (EMRS). The extended mode register stores these data until the next EMRS command, which may be issued when all banks are in idle state. After tMRD from a EMRS command, the DDR SDRAM is ready to accept the new command. CLK /CLK /CS /RAS /CAS BA1 BA0 A12 A11 A10 A9 0 1 0 0 0 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 DS A0 DD /WE BA0 BA1 A12-A0 V DLL Disable 0 1 DLL Enable DLL Disable Drive Strength 0 1 Normal Weak MITSUBISHI ELECTRIC -14- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM /CLK CLK Command Address DQS DQ CL= 2 BL= 4 Read Y Write Y Q0 Q1 Q2 Q3 D0 D1 D2 D3 /CAS Latency Burst Length Burst Length Initial Address A2 0 0 0 0 1 1 1 1 A1 A0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 BL Sequential 0 1 2 3 8 4 5 6 7 0 1 4 2 3 0 2 1 1 2 3 4 5 6 7 0 1 2 3 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 3 4 5 6 7 0 1 2 3 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 Column Addressing Interleaved 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 0 1 2 3 0 1 1 0 3 2 5 4 7 6 1 0 3 2 1 0 2 3 0 1 6 7 4 5 2 3 0 1 3 2 1 0 7 6 5 4 3 2 1 0 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0 0 1 0 1 0 1 0 1 0 1 MITSUBISHI ELECTRIC -15- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM ABSOLUTE MAXIMUM RATINGS Symbol Vdd VddQ VI VO IO Pd Topr Tstg Parameter Supply Voltage Supply Voltage for Output Input Voltage Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature Ta = 25 oC Conditions with respect to Vss with respect to VssQ with respect to Vss with respect to VssQ Ratings -0.5 ~ 3.7 -0.5 ~ 3.7 -0.5 ~ Vdd+0.5 -0.5 ~ VddQ+0.5 50 1500 0 ~ 70 -65 ~ 150 Unit V V V V mA mW o o C C DC OPERATING CONDITIONS (Ta=0 ~ 70oC, unless otherwise noted) Symbol Vdd VddQ Vref VIH(DC) VIL(DC) VIN(DC) VID(DC) VTT Limits Unit Notes Min. Typ. Max. Supply Voltage 2.3 2.5 2.7 V Supply Voltage for Output 2.3 2.5 2.7 V Input Reference Voltage 0.49*VddQ 0.50*VddQ 0.51*VddQ V 5 High-Level Input Voltage Vref + 0.15 VddQ+0.3 V Low-Level Input Voltage -0.3 Vref - 0.15 V Input Voltage Level, CLK and /CLK -0.3 VddQ + 0.3 V Input Differential Voltage, CLK and /CLK 0.36 VddQ + 0.6 V 7 I/O Termination Voltage Vref - 0.04 Vref + 0.04 V 6 Parameter AC OVERSHOOT/UNDERSHOOT SPECIFICATION Parameter Maximum peak amplitude allowed for overshoot Maximum peak amplitude allowed for undershoot The area between the overshoot signal and Vdd must be less than or euqal to The area between the undershoot signal and Vss must be less than or euqal to Specification 1.6V 1.6V 4.5 V-ns 4.5 V-ns Volts (V) 5 Overshoot 4 3 2 1 Vss(0) -1 -2 -3 undershoot Maximum Amplitude Vdd Area (max.4.5V-ns) Maximum Amplitude 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 5.625 7.5 time (ns) MITSUBISHI ELECTRIC -16- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM AVERAGE SUPPLY CURRENT from Vdd (Ta=0 ~ 70oC, Vdd = VddQ = 2.5V + 0.2V, Vss = VssQ = 0V, Output Open, unless otherwise noted) Symbol Parameter/Test Conditions Organization Limits(Max.) -75 -10 140 140 150 160 6 30 30 15 130 130 140 150 6 25 25 12 Unit Notes OPERATING CURRENT: One Bank; Active-Precharge; t RC = t RC MIN; t CK IDD0 = t CK MIN; DQ, DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle OPERATING CURRENT: One Bank; Active-Read-Precharge; IDD1 Burst = 2; t RC = t RC MIN; CL = 2.5; t CK = t CK MIN; IOUT= 0mA; Address and control inputs changing once per clock cycle IDD2P PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; powerdown mode; CKE IDLE STANDBY CURRENT: /CS > VIH (MIN); All banks idle; IDD2F CKE > VIH (MIN); t CK = t CK MIN; Address and other control inputs changing once per clock cycle IDD3P ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; powerdown mode; CKE < VIL (MAX); t CK = t CK MIN ACTIVE STANDBY CURRENT: /CS > VIH (MIN); CKE > VIH (MIN); One bank; Active-Precharge; t RC = t RAS MAX; t CK = t CK MIN; DQ,DM and IDD3N DQS inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst;One bank active; IDD4R Address and control inputs changing once per clock cycle;CL=2.5; t CK = t CK MIN; IOUT = 0 mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; IDD4W Address and control inputs changing once per clock cycle; CL=2.5; t CK = t CK MIN;DQ, DM and DQS inputs changing twice per clock cycle IDD5 AUTO REFRESH CURRENT: t RC = t RFC (MIN) IDD6 SELF REFRESH CURRENT: CKE < 0.2V Standard Low Power (-75L,-10L) OPERATING CURRENT-Four bank Operation: Four bank interleaving with IDD7 BL=4 -Refer to the Notes 20 45 45 190 220 180 210 280 6 4 380 400 35 35 140 170 150 180 260 6 4 300 320 mA 20 20 AC OPERATING CONDITIONS AND CHARACTERISTICS (Ta=0 ~ 70oC, Vdd = VddQ = 2.5V + 0.2V, Vss = VssQ = 0V, Output Open, unless otherwise noted) Symbol Parameter / Test Conditions Limits Min. Vref + 0.31 Max. Vref - 0.31 0.7 VddQ + 0.6 0.5*VddQ - 0.2 0.5*VddQ + 0.2 -5 5 -2 2 -16.8 16.8 Unit V V V V A A mA mA 7 8 Notes VIH(AC) High-Level Input Voltage (AC) VIL(AC) Low-Level Input Voltage (AC) VID(AC) VIX(AC) IOZ II IOH IOL Input Differential Voltage, CLK and /CLK Input Crossing Point Voltage, CLK and /CLK Off-state Output Current /Q floating Vo=0~VddQ Input Current / VIN=0 ~ VddQ Output High Current (VOUT = VTT+0.84V) Output High Current (VOUT = VTT-0.84V) MITSUBISHI ELECTRIC -17- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM AC TIMING REQUIREMENTS (Ta=0 ~ 70oC, Vdd = VddQ = 2.5V +0.2V, Vss = VssQ = 0V, unless otherwise noted) Symbol tAC AC Characteristics Parameter DQ Output Valid data delay time from CLK//CLK -75 Min. -0.75 -0.75 0.45 0.45 CL=2.5 CL=2 7.5 10 0.5 0.5 1.75 -0.75 -0.75 0.75 0.75 0.5 tCLmin or tCHmin tHP-0.75 0.75 0.35 0.35 0.2 0.2 15 0 0.4 0.25 0.9 0.9 0.4 0.9 0.6 1.1 0.6 1.25 tCLmin or tCHmin tHP-1.0 0.75 0.35 0.35 0.2 0.2 15 0 0.4 0.25 1.1 1.1 0.4 0.9 0.6 1.1 0.6 1.25 Max 0.75 0.75 0.55 0.55 15 15 Min. -0.8 -0.8 0.45 0.45 8 10 0.6 0.6 2 -0.8 -0.8 0.8 0.8 0.6 -10 Max 0.8 0.8 0.55 0.55 15 15 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns tCK tCK tCK tCK tCK ns ns tCK tCK ns ns tCK tCK 19 19 16 15 14 14 Notes tDQSCK DQ Output Valid data delay time from CLK//CLK tCH tCL tCK tDS tDH CLK High level width CLK Low level width CLK cycle time Input Setup time (DQ,DM) Input Hold time(DQ,DM) tDIPW DQ and DM input pulse width (for each input) tHZ tLZ Data-out-high impedance time from CLK//CLK Data-out-low impedance time from CLK//CLK tDQSQ DQ Valid data delay time from DQS tHP tQH tDQSS Clock half period Output DQS valid window Write command to first DQS latching transition tDQSH DQS input High level width tDQSL DQS input Low level width tDSS tDSH tMRD DQS falling edge to CLK setup time DQS falling edge hold time from CLK Mode Register Set command cycle time tWPRES Write preamble setup time tWPST Write postamble tWPRE Write preamble tIS tIH tRPST tRPRE Input Setup time (address and control) Input Hold time (address and control) Read postamble Read preamble MITSUBISHI ELECTRIC -18- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM AC TIMING REQUIREMENTS(Continued) (Ta=0 ~ 70oC, Vdd = VddQ = 2.5V +0.2V, Vss = VssQ = 0V, unless otherwise noted) Symbol tRAS tRC tRFC tRCD tRP tRRD tWR tDAL tWTR AC Characteristics Parameter Row Active time Row Cycle time(operation) Auto Ref. to Active/Auto Ref. command period Row to Column Delay Row Precharge time Act to Act Delay time Write Recovery time Auto Precharge write recovery + precharge time Internal Write to Read Command Delay -75 Min. 45 65 75 20 20 15 15 35 1 75 200 1 1 7.8 Max 120,000 Min. 50 70 80 20 20 15 15 35 1 80 200 1 1 7.8 -10 Max 120,000 Unit ns ns ns ns ns ns ns ns tCK ns tCK tCK tCK s Notes tXSNR Exit Self Ref. to non-Read command tXSRD Exit Self Ref. to -Read command tXPNR Exit Power down to command tXPRD Exit Power down to -Read command tREFI Average Periodic Refresh interval 18 17 Output Load Condition DQS VTT=VREF VREF DQ VREF 50 VOUT Zo=50 30pF VREF Output Timing Measurement Reference Point CAPACITANCE (Ta=0 ~ 70oC, Vdd = VddQ = 2.5V + 0.2V, Vss = VssQ = 0V, unless otherwise noted) Symbol CI(A) CI(C) CI(K) CI/O Parameter Input Capacitance, address pin Input Capacitance, control pin Input Capacitance, CLK pin I/O Capacitance, I/O, DQS, DM pin Test Condition VI=1.25v f=100MHz VI=25mVrms Limits Delta Unit Notes Min. Max. Cap.(Max.) 2.0 3.0 pF 11 0.50 2.0 3.0 pF 11 2.0 4.0 3.0 5.0 0.25 0.50 pF pF 11 11 MITSUBISHI ELECTRIC -19- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM Notes 1. All voltages are referenced to Vss. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, However, the specifications and device operations are guaranteed for the full voltage range specified. 3. AC timing and IDD tests may use the VIL to VIH swing of up to 1.5V in the test environment. Input timing is still referenced to VREF (or to the crossing point for CK//CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL(AC) and VIH(AC). 4. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above (below) the DC input LOW (HIGH) level. 5. VREF is expected to be equal to 0.5*VddQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +2% of the DC value. 6. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 7. VID is the magnitude of the difference between the input level on CLK and the input level on /CLK. 8. The value of VIX is expected to equal 0.5*VddQ of the transmitting device and must track variations in the DC level of the same. 9. Enables on-chip refresh and address counters. 10. IDD specifications are tested after the device is properly initialized. 11. This parameter is sampled. VddQ = 2.5V+0.2V, Vdd = 2.5V + 0.2V , f = 100 MHz, Ta = 25oC, VOUT(DC) = VddQ/2, VOUT(PEAK TO PEAK) = 25mV. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in loading (to facilitate trace matching at the board level). 12. The CLK//CLK input reference level (for timing referenced to CLK//CLK) is the point at which CLK and /CLK cross; the input reference level for signals other than CLK//CLK, is VREF. 13. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE< 0.3VddQ is recognized as LOW. 14. t HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ), or begins driving (LZ). 15. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 16. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CLK edge. A valid transition is defined as monotonic, and satisfies the input slew rate specifications. When no writes were previously in progress on the bus, DQS will be transitioning from High-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. MITSUBISHI ELECTRIC -20- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM Notes (continued) 17. A maximum of eight AUTO REFRESH commands can be asserted to any given DDR SDRAM device. 18. tXPRD should be 200 tCLK when the clocks are unstable during the power down mode. 19. For command/address and CK & /CK slew rate > 1.0V/ns. 20. IDD7 : Operating current is measured under the conditions (1).Four Bank are being interleaved with tRC(min),burst mode,address and control inputs on NOP edge are not changing.Iout = 0mA (2).Timing Patterns -DDR200(-10) (100MHz,CL=2) : tCK=10ns, CL=2, BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with autoprecharge Setup:A0 N A1 R0 A2 R1 A3 R2 Read :A0 R3 A1 R0 A2 R1 A3 R2 -repeat the same timing with random address changing 50% of data changing at every transfer -DDR266B(-75) (133MHz,CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with autoprecharge Setup:A0 N A1 R0 A2 R1 A3 R2 N R3 Read :A0 N A1 R0 A2 R1 A3 R2 N R3 -repeat the same timing with random address changing 50% of data changing at every transfer -DDR266A(-75A) (133MHz,CL=2) : tCK=7.5ns, CL=2, BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with autoprecharge Setup: A0 N A1 R0 A2 R1 A3 R2 N R3 Read : A0 N A1 R0 A2 R1 A3 R2 N R3 -repeat the same timing with random address changing 50% of data changing at every transfer *Legend: A=Activate,R=Read, P=Precharge, N=NOP MITSUBISHI ELECTRIC -21- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM Read Operation tCK tCH tCL /CLK CLK Cmd & Add. tDQSCK tIS tIH VREF Valid Data tRPRE tQH tRPST DQS tDQSQ DQ tAC Write Operation / tDQSS=max. /CLK CLK DQS tDQSS tWPRES tDSS tDQSL tDS tDQSH tDH tWPST tWPRE DQ Write Operation / tDQSS=min. /CLK CLK DQS tDQSS tWPRES tWPRE tDQSL tDS tDQSH tDH tDSH tWPST DQ MITSUBISHI ELECTRIC -22- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM OPERATIONAL DESCRIPTION BANK ACTIVATE (ACT) The DDR SDRAM has four independent banks. Each bank is activated by the ACT command with the bank addresses (BA0,1). A row is indicated by the row address A12-0. The minimum activation interval between banks is tRRD. PRECHARGE (PRE) The PRE command deactivates the bank indicated by BA0,1. When multiple banks are active, the precharge all command (PREA,PRE+A10=H) is available to deactivate all banks them at the same time. After tRP from the precharge, an ACT command to the same bank can be issued. Bank Activation and Precharge All (BL=8, CL=2) /CLK CLK 2 ACT command / tRCmin tRCmin Command A0-9,11-12 ACT tRRD Xa ACT READ tRAS Xb tRCD Y BL/2 0 PRE tRP ACT Xb A10 BA0,1 Xa Xb 1 Xb 00 01 00 01 DQS DQ Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7 Precharge all A precharge command can be issued after BL/2 time from a read command. MITSUBISHI ELECTRIC -23- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 READ MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM After tRCD from the bank activation, a READ command can be issued. 1st Output data is available after the /CAS Latency from the READ, followed by (BL-1) consecutive data. (BL:Burst Length) The start address is specified by A12-A11,A9-A0(x4)/A11,A9-A0(x8), and the address sequence of burst data is defined by the Burst Type. A READ command may be applied to any active bank, so the row precharge time (tRP) can be hidden during the continuous burst data by interleaving the multiple banks. When A10 is high in READ command, the auto-precharge (READA) is performed. Any command(READ,WRITE,PRE,ACT) asserted to the same bank is inhibited till the internal precharge is completed. The internal precharge operation starts at BL/2 time after READA command. The next ACT command can be issued after (BL/2+tRP) time from the previous READA. Multi Bank Interleaving READ (BL=8, CL=2) /CLK CLK Command A0-9,11-12 A10 BA0,1 DQS DQ /CAS latency Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7 Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 Qb7 Qb8 ACT tRCD Xa Xa READ ACT Y 0 Xb Xb READ PRE Y 0 0 00 00 10 10 00 Burst Length MITSUBISHI ELECTRIC -24- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM READ with Auto-Precharge (BL=8, CL=2,2.5) 0 1 2 3 4 5 6 BL/2 + tRP 7 8 9 10 11 12 /CLK CLK Command ACT tRCD READ BL/2 Y 1 00 tRP A0-9,11-12 A10 BA0,1 DQS CL=2 DQ DQS CL=2.5 DQ Xa Xa 00 Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7 Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7 Internal Precharge Starts here Asserted Command READ READA WRITE(CL=2) WRITE(CL=2.5) WRITEA(CL=2) For Different Bank 3 4 5 6 7 8 9 10 Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Illegal Illegal Illegal Illegal Illegal Legal Legal Legal Illegal Illegal Illegal Illegal Illegal Illegal Legal Legal Illegal Illegal Illegal Illegal Illegal Legal Legal Legal WRITEA(CL=2.5) Illegal Illegal Illegal Illegal Illegal Illegal Legal Legal ACT PCG Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Operating description when new command is asserted. MITSUBISHI ELECTRIC -25- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 WRITE MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM After tRCD time from the bank activation, a WRITE command can be issued. 1st input data is sampled at the WRITE command with data strobe input, followed by (BL-1) data being written into RAM. The Burst Length is BL. The start address is specified by A12-A11,A9-A0(x4)/A11,A9-A0(x8), and the address sequence of burst data is defined by the Burst Type. A WRITE command may be applied to any active bank, so the row precharge time (tRP) can be hidden during the continuous input data by interleaving the multiple banks. The write recovery time (tWR) is required from the last written data to the next PRE command. When A10 is high in a WRITE command, the auto-precharge(WRITEA) is performed. Any command(READ,WRITE,PRE,ACT) to the same bank is inhibited till the internal precharge operation is completed. The next ACT command can be issued after tDAL from the last input data cycle. Multi Bank Interleaving WRITE (BL=8) /CLK CLK Command A0-9,11-12 A10 BA0,1 DQS DQ Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7 Db0 Db1 Db2 Db3 Db4 Db5 Db6 Db7 ACT tRCD Xa D Xa Xa 00 WRITE ACT Ya 0 00 Xb Xb 10 tRCD D WRITE Yb 0 10 PRE PRE 0 00 0 10 MITSUBISHI ELECTRIC -26- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM WRITE with Auto-Precharge (BL=8) 0 1 2 3 4 5 6 7 8 9 10 11 12 /CLK CLK Command A0-9,11-12 A10 BA0,1 DQS DQ Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7 ACT tRC Xa Xa 00 D WRITE tDAL Y 1 00 ACT Xb Xb 00 Asserted Command READ READA WRITE WRITEA ACT PCG For Different Bank 3 Illegal Illegal Legal Legal Legal Legal 4 Illegal Illegal Legal Legal Legal Legal 5 6 7 Illegal Illegal Legal Legal Legal Legal 8 Legal Legal Legal Legal Legal Legal 9 Legal Legal Legal Legal Legal Legal 10 Legal Legal Legal Legal Legal Legal Illegal Illegal Illegal Illegal Legal Legal Legal Legal Legal Legal Legal Legal Operating description when new command is asserted. MITSUBISHI ELECTRIC -27- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM BURST INTERRUPTION [Read Interrupted by Read] Burst read operation can be interrupted by the new Read command issued to any other bank. Random column access is allowed. READ to READ interval is 1CLK as the minimum. Read Interrupted by Read (BL=8, CL=2) /CLK CLK Command A0-9,11-12 A10 BA0,1 DQS DQ Qai0 Qai1 Qaj0 Qaj1 Qaj2 Qaj3 Qak0 Qak1 Qak2 Qak3 Qak4 Qak5 Qal0 Qal1 Qal2 Qal3 Qal4 Qal5 Qal6 Qal7 READ READ Yi 0 00 Yj 0 00 READ Yk 0 10 READ Yl 0 01 [Read Interrupted by precharge] Burst read operation can be interrupted by precharge of the same bank. READ to PRE interval is 1 CLK minimum. The time between PRE command to output disable is equal to the CAS Latency. As a result, READ to PRE interval determines valid data length to be outputed. The figure below shows the example of BL=8. Read Interrupted by Precharge (BL=8) /CLK CLK Command DQS DQ Command READ PRE Q0 Q1 Q2 Q3 Q4 Q5 READ PRE CL=2.5 DQS DQ Command DQS DQ Q0 Q1 Q0 Q1 Q2 Q3 READ PRE MITSUBISHI ELECTRIC -28- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM Read Interrupted by Precharge (BL=8) /CLK CLK Command DQS DQ Command READ Q0 Q1 Q2 Q3 Q4 Q5 READ PRE PRE CL=2.0 DQS DQ Command DQS DQ Q0 Q1 Q0 Q1 Q2 Q3 READ PRE MITSUBISHI ELECTRIC -29- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM [Read Interrupted by Burst Stop] Burst read operation can be interrupted by a burst stop command(TERM). READ to TERM interval is 1 CLK minimum. The time between TERM command to output disable equal to the CAS Latency. As a result, READ to TERM interval determines valid data length to be output. The figure below shows the example of BL=8. Read Interrupted by TERM (BL=8) /CLK CLK Command DQS DQ Command READ TERM Q0 Q1 Q2 Q3 Q4 Q5 READ TERM CL=2.5 DQS DQ Command DQS DQ Command DQS DQ Command READ Q0 Q1 Q2 Q3 Q4 Q5 Q0 Q1 Q0 Q1 Q2 Q3 READ TERM READ TERM TERM CL=2.0 DQS DQ Command DQS DQ Q0 Q1 Q0 Q1 Q2 Q3 READ TERM MITSUBISHI ELECTRIC -30- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM [Read Interrupted by Write with TERM] Read Interrupted by TERM (BL=8) /CLK CLK Command READ TERM WRITE CL=2.5 DQS DQ Command READ TERM Q0 Q1 Q2 Q3 D0 D1 D2 D3 D4 D5 WRITE CL=2.0 DQS DQ Q0 Q1 Q2 Q3 D0 D1 D2 D3 D4 D5 D6 D7 MITSUBISHI ELECTRIC -31- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM [Write interrupted by Write] Burst write operation can be interrupted by Write to any bank. Random column access is allowed. WRITE to WRITE interval is 1 CLK minimum. Write Interrupted by Write (BL=8) /CLK CLK Command A0-9,11-12 A10 BA0,1 DQS DQ Dai0 Dai1 Daj0 Daj1 Daj2 Daj3 Dak0 Dak1 Dak2 Dak3 Dak4 Dak5 Dal0 Dal1 Dal2 Dal3 Dal4 Dal5 Dal6 Dal7 WRITE WRITE Yi 0 00 Yj 0 00 WRITE Yk 0 10 WRITE Yl 0 00 [Write interrupted by Read] Burst write operation can be interrupted by read of the same or the other bank. Random column access is allowed. Internal WRITE to READ command interval(tWTR) is 1 CLK minimum. The input data masked by DM in the interrupted READ cycle is "don't care". tWTR is referenced from the first positive edge after the last data input. Write Interrupted by Read (BL=8, CL=2.5) /CLK CLK Command A0-9,11 A10 BA0,1 DM tWTR QS DQ Dai0 Dai1 Qaj0 Qaj1 Qaj2 Qaj3 Qaj4 Qaj5 Qaj6 Qaj7 WRITE Yi 0 00 READ Yj 0 00 MITSUBISHI ELECTRIC -32- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM [Write interrupted by Precharge] Burst write operation can be interrupted by precharge of the same or all bank. Random column access is allowed. tWR is referenced from the first positive CLK edge after the last data input. Write Interrupted by Precharge (BL=8, CL=2.5) /CLK CLK Command A0-9,11-12 A10 BA0,1 DM QS DQ Dai0 Dai1 WRITE Yi 0 00 PRE 00 tWR MITSUBISHI ELECTRIC -33- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM Initialize and MRS [Initialize and Mode Register sets] /CLK CLK CKE Command A0-9,11-12 A10 BA0,1 DQS DQ tMRD Extended Mode Register Set 1 NOP PRE EMRS Code MRS Code PRE AR AR MRS ACT Xa Code Code 1 Code Xa 10 00 00 Xa tMRD tRP tRFC tRFC tMRD Mode Register Set, Reset DLL [AUTO REFRESH] Auto-refresh cycle is initiated with a REFA(/CS=/RAS=/CAS=L,/WE=CKE=H) command. The refresh address is generated internally. 8192 REFA cycles within 64 ms refresh 512 Mbits memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing an auto refresh, all banks must be in the idle state. The minimum interval between auto-refreshes is tRFC. No command is allowed within tRFC time after the REFA command. Auto-Refresh /CLK CLK /CS /RAS /CAS /WE CKE A0-12 BA0,1 tRFC NOP or DESELECT Auto Refresh on All Banks Auto Refresh on All Banks -34- MITSUBISHI ELECTRIC DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM [SELF REFRESH] Self -refresh mode is entered by asserting a REFS command (/CS=/RAS=/CAS=L,/WE=H,CKE=L). The self-refresh mode is maintained as long as CKE is kept low. During the self-refresh mode, CKE becomes asynchronous and the only enable input. All other inputs including CLK are disabled and ignored to save the power consumption. In order to exit the self-refresh mode, the device shall be supplied the stable CLK input, followed by DESEL or NOP command, then asserting CKE for the period longer than tXSNR/tXSRD. Self-Refresh /CLK CLK Stable CLK /CS /RAS /CAS /WE CKE A0-12 BA0,1 tXSNR Self Refresh Entry Self Refresh Exit X X tXSRD Y Y MITSUBISHI ELECTRIC -35- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM [Power DOWN] The purpose of CLK suspend is power down. CKE is synchronous input except during the selfrefresh mode. A command at cycle is ignored. From CKE=H to normal function, DLL recovery time is NOT required when the stable CLK is supplied during the power down mode. Power Down by CKE /CLK CLK CKE Command PRE NOP Standby Power Down NOP Valid tXPNR/tXPRD CKE Command Active Power Down ACT NOP NOP Valid [DM CONTROL] DM is defined as the data mask for write data. During the writes, DM masks the input data cycle by cycle. Latency of DM to write mask is 0. DM Function(BL=8,CL=2) /CLK CLK Command DM DQS DQ D0 D1 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 WRITE READ Don't Care masked by DM=H MITSUBISHI ELECTRIC -36- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM Keep safety first in your circuit designs! Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com). When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. MITSUBISHI ELECTRIC -37- DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM Revision History Rev. 1.0 Nov '01 -New registration Rev. 1.1 Jan '02 -Added -75L,-10L spec. -Added WRITEA and READA operating description table when new command asserted -Deleted -75A spec. -Added AC overshoot and overshoot spec. -Changed the average supply current from Vdd spec. from to Symbol Organization x4 IDD0 x8 x4 IDD1 x8 IDD2P x4/x8 x4 IDD2F x8 IDD3P x4/x8 x4 IDD3N x8 x4 IDD4R x8 x4 IDD4W x8 IDD5 IDD6 IDD7 x4/x8 x4/x8 x4 x8 220 360 6 400 410 210 340 6 380 390 IDD5 IDD6 -L IDD7 225 210 215 200 IDD4W 70 215 65 205 IDD4R 40 35 65 40 35 60 IDD3N IDD3P 215 20 35 210 20 35 IDD2F IDD2P 205 210 200 205 IDD1 Limits(Max.) -75 200 -10 195 IDD0 Symbol Limits(Max.) -75 -10 140 140 150 160 6 30 30 15 130 130 140 150 6 25 25 12 Unit 45 45 190 220 180 210 280 6 4 380 400 35 35 140 170 150 180 260 6 4 300 320 mA MITSUBISHI ELECTRIC -38- |
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