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WSF128K16-XXX
128Kx16 SRAM/FLASH MODULE, SMD 5962-96900
FEATURES
n n n Access Times of 35ns (SRAM) and 70ns (FLASH) n Access Times of 70ns (SRAM) and 120ns (FLASH) n Packaging * 66-pin, PGA Type, 1.075 inch square HIP, Hermetic Ceramic HIP (Package 400) * 66-pin, PGA Type, 1.185 inch square HIP, Hermetic Ceramic HIP (Package 401) * 68 lead, Hermetic CQFP (G1U), 22.4mm (0.880 inch) square (Package 519). Designed to fit JEDEC 68 lead 0.990" CQFJ footprint (Fig. 2) n 128Kx16 SRAM n 128Kx16 5V FLASH n Organized as 128Kx16 of SRAM and 128Kx16 of Flash Memory with separate Data Buses n Both blocks of memory are User Configurable as 256Kx8 n Low Power CMOS n Commercial, Industrial and Military Temperature Ranges n TTL Compatible Inputs and Outputs n n n n Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation Weight * WSF128K16-XHX - 13 grams typical * WSF128K16-H1X - 13 grams typical * WSF128K16-XG1UX - 5 grams typical
FLASH MEMORY FEATURES
n n 10,000 Erase/Program Cycles Sector Architecture * 8 equal size sectors of 16K bytes each * Any combination of sectors can be concurrently erased. Also supports full chip erase 5 Volt Programming; 5V 10% Supply Embedded Erase and Program Algorithms Hardware Write Protection Page Program Operation and Internal Program Control Time.
Note: For programming information refer to Flash Programming 1M5 Application Note.
FIG.1 PIN CONFIGURATION FOR WSF128K16-XHX AND WSF128K16-XH1X
TOP VIEW
FD0-15 SD0-15 A0-16 SWE1-2 SCS1-2 OE VCC GND NC FWE1-2 FCS1-2
PIN DESCRIPTION
Flash Data Inputs/Outputs SRAM Data Inputs/Outputs Address Inputs SRAM Write Enable SRAM Chip Selects Output Enable Power Supply Ground Not Connected Flash Write Enable Flash Chip Select
BLOCK DIAGRAM
May 2001 Rev. 5
1
White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com
WSF128K16-XXX
FIG. 2 PIN CONFIGURATION FOR WSF128K16-XG1UX
TOP VIEW
FD0-15 SD0-15 A0-16 SWE1-2 SCS1-2 OE
PIN DESCRIPTION
Flash Data Inputs/Outputs SRAM Data Inputs/Outputs Address Inputs SRAM Write Enable SRAM Chip Selects Output Enable Power Supply Ground Not Connected Flash Write Enable Flash Chip Select
The WEDC 68 lead G1U CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G1U has the TCE and lead inspection advantage of the CQFP form.
VCC GND NC FWE1-2 FCS1-2
BLOCK DIAGRAM
White Electronic Designs Corporation * Phoenix AZ * (602) 437-1520
2
WSF128K16-XXX
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Min Max Unit SCS OE
SRAM TRUTH TABLE
SWE Mode Data I/O Power
Operating Temperature Storage Temperature Signal Voltage Relative to GND Junction Temperature Supply Voltage
TA TSTG VG TJ VCC
-55 -65 -0.5 -0.5
+125 +150 7.0 150 7.0
C C V C V
H L L L
X L H X
X H H L
Standby Read Read Write
High Z Data Out High Z Data In
Standby Active Active Active
Parameter
CAPACITANCE (TA = +25C)
10 years 10,000
Test Symbol Condition Max Unit
Flash Data Retention Flash Endurance (write/erase cycles)
NOTES: 1. Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability.
OE Capacitance F/S WE 1-2 Capacitance F/S CS 1-2 Capacitance SD0-15/FD0-15 Capacitance A0 - A16 Capacitance
COE CWE CCS CI/O CAD
VIN = 0V, f = 1.0MHz 50 VIN = 0V, f = 1.0MHz 20 VIN = 0V, f = 1.0MHz 20 VIN = 0V, f = 1.0MHz 20 VIN = 0V, f = 1.0MHz 50
pF pF pF pF pF
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Max Unit
This parameter is guaranteed by design but not tested.
Supply Voltage Input High Voltage Input Low Voltage
VCC VIH VIL
4.5 2.2 -0.5
5.5 VCC + 0.3 +0.8
V V V
DC CHARACTERISTICS (VCC = 5.0V, VSS = 0V, TA = -55C TO +125C)
Parameter Symbol Conditions Min Max Unit
Input Leakage Current Output Leakage Current SRAM Operating Supply Current x 16 Mode Standby Current SRAM Output Low Voltage SRAM Output High Voltage Flash VCC Active Current for Read (1) Flash VCC Active Current for Program or Erase (2) Flash Output Low Voltage Flash Output High Voltage Flash Output High Voltage Flash Low VCC Lock Out Voltage
ILI ILO ICCx16 ISB VOL VOH ICC1 ICC2 VOL VOH1 VOH2 VLKO
VCC = 5.5, VIN = GND to VCC SCS = VIH, OE = VIH, VOUT = GND to VCC SCS = VIL, OE = FCS = VIH, f = 5MHz, VCC = 5.5 FCS = SCS = VIH, OE = VIH, f = 5MHz, VCC = 5.5 IOL = 2.1mA, VCC = 4.5 IOH = -1.0mA, VCC = 4.5 FCS = VIL, OE = SCS = VIH FCS = VIL, OE = SCS = VIH IOL = 8.0mA, VCC = 4.5 IOH = -2.5 mA, VCC = 4.5 IOH = -100 A, VCC = 4.5 0.85 x VCC VCC -0.4 3.2 2.4
10 10 360 40 0.4
A A mA mA V V
100 130 0.45
mA mA V V V V
NOTES: 1. The ICC current listed includes both the DC operating current and the frequency dependent component (@ 5 MHz). The frequency component typically is less than 2 mA/MHz, with OE at VIH. 2. ICC active while Embedded Algorithm (program or erase) is in progress. 3. DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V
3
White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com
WSF128K16-XXX
SRAM AC CHARACTERISTICS (VCC = 5.0V, TA = -55C TO +125C)
Parameter Read Cycle Symbol -35 Min Max -70 Min Max Unit
SRAM AC CHARACTERISTICS (VCC = 5.0V, TA = -55C TO +125C)
Parameter Write Cycle Symbol -35 Min Max -70 Unit
Read Cycle Time Address Access Time Output Hold from Address Change Chip Select Access Time Output Enable to Output Valid Chip Select to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z
tRC tAA tOH tACS tOE tCLZ 1 tOLZ 1 tCHZ 1 tOHZ 1
35 35 0 35 20 3 0 20 20
70 70 3 70 35 3 0 25 25
ns ns ns ns ns ns ns ns ns
Write Cycle Time Chip Select to End of Write Address Valid to End of Write Data Valid to End of Write Write Pulse Width Address Setup Time Address Hold Time Output Active from End of Write Write Enable to Output in High Z Data Hold from Write Time
tWC tCW tAW tDW tWP tAS tAH tOW 1 tWHZ 1 tDH
35 25 25 20 25 0 0 4 20 0
70 60 60 30 50 5 5 5 25 0
ns ns ns ns ns ns ns ns ns ns
1. This parameter is guaranteed by design but not tested.
1. This parameter is guaranteed by design but not tested.
FIG. 3 AC TEST CIRCUIT
Parameter
AC TEST CONDITIONS
Typ Unit
Input Pulse Levels Input Rise and Fall Input and Output Reference Level Output Timing Reference Level
VIL = 0, VIH = 3.0 5 1.5 1.5
V ns V V
Notes: VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75W. VZ is typically the midpoint of VOH and VOL. IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance.
White Electronic Designs Corporation * Phoenix AZ * (602) 437-1520
4
WSF128K16-XXX
FIG. 4 SRAM TIMING WAVEFORM - READ CYCLE
FIG. 5 SRAM WRITE CYCLE - SWE CONTROLLED
FIG. 6 SRAM WRITE CYCLE - SCS CONTROLLED
WS32K32-XHX
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White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com
WSF128K16-XXX
FLASH AC CHARACTERISTICS WRITE/ERASE/PROGRAM OPERATIONS, FWE CONTROLLED (VCC = 5.0V, TA = -55C TO +125C)
Parameter Symbol Min -70 Max Min -120 Max Unit
Write Cycle Time Chip Select Setup Time Write Enable Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time Chip Select Hold Time Write Enable Pulse Width High Duration of Byte Programming Operation (min) Chip and Sector Erase Time Read Recovery Time Before Write VCC Set-up Time Chip Programming Time Output Enable Setup Time Output Enable Hold Time (1)
tAVAV tELWL tWLWH tAVWL tDVWH tWHDX tWLAX tWHEH tWHWL tWHWH1 tWHWH2 tGHWL
tWC tCS tWP tAS tDS tDH tAH tCH tWPH
70 0 35 0 30 0 45 0 20 14 2.2 0 60
120 0 50 0 50 0 50 0 20 14 2.2 0 50 12.5 12.5 0 10 60
ns ns ns ns ns ns ns ns ns s sec s s sec ns ns
tVCS tOES tOEH
50 0 10
1. For Toggle and Data Polling.
FLASH AC CHARACTERISTICS READ ONLY OPERATIONS (VCC = 5.0V, TA = -55C TO +125C)
Parameter Symbol Min Max -70 Min Max -120 Unit
Read Cycle Time Address Access Time Chip Select Access Time OE to Output Valid Chip Select to Output High Z (1) OE High to Output High Z (1) Output Hold from Address, CS or OE Change, whichever is first
tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX
tRC tACC tCE tOE tDF tDF tOH
70 70 70 35 20 20 0
120 120 120 50 30 30 0
ns ns ns ns ns ns ns
1. Guaranteed by design, not tested.
White Electronic Designs Corporation * Phoenix AZ * (602) 437-1520
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WSF128K16-XXX
FLASH AC CHARACTERISTICS WRITE/ERASE/PROGRAM OPERATIONS, FCS CONTROLLED (VCC = 5.0V, TA = -55C TO +125C)
Parameter Symbol Min -70 Max Min -120 Max Unit
Write Cycle Time FWE Setup Time FCS Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time FWE Hold from FWE High FCS Pulse Width High Duration of Programming Operation Duration of Erase Operation Read Recovery before Write Chip Programming Time
tAVAV tWLEL tELEH tAVEL tDVEH tEHDX tELAX tEHWH tEHEL tWHWH1 tWHWH2 tGHEL
tWC tWS tCP tAS tDS tDH tAH tWH tCPH
70 0 35 0 30 0 45 0 20 14 2.2 0 12.5 60
120 0 50 0 50 0 50 0 20 14 2.2 0 12.5 60
ns ns ns ns ns ns ns ns ns s sec ns sec
7
White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com
WSF128K16-XXX
FIG. 7 AC WAVEFORMS FOR FLASH MEMORY READ OPERATIONS
White Electronic Designs Corporation * Phoenix AZ * (602) 437-1520
8
WSF128K16-XXX
FIG. 8 WRITE/ERASE/PROGRAM OPERATION, FLASH MEMORY FWE CONTROLLED
NOTES: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence.
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White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com
WSF128K16-XXX
FIG. 9 AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS FOR FLASH MEMORY
Notes: 1. SA is the sector address for Sector Erase.
White Electronic Designs Corporation * Phoenix AZ * (602) 437-1520
10
WSF128K16-XXX
FIG. 10 AC WAVEFORMS FOR DATA POLLING DURING EMBEDDED ALGORITHM OPERATIONS FOR FLASH MEMORY
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White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com
WSF128K16-XXX
FIG. 11 WRITE/ERASE/PROGRAM OPERATION FOR FLASH MEMORY, CS CONTROLLED
NOTES: 1. PA represents the address of the memory location to be programmed. 2. PD represents the data to be programmed at byte address. 3. D7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates the last two bus cycles of a four bus cycle sequence.
White Electronic Designs Corporation * Phoenix AZ * (602) 437-1520
12
WSF128K16-XXX
PACKAGE 400: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H1)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
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White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com
WSF128K16-XXX
PACKAGE 519: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G1U)
The WEDC 68 lead G1U CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G1U has the TCE and lead inspection advantage of the CQFP form.
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
White Electronic Designs Corporation * Phoenix AZ * (602) 437-1520
14
WSF128K16-XXX
ORDERING INFORMATION
W S F 128K16 - XXX X X X
LEAD FINISH:
Blank =Gold plated leads A = Solder dip leads
DEVICE GRADE:
M I C
= Military Screened = Industrial = Commercial
-55C to +125C -40C to +85C 0C to +70C
PACKAGE TYPE:
H1 H G1U
= 1.075" sq. Ceramic Hex In-line Package, HIP (Package 400) = 1.185" sq. Ceramic Hex In-line Package, HIP (Package 401) = 22.4 mm Ceramic Quad Flat Pack, CQFP (Package 519)
ACCESS TIME (ns)
37 72
= 35ns SRAM and 70ns FLASH = 70ns SRAM and 120ns FLASH
ORGANIZATION, 128K x 16 FLASH SRAM WHITE ELECTRONIC DESIGNS CORP.
DEVICE TYPE
128K x 16 Mixed Module 128K x 16 Mixed Module 128K x 16 Mixed Module 128K x 16 Mixed Module 128K x 16 Mixed Module 128K x 16 Mixed Module
SRAM SPEED
70ns 70ns 35ns 35ns 70ns 35ns
FLASH SPEED
120ns 120ns 70ns 70ns 120ns 70ns
PACKAGE
66 pin HIP (H) 66 pin HIP (H1) 66 pin HIP (H) 66 pin HIP (H1) 68 lead CQFP/J (G1U) 68 lead CQFP/J (G1U)
SMD NO.
5962-96900 01HXX 5962-96900 01HYX 5962-96900 02HXX 5962-96900 02HYX 5962-96900 01HX* 5962-96900 02HX*
*SMD Pending
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White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com

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