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| IS23SC4442 256 BYTE EEPROM WITH WRITE PROTECT FUNCTION AND PROGRAMMABLE SECURITY FEATURES * Standard CMOS process * 256 x 8 bits EEPROM organization * Byte-wise addressing * Irreversible byte-wise write protection of lowest 32 address (Byte 0..31) * 3-byte Programmable Security Code (PSC) for memory write/erase protection * 2.7-5.5V power supply for read and write/erase * Low power operation: 3 mA typical active current * 2.5 ms programming time * 2-wire serial interface * End of processing indication * ISO standard 7816 compatible * High reliability: ISSI PRELIMINARY INFORMATION August 2003 (R) DESCRIPTION IS23SC4442 contains 256 x 8 bits of EEPROM main memory and a 32 x 1 bit protection PROM memory. The main memory can be randomly accessed byte by byte. During memory erase, all 8 bits of a byte are set to logical one. During memory write, individual bit(s) are set to logical zeros depend on the data value to be written. Normally, a data change may consists of an erase and a write operation. The write or erase operation takes at least 2.5 ms to complete. The first 32 bytes (Address: 0 to 31) in memory are irreversibly protected by the corresponding 32 protect bits in the 32 x 1 bit protection memory. The 32 protect bits are onetime programmable, and they cannot be erased once they are set to logical zero. IS23SC4442 provides a 3-bit Error Counter (EC), and three bytes Programmable Security Code (PSC) to prevent unauthorized erase/write operation to the memory. All the memory, except the PSC, can be read after the chip is powered on. But, the memory can be written or erased only after the PSC is entered and verified correct. After three successive unsuccessful verifications of PSC, the Error Counter locks the chip from a further attempt, and the memory can never be erased or written. - 1,000,000 erase/write cycles guaranteed - 10 years data retention * Wide operating temperature range -30oC to 75oC Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. 00B 08/01/03 1 IS23SC4442 ISSI (R) PIN CONFIGURATION C1 C5 C2 C6 C3 C7 C4 C8 Definitions and Functions Card Contact C1 C2 C3 C4 C5 C6 C7 C8 Symbol VCC RST CLK NC GND NC I/O NC Description Supply Voltage Reset Clock Input No Connect Ground No Connect Bidirectional Data I/O (Open drain) No Connect Note: An external pull up resistor is needed to be connected to the I/O pin. 2 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. 00B 08/01/03 IS23SC4442 ISSI Main Memory (R) MEMORY OVERVIEW VCC Reset, Blockade Logic Sequencer and Security Logic High-Volt Generator 225 224 Byte Unprotected Data Memory RST CLK I/O Interface Protection Memory (PROM) 32 31 32 Byte Protectable Data Memory Manufacturer Code Decoder GND 0 Functional Description The IS23SC4442 works on a 2-wire serial transmission protocol. Data is input or output from the chip through the I/O pin at the falling edge of CLK. The following are the four modes of operations: - Reset and Answer-to-Reset - Command Mode - Outgoing Data Mode - Processing Mode Reset and Answer-to-Reset The Answer-to-Reset operation conforms to ISO 7816-3 ATR standard. The reset action can be invoked at any time during the operation to terminate any active command operation. With RST High, the internal address counter is set to zero by the CLK pulse. The LSB of the first byte data in the memory will be output from I/O when RST goes from High to Low. By continuing to send pluses to CLK, the contents of the first four bytes will be output from I/O pin. After the ATR process completes, the I/O pin will be set to high impedance. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. 00B 08/01/03 3 IS23SC4442 ISSI (R) FUNCTIONAL DESCRIPTION Block Diagram Main memory Protection memory 31 Security memory 255 EEPROM 256X8 3 Reference data 2 Reference data 32 31 Erase with PSC 1 Reference data 0 write 0 protection 0 EC addr. data 8 5 addr. data addr. data 2LSB memory High-voltage generator Bias current generator Vecoder Column sampling Addr. & data register comparator Programming Control Reset Timing security Interface VCC GND CLK I/O RST 4 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. 00B 08/01/03 IS23SC4442 ISSI (R) Functional Description The IS23SC4442 contains 256 bytes of EEPROM main memory (see block diagram) and a 32 bit protection memory. The main memory is byte-wise erased and written. When the memory is erased, 8 bits of the data byte are all set to logic 1. When the memory is written, a data byte can be programmed bit by bit, and it is set to logic 0 according to the logic between the old and new data. Generally, updating data includes an erase and write procedure. When updated, new input data and the contents of the old data are compared. If none of the 8 bits requires a logic 0 to 1 change, the erase operation will be skipped. On the contrary, the write operation will be skipped if no logic 1 to 0 change is necessary. The write and erase operation takes at least 2.5 ms each. The first 32 bytes can be protected individually by writing the corresponding bit in the protection memory. Each data byte in the address range and its assigned bit in the protection memory have the same address. Once the protection bit is written it cannot be erased. The security memory of IS23SC4442 contains an error counter (bit 0-bit 2) and 3 bytes reference data. The three bytes reference data are as a whole called programmable security code (PSC). After power on, except for the PSC, the whole memory can always be read. The error counter can always be written. After three successive unsuccessful PSC verifications, the error counter will block the chip, and write and erase operation to the memory will be forbidden. TRANSMISSION PROTOCOL Transmission Mode The transmission protocol is a two-wire link protocol between the interface device IFD and IC. The protocol type is "S = 10". All data changes on I/O are triggered by the falling edge on CLK. The transmission protocol is composed of the following four modes: - Reset and answer- to-reset - Command mode - Data output mode - Processing mode Reset and Answer-To-Reset According to IS07816-3, Answer-To-Reset takes place during operation. The reset can be implemented at any time. During reset, the address counter is set to zero. When RST is set from high level to low level, the lowest bit of the first byte is read on the I/O. Under continuous 31 clock pulses, the contents of the first 4 byte EEPROM addresses can be read out. The 33rd clock pulse sets the I/O to high impedance. During Answer-To-Reset, any start and stop condition is ignored. Vcc RST 1 2 3 31 32 IC sets I/O high impedance CLK I/O 1 2 3 31 32 Figure: Reset and Answer-To-Reset Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. 00B 08/01/03 5 IS23SC4442 ISSI on I/O - After receiving a command, there are two possible modes: - Processing mode for writing and erasing (R) Command Mode After Answer-To-Reset, IS23SC4442 waits for a command entry. Each command begins with a start condition, which includes a three bytes command entry, and it ends with a stop condition. - Start condition: during CLK in high level, a falling edge on I/O - Stop condition: during CLK in high level, a rising edge IFD sets I/O To L-level Command 1 2 3 23 24 CLK I/O 1 2 3 23 24 Start from IFD Stop from IFD Figure: Command Mode Data Output Mode When reading, the chip sends the data to IFD. The figure shows the timing diagram. After the first falling edge on CLK, the first bit on the I/O is valid. After the last data bit, an additional CLK pulse is necessary to set the I/O to a high level for receiving a new command. During this mode, any start and stop condition is ignored. IC set I/O to high-level Command n-1 CLK 1 2 3 n 1 2 3 n-1 n I/O Start of output data Figure: Data Output Mode 6 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. 00B 08/01/03 IS23SC4442 ISSI (R) Processing Mode During processing, the chip processes internally. The following Figure shows the timing diagram. The IFD sends clock to the chip continuously until the I/O us set to the high level that has been set to low level on the first falling edge of CLK. During this mode any start and stop condition is ignored. IFD sets I/O to level L Outgoing Data IC sets I/O To level Z Command RST is low level 0 1 24 0 1 2 n CLK I/O DI0 .. .. DI23 DO0 .. .. Don-1 DOn Start from IFD Stop From IFD Start of Outgoing Data IC sets I/O To level Z Processing CLK I/O 0 1 DI: Data In DO: Data Out Start of Processing End of Processing Figure : Sector Trailer (Block 3) Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. 00B 08/01/03 7 IS23SC4442 ISSI (R) COMMANDS Command Format IS23SC4442 provide seven commands that are listed on Table 1. Every command consists of three bytes. MSB CONTROL LSB MSD ADDRESS LSB B7 B6 B5 B4 B3 B2 B1 B0 A7 A6 A5 A4 A3 A2 A1 A0 Note: Command transmission begins with the control byte LSB. MSB DATA D7 D6 D5 D4 D3 D2 LSB D1 D0 Table 1 Control of Byte 1 B7 B6 B5 B4 B3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 B2 0 0 1 1 0 0 0 B1 B0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 Address Input Data Address of Byte 2 A7 ~ A0 Address Address Data of Byte 3 D7 ~ D0 Operation Read Main Memory Update Main Memory Read Protection Memory Write Protection Memory Read Main Memory Update Main Memory Compare Data Mode Data Output Processing Output Data Output Data Data Output Processing Processing Input Data Address Address Input Data Input Data Command Mode IFD sets I/O To Level L Command 0 1 24 CLK I/O B0 ... .. B7 A0 .. A7 D07 .. D7 Start from IFD Stop from IFD 8 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. 00B 08/01/03 IS23SC4442 ISSI provide sufficient clock pluses. The number of clock pulse = (256 - N) x 8+1. The main memory can always be read. (R) Read Main Memory The command reads out the memory contents from the given address (N) to the last address of the memory (with LSB first). After the command entry, the IFD has to Address (decimal) 255 Main Memory Data Byte 255 (D7 ...D0) Protection Memory Security Memory -- ---- Protection Bit 31 (D31) -- -- -- -- -- Reference Data Byte 1 (D7...D0) Error Counter : 32 31 : Data Byte 32 (D7 ... D0) Data Byte 31(D7 ... D0) : 1 0 : Data Byte 1 (D7 ... D0) Data Byte 0 (D7 ... D0) : Protection Bit 1 (D1) Protection Bit 0 (D0) Control B7 B6 B5 B4 B3 B2 B1 B0 Address A7... A0 Address 00 H ... FF H Data D7... D0 No Effect No Effect Binary Hexadecimal 0 0 1 1 0 0 0 0 30 H Command IFD set I/O to level L 24 Outgoing Data IC sets I/O To Level Z 1 10 0 1 0 CLK I/O B0 ... .. B7 ... D0 D1 .. D0 D1 .. D0 .. D7 Start from IFD Data of Startaddress Stop from IFD Start of Outgoing Data Data of Startaddress +1 Data of Startaddress 255 Figure: Read Main Memory Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. 00B 08/01/03 9 IS23SC4442 ISSI (R) Read Protection Memory The command reads out 32 bits to I/O on continuous 32 clock pulses. By an additional clock pulse, the I/O is set to high level. The protection memory can always be read. Address (decimal) 255 Main Memory Data Byte 255 (D7 ...D0) Protection Memory Security Memory -- -- -- Protection Bit 31 (D31) -- -- -- -- -- Reference Data Byte 1 (D7...D0) Error Counter : 32 31 : Data Byte 32 (D7 ... D0) Data Byte 31 (D7...D0) : 1 0 : Data Byte 1 (D7 ... D0) Data Byte 0 (D7 ... D0) : Protection Bit 1 (D1) Protection Bit 0 (D0) Control B7 B6 0 Address B2 1 Data D7... D0 No Effect No Effect B5 1 B4 1 34 B3 0 H B1 0 B0 0 A7... A0 No Effect Binary Hexadecimal 0 No Effect Command IFD set I/O to level L 24 24 Outgoing Data IC sets I/O To Level Z 1 0 1 0 32 CLK I/O B0 .. ... B7 D0 D1 ... .. D8 D9 .. D24 .. D31 Start from IFD Data of Byte 1 Stop from IFD Start of Outgoing Data Data of Byte 2 Data of byte 4 Figure: Read Protection Memory 10 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. 00B 08/01/03 IS23SC4442 ISSI (R) Read Security Memory The three bytes of reference data can only be read after successful PSC verification; otherwise, the output of the PSC will be suppressed and the I/O will be set to the low level. The error counter can always be read. The read out four bytes security memory requires 32 clock pulses, I/O is set to the high level by an additional pulse. Address (decimal) 255 Main Memory Data Byte 255 (D7 ...D0) Protection Memory Security Memory -- -- -- Protection Bit 31 (D31) -- -- -- -- -- Reference Data Byte 1 (D7...D0) Error Counter : 32 31 : Data Byte 32 (D7 ... D0) Data Byte 31(D7 ... D0) : 1 0 : Data Byte 1 (D7 ... D0) Data Byte 0 (D7 ... D0) : Protection Bit 1 (D1) Protection Bit 0 (D0) Control B7 B6 B5 B4 B3 B2 B1 B0 Address A7... A0 Data D7... D0 No Effect Binary Hexadecimal 0 0 1 1 0 0 0 1 No Effect No Effect 31 H No Effect Command IFD set I/O to level L 24 24 Outgoing Data IC sets I/O To Level Z 32 0 1 0 1 CLK I/O B0 ... .. ... X D0 D1 .. D8 D9 .. D24 .. D31 Start from IFD Data of Error Counter Stop from IFD Start of Outgoing Data Reference Data Byte 1 Reference Data byte 3 Figure: Read Security Memory Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. 00B 08/01/03 11 IS23SC4442 ISSI - Write only (2.5 ms) corresponding to m=124 clock pulses (R) Update Main Memory The command programs the addressed EEPROM byte with the given data byte. Depending on the old and the new data, one of the following operations will take place during processing mode. - Erase and write (5 ms) corresponding to m = 255 clock pulses - Erase only (2.5ms) corresponding to m=124 clock pulses (frequency of clock = 50 kHz) Command Processing 1 2 3 24 1 2 3 m m-2 m-1 CLK I/O RST 1 2 .. .. ... 24 ... Figure: Update Main Memory Address (decimal) 255 Main Memory Data Byte 255 (D7 ...D0) Protection Memory Security Memory -- -- -- Protection Bit 31 (D31) -- -- -- -- -- Reference Data Byte 1 (D7...D0) Error Counter : 32 31 : Data Byte 32 (D7 ... D0) Data Byte 31(D7 ... D0) : 1 0 : Data Byte 1 (D7 ... D0) Data Byte 0 (D7 ... D0) : Protection Bit 1 (D1) Protection Bit 0 (D0) Control B7 B6 B5 B4 B3 B2 B1 B0 Address A7... A0 Address Data D7... D0 Input Data Input Data Binary Hexadecimal 0 0 1 1 38 H 1 0 0 0 00 ...FF H H 12 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. 00B 08/01/03 IS23SC4442 ISSI Command IFD set I/O to level L 24 24 (R) Erase or Write Main Memory IC sets I/O To Level Z 254 Processing 0 1 0 1 CLK I/O B0 ... .. ... X Start from IFD Stop from IFD Start of Processing Figure 1 Command IFD set I/O to level L 24 24 Processing IC sets I/O To Level Z 123 0 1 0 1 CLK I/O B0 ... .. X ... Start from IFD Stop from IFD Start of Processing Figure 2 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. 00B 08/01/03 13 IS23SC4442 ISSI (R) Update Security Memory After the successful PSC verification, the reference data can be updated. Otherwise, only the error counter can be written. The processing time and the required clock pulses are the same as that of the update main memory. Control B7 B6 B5 B4 B3 B2 B1 B0 Address A7... A0 Address Data D7... D0 Input Data Input Data Binary Hexadecimal 0 0 1 1 39 H 1 0 0 1 00 ...03 H H Write Protection Memory The execution of this command includes a comparison of the given data byte and the assigned byte in the main memory. If the result is data identity, the protection bit is written so the corresponding data byte in the main memory is unchangeable. If the result is differences, the protection bit cannot be written. The execution time and clock pulses are the same as that of the update main memory. Address (decimal) 255 Main Memory Data Byte 255 (D7 ...D0) Protection Memory Security Memory -- -- -- Protection Bit 31 (D31) -- -- -- -- -- Reference Data Byte 1 (D7...D0) Error Counter : 32 31 : Data Byte 32 (D7 ... D0) Data Byte 31(D7 ... D0) : 1 0 : Data Byte 1 (D7 ... D0) Data Byte 0 (D7 ... D0) : Protection Bit 1 (D1) Protection Bit 0 (D0) Control B7 B6 B5 B4 B3 B2 B1 B0 Address A7... A0 Address Data D7... D0 Input Data Input Data Binary Hexadecimal 0 0 1 1 1 1 0 0 3C H 00 ...1F H H 14 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. 00B 08/01/03 IS23SC4442 ISSI (R) Compare Verification Data Only after the error counter has written one bit, can the procedure and compare verification data be executed. The command compares the given verification data byte with the corresponding reference data byte. Control B7 B6 B5 B4 B3 B2 B1 B0 Address A7... A0 Address Data D7... D0 Input Data Input Data Binary Hexadecimal 0 0 1 1 33 H 0 0 1 1 00 ...03 H H IFD set I/O to level L Command 0 1 2 IC sets I/O To Level Z 0 24 1 2 CLK I/O B0 ... .. A0 .. D0 .. D7 Start from IFD Address1 Byte1 Address2 Byte2 Address3 Byte3 Stop from IFD Start of Processing Figure: Compare Verification data Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. 00B 08/01/03 15 IS23SC4442 ISSI (R) Usage of the Compare Command The following procedure must be completed exactly as described. Any variation to the procedure can results in a failure, so that a write and erase can not be accessed. If the procedure cannot successful complete, only the error counter can be written that means one to zero but it cannot be erased. First of all, an error counter bit has to be written to zero by an update security memory command. Thereafter, a successful execution of three compare verification Command Control B7....B0 Read Security Memory Update Security Memory 31H 39H Address A7...A0 commands from byte 1 to byte 3 makes erasing the error counter possible. Write and erase access to all memory areas is possible; as long as, the operation voltage is applied. If an error takes place, the whole reference data can be updated like any other information in the main memory. As transported, the PSC is coded with the individual agreement with the customer. Knowing the code is indispensable to alter data. Data D7...D0 Not Effect Input Data Check Error Counter Write Free Bit in Error Counter Input Data 0000 0dd Binary Remark No Effect 00H Compare Verification Data Compare Verification Data Compare Verification Data Update Security Memory Read Security Memory 33H 33H 33H 39H 31H 01H 02H 03H 00H No Effect Input Data Input Data Input Data FFH No Effect Reference Data Byte 1 Reference Data Byte 2 reference Data Byte 3 Erase Error Counter Check Error Counter 16 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. 00B 08/01/03 IS23SC4442 ISSI Verification Procedure Read EC Read SM ... . ... . (R) Verification Procedure Comparison Blocked Y (EC) =000? N write one bit of EC to "0" Compare VD,ref, D Update SM Address Data Compare VD Address Byte 1 Compare VD Address Byte 2 Compare VD Address Byte 3 Update SM Addr. 0 Read SM ... . 111111111 .... Erase EC Number of comparision unsuccessful "1" = number of posible retries N Read EC (EC) =111? Y EC = error counter SM = security memory VD = verification data Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. 00B 08/01/03 17 IS23SC4442 ISSI Break (R) RESET MODE Reset and Answer-To-Reset If RST is set on the high level while CLK is set on the low level, the operation is aborted and the I/O is switched to the high level. To trigger a defined valid reset, the necessary minimum duration is tRES = 5 ms. After break, the IC is ready for further operations. Power on Reset After power on, the I/O is set to the high level. A read operation or an Answer-To-Reset command must be carried out before any data can be altered. RST CLK I/O tRES Figure: Break Failures Behavior of failures: In case of one of the following failures, the chip sets the I/O to the high level after 8 clock pulses. Possible failures: - Comparison unsuccessful - Wrong number of command clock pulses - Write/erase access to already protected bytes - Rewrite and erase a protection bit Coding of the Chip For security purposes, every chip is irreversibly coded by a scheme. This way fraud and misuse is excluded. For example, Figure a and Figure b show ATR and Directory Data of Structure 1. When transported, the ATR header, ICM and ICT are programmed. Shanghai Belling Microelectronics Mfg. CO., Ltd. programs the IC manufacturer identifier (ICM), IC type (ICT)... Belling programs other code depending on the customer agreement. 18 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. 00B 08/01/03 IS23SC4442 ISSI (R) Synchronous Transmission ATR and Directory Data ATR head 1 1 1 1 1 1 ATR data 1 1 5 4 1 1 DIR data 6 1 1 1 1 1 Application file H1 H2 H3 H4 TM LM ICM ICT ICCF ICCSN TT LT TA LA AID TD LD AP LA LD LM LT Figure a AID AP Application identifier Appl. personalizer identifier ICCF ICCSN ICM ICT LA LD Card Fabricator id. Card serial number IC manufacturer IC manufacturer Length of AID Length of data LM LT TA TD TM TT Length of manufacture data Length of application template Tag of AZD Tag of discretionary data Tag of manufacturer data Tag of application data ATR Answer-to-Reset DIR Directory H1, H2 Protocol bytes H3, H4 ATR historical bytes Output Mode protocol bytes acc. to ISO7816-3 protocol type H1 protocol parameter H2 Historical bytes acc. to ISO7816-4 category indicator H3 DIR data referemce b8 b7 b6 b5 b4 b3 b2 b1 b8 b7 b6 b5 b4 b3 b2 b1 b8 b7 b6 b5 b4 b3 b2 b1 b8 b7 b6 b5 b4 b3 b2 b1 10100010000100110001000010010001 Protocol typeS RFU structure id 0-7 = defined by ISO 8-E =not def.by ISO 8 =serial data access protocol 9=3 wire bus protocol A=2 wire bus protocol F=RFU number of data units Length of data units in bits (2xx) category indicator acc. to ISO 786-4 b8 = 1 b7-b1 = reference of DIR data b8 = 0 b7-b1 = out of ISO7816-4 RFU 000 = no indication 001 = 128 010 = 256 100 = 1024 101 = 2048 111 = RFU 0: read to end 1: read with defined length 00 = definee by ISO 10 = structure 1 01 = structure 2 not def. by ISO 11 = structure 3 1: specify DIR data ref. 0: not specify DIR data ref. Figure b Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. 00B 08/01/03 19 IS23SC4442 ISSI Symbol VCC V1 TSTG TTOT Ta Min. -0.3 -0.3 -40 (R) ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Supply Input voltage Storage temperature Power Dissipation Temperature Limits Typ. -- -- -- -- -- Unit Max. 6 6 125 70 75 V V O C mW O C 0 -30 Absolute Maximum Ratings Parameter Supply Supply Voltage Supply Current Data Input H input Voltage (I/O, CLK, RST, SELECT) L input Voltage (I/O, CLK RST, SELECT) H input current (I/O, CLK, RST) Data Output (I/O) L output current H current leakage Capacitance Input capacitance Symbol Min. VCC ICC VH VL IH IL IH CI 2.7 -- VCC-1 VGND-0.2 -- 1 -- -- Limits Typ. 5 3 -- -- -- -- -- -- Unit Max 5.5 10 VCC+0.3 VGND+0.8 50 -- 50 10 V mA V V A mA A pF 20 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. 00B 08/01/03 IS23SC4442 ISSI Symbol CLK tH tL tR tF td1 td2 td3 td5 td7 td8 tRES td9 tER Twr tbuf Min. 7 9 9 Limits Max 50 Unit kHz s s s s s s s s s s s s ms ms s (R) AC Characteristics Parameter Clock frequency Clock High period Clock Low period Rise Time Full Time Start Condition hold time Delay Time Stop condition, setup time Data hold time Data setup time Start condition, setup time Reset Delay Time Erase Time Write Time Interval before new start condition Notes: *f = 50kHz 1 1 4 2.5 4 1 1 4 5 2.5 2.5* 2.5* 10 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. 00B 08/01/03 21 |
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