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ispLSI 5256VE
(R)
In-System Programmable 3.3V SuperWIDETM High Density PLD Features
* Second Generation SuperWIDE HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC DEVICE -- 3.3V Power Supply -- User Selectable 3.3V/2.5V I/O -- 12000 PLD Gates / 256 Macrocells -- Up to 144 I/O Pins -- 256 Registers -- High-Speed Global Interconnect -- SuperWIDE Generic Logic Block (32 Macrocells) for Optimum Performance -- SuperWIDE Input Gating (68 Inputs) for Fast Counters, State Machines, Address Decoders, etc. -- PCB Efficient Ball Grid Array (BGA) Package Options -- Interfaces with Standard 5V TTL Devices * HIGH PERFORMANCE E2CMOS(R) TECHNOLOGY -- fmax = 165 MHz Maximum Operating Frequency -- tpd = 6.0 ns Propagation Delay -- TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels -- Electrically Erasable and Reprogrammable -- Non-Volatile -- Programmable Speed/Power Logic Path Optimization * IN-SYSTEM PROGRAMMABLE -- Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality -- Reprogram Soldered Devices for Faster Debugging * 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND 3.3V IN-SYSTEM PROGRAMMABLE * ARCHITECTURE FEATURES -- Enhanced Pin-Locking Architecture with SingleLevel Global Routing Pool and SuperWIDE GLBs -- Wrap Around Product Term Sharing Array Supports up to 35 Product Terms Per Macrocell -- Macrocells Support Concurrent Combinatorial and Registered Functions -- Macrocell Registers Feature Multiple Control Options Including Set, Reset and Clock Enable -- Four Dedicated Clock Input Pins Plus Macrocell Product Term Clocks -- Programmable I/O Supports Programmable Bus Hold, Pull-up, Open Drain and Slew Rate Options -- Four Global Product Term Output Enables, Two Global OE Pins and One Product Term OE per Macrocell
Functional Block Diagram
Input Bus
Generic Logic Block
Input Bus
Generic Logic Block
Boundary Scan Interface
Generic Logic Block
Generic Logic Block
Input Bus
Input Bus
Global Routing Pool (GRP)
Generic Logic Block Generic Logic Block
Input Bus
Input Bus
Generic Logic Block
Generic Logic Block
Input Bus
Input Bus
ispLSI 5000VE Description
The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routing Pool (GRP) between the GLBs. Switching resources are provided to allow signals in the Global Routing Pool to drive any or all the GLBs in the device. This mechanism allows fast, efficient connections across the entire device. Each GLB contains 32 macrocells and a fully populated, programmable AND-array with 160 logic product terms and three extra control product terms. The GLB has 68 inputs from the Global Routing Pool which are available in both true and complement form for every product term. The 160 product terms are grouped in 32 sets of five and sent into a Product Term Sharing Array (PTSA) which allows sharing up to a maximum of 35 product terms for a single function. Alternatively, the PTSA can be bypassed for functions of five product terms or less. The three extra product terms are used for shared controls: reset, clock, clock enable and output enable.
Copyright (c) 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
January 2002
5256ve_10
1
Specifications ispLSI 5256VE
Functional Block Diagram
Figure 1. ispLSI 5256VE Functional Block Diagram (144-I/O Option)
I/O 143 I/O 142 I/O 141 I/O 140 I/O 129 I/O 128 I/O 127 I/O 126 I/O 125 I/O 124 I/O 123 I/O 122 I/O 111 I/O 110 I/O 109 I/O 108
GOE0 GOE1
Input Bus
Generic Logic Block
Input Bus
Generic Logic Block
Boundary Scan Interface
TMS
TCK
TDI TDO
VCCIO 1TOE I/O 1 I/O 2 I/O 3
Generic Logic Block
Input Bus
I/O 107 I/O 106 I/O 105 I/O 104
Generic Logic Block
Input Bus
I/O 14 I/O 15 I/O 16 I/O 17
I/O 93 I/O 92 I/O 91 I/O 90
Generic Logic Block
Input Bus
I/O 18 I/O 19 I/O 20 I/O 21
Global Routing Pool (GRP)
Generic Logic Block
I/O 89 I/O 88 I/O 87 I/O 86
Input Bus
I/O 32 I/O 33 I/O 34 I/O 35
I/O 75 I/O 74 I/O 73 I/O 72
Generic Logic Block
Generic Logic Block
Input Bus
RESET
Input Bus
I/O 54 I/O 55 I/O 56 I/O 57
CLK 0 CLK 1 1CLK 2 1CLK 3
I/O 36 I/O 37 I/O 38 I/O 39
1. CLK2, CLK3 and TOE signals are shared with I/O signals. Use the table below to determine which I/O is shared by package type.
Package Type 100 TQFP 128 TQFP 256 fpBGA 272 BGA
I/O 50 I/O 51 I/O 52 I/O 53
1/O 44 / CLK2 I/O 59 / CLK2 I/O 119 / CLK2 I/O 119 / CLK2
Multplexed Signals I/O 49 / CLK 3 I/O 65 / CLK3 I/O 131 / CLK3 I/O 131 / CLK3
I/O 68 I/O 69 I/O 70 I/O 71
I/O 0 / TOE I/O 0 / TOE I/O 0 / TOE I/O 0 / TOE
2
Specifications ispLSI 5256VE
ispLSI 5000VE Description (Continued)
The 32 registered macrocells in the GLB are driven by the 32 outputs from the PTSA or the PTSA bypass. Each macrocell contains a programmable XOR gate, a programmable register/latch and the necessary clocks and control logic to allow combinatorial or registered operation. The macrocells each have two outputs, combinatorial and registered. This dual output capability from the macrocell allows efficient use of the hardware resources. One output can be a registered function for example, while the other output can be an unrelated combinatorial function. A direct register input from the I/O pad facilitates efficient use of this feature to construct high-speed input registers. Macrocell registers can be clocked from one of several global or product term clocks available on the device. A global and product term clock enable is also available to each register, eliminating the need to gate the clock to the macrocell registers. Reset for the macrocell register is provided from the global signal, its polarity is userselectable. The macrocell register can be programmed to operate as a D-type register or a D-type latch. The 32 outputs from the GLB can drive both the Global Routing Pool and the device I/O cells. The Global Routing Pool contains one input from each macrocell output and one input from each I/O pin. The input buffer threshold has programmable TTL/3.3V/ 2.5V compatible levels. The output driver can source 4mA and sink 8mA in 3.3V mode. The output drivers have a separate VCCIO reference input which is independent of the main VCC supply for the device. This feature allows individual output drivers to drive either 3.3V (from the device VCC) or 2.5V (from the VCCIO pin) output levels while the device logic and the output current drive are powered from device supply (VCC). The output drivers also provide individually programmable edge rates and open drain capability. A programmable pullup resistor is provided to tie off unused inputs. Additionally, a programmable bus-hold latch is available to hold tristate outputs in their last valid state until the bus is driven again by some device. Table 1. ispLSI 5000VE Family
Package Type Device ispLSI 5128VE ispLSI 5256VE ispLSI 5384VE ispLSI 5512VE GLBs 4 8 12 16 Macrocells 100 TQFP 128 256 384 512 -- 72 I/O -- -- 128 TQFP 96 I/O 96 I/O -- -- 256 fpBGA -- 144 I/O 192 I/O 192 I/O 272 BGA -- 144 I/O 192 I/O 192 I/O 388 fpBGA -- -- -- 256 I/O 388 BGA -- -- -- 256 I/O
The ispLSI 5000VE Family features 3.3V, non-volatile insystem programmability for both the logic and the interconnect structures, providing the means to develop truly reconfigurable systems. Programming is achieved through the industry standard IEEE 1149.1-compliant Boundary Scan interface. Boundary Scan test is also supported through the same interface. An enhanced, multiple cell security scheme is provided that prevents reading of the JEDEC programming file when secured. After the device has been secured using this mechanism, the only way to clear the security is to execute a bulk-erase instruction.
ispLSI 5000VE Family Members
The ispLSI 5000VE Family ranges from 128 macrocells to 512 macrocells and operates from a 3.3V power supply. All family members will be available with multiple package options. The ispLSI 5000VE Family device matrix showing the various bondout options is shown in the table below. The interconnect structure (GRP) is very similar to Lattice's existing ispLSI 1000, 2000 and 3000 families, but with an enhanced interconnect structure for optimal pin locking and logic routing. This eliminates the need for registered I/O cells or an Output Routing Pool. The ispLSI 5000VE encompasses the innovative features of the ispLSI 5000VA family with several enhancements. The macrocell is optimized and the Ttype flip flop option is removed. To improve the efficiency of design fits, the Product Term Reset Logic is simplified and the polarity option as well as the Global Preset function are removed. The programmable output-delay feature (skew option) is also removed. As a result, the ispLSI 5000VE is not JEDEC compatible with the ispLSI 5000VA. ispLSI 5000VA and 5000VE pinouts may differ in the same package, however all programming and power/ground pins are located in the same locations.
3
Specifications ispLSI 5256VE
Figure 2. ispLSI 5256VE Block Diagram (144 I/O Version)
18 CLK2 18 I/O Q D 32 GLB4 32 18 32 GLB3
18 32 32 D Q 32 18 18 I/O
160 3 PT 3 160 PT 160 68 68
160 160 PT 160 3 PT 3
18 CLK3 18 I/O Q D 32 GLB5 32 18 32 GLB2
18 32 32 D Q 32 18 18 I/O
160 3 PT 3 160 PT 160 68 68
160 160 PT 160 3 PT 3
18 18 I/O Q D 32 GLB6 32 18 32 GLB1
18 32 32 D Q 32 18 18 I/O
160 3 PT 3 160 PT 160 68 68
160 160 PT 160 3 PT 3
18 18 I/O Q D 32 GLB7 32 18 32 GLB0
18 32 32 D Q 32 18 18 I/O IO0/TOE
400 160 3 PT 3 160 PT 160 68 68 160 160 PT 160 3 PT 3
CLK0 CLK1 GOE0 GOE1 RESET
4
Specifications ispLSI 5256VE
Figure 3. ispLSI 5000VE Generic Logic Block (GLB)
From GRP 012 66 67 Global PTOE Bus PTSA PT 0 PT 1 PT 2 PT 3 PT 4 PTOE PT Clock PT Reset PT Preset Shared PT Clock Shared PT Reset Global PTOE 0 ... 3 To GRP PTSA bypass
Macrocell 0
From PTSA To I/O Pad
4 PT 9 PT 8 PT 7 PT 6 PT 5
Macrocell 1
From PTSA PTSA bypass To I/O Pad
PTOE PT Clock PT Reset PT Preset Shared PT Clock Shared PT Reset Global PTOE 0 ... 3 To GRP
4
PT 79 PT 78 PT 77 PT 76 PT 75
Macrocell 15
From PTSA PTSA bypass To I/O Pad
PTOE PT Clock PT Reset PT Preset Shared PT Clock Shared PT Reset Global PTOE 0 ... 3 To GRP
4
PT 159 PT 158 PT 157 PT 156 PT 155
Macrocell 31
From PTSA PTSA bypass To I/O Pad
PTOE PT Clock PT Reset PT Preset PT 160 PT 161 PT 162 4 Shared PT Clock Shared PT Reset Global PTOE 0 ... 3 To GRP
5
Specifications ispLSI 5256VE
Figure 4. ispLSI 5000VE Macrocell
VCCIO
Global PTOE 0 Global PTOE 1 Global PTOE 2 Global PTOE 3
VCC
VCCIO
PTOE GOE0 GOE1
TOE
PTSA bypass I/O Pad D Q Slew rate PT Clock Clk En 2.5V/3.3V Output R/L
Shared PT Clock CLK0 CLK1 CLK2 CLK3
PTSA
Open drain To GRP
Input threshold 2.5V/3.3V To GRP
Clk RP
PT Reset Shared PT Reset
Global Reset
PT Preset speed/ power
Note: Not all macrocells have I/O pads.
6
Specifications ispLSI 5256VE
Global Clock Distribution
The ispLSI 5000VE Family has four dedicated clock input pins: CLK0 - CLK3. CLK0 input is used as the dedicated master clock that has the lowest internal clock skew with no clock inversion to maintain the fastest internal clock Figure 5. ispLSI 5000VE Global Clock Structure
CLK 0 (dedicated pin) CLK 1 (dedicated pin) CLK0
speed. The clock inversion is available on the remaining CLK1 - CLK3 signals. By sharing the pins with the I/O pins, CLK2 and CLK3 can not only be inverted but are also available for logic implementation through GRP signal routing. Figure 5 shows these different clock distribution options.
CLK1
IO/CLK 2 (shared pin)
to/from GRP CLK2
CLK3
IO/CLK 3 (shared pin) RESET (dedicated pin)
to/from GRP
Global Reset
IO0/TOE (shared pin)
to/from GRP TOE
7
Specifications ispLSI 5256VE
Figure 6. Boundary Scan Register Circuit for I/O Pins
HIGHZ EXTEST SCANIN (from previous cell) 1 0 EXTEST PROG_MODE Normal Function D Q D Q TOE Normal Function OE 0 1
BSCAN Registers D Q
BSCAN Latches D Q
0 I/O Pin 1
1 0
1 0 D Q SCANOUT (to next cell)
Shift DR
Clock DR
Update DR
Reset
Figure 7. Boundary Scan Register Circuit for Input-Only Pins
Input Pin SCANIN (from previous cell) Shift DR Clock DR 0 1 D Q SCANOUT (to next cell)
8
Specifications ispLSI 5256VE
Figure 8. Boundary Scan Waveforms and Timing Specifications
TMS
TDI Tbtsu Tbtch TCK Tbtcl Tbth Tbtcp
Tbtvo TDO Valid Data
Tbtco Valid Data
Tbtoz
Tbtcpsu Data to be captured
Tbtcph Data Captured
Tbtuov Data to be driven out
Tbtuco Valid Data
Tbtuoz Valid Data
SYMBOL tbtcp tbtch tbtcl
tbtsu tbth trf tbtco tbtoz tbtvo tbtcpsu tbtcph tbtuco tbtuoz tbtuov
PARAMETER
TCK [BSCAN test] clock pulse width TCK [BSCAN test] pulse width high TCK [BSCAN test] pulse width low TCK [BSCAN test] setup time TCK [BSCAN test] hold time TCK [BSCAN test] rise and fall time TAP controller falling edge of clock to valid output TAP controller falling edge of clock to data output disable TAP controller falling edge of clock to data output enable BSCAN test Capture register setup time BSCAN test Capture register hold time BSCAN test Update reg, falling edge of clock to valid output BSCAN test Update reg, falling edge of clock to output disable BSCAN test Update reg, falling edge of clock to output enable
MIN 125 62.5 62.5 25 25 50 - - - 25 25 - - -
MAX UNITS - - - - - - 25 25 25 - - 50 50 50 ns ns ns ns ns mV/ns ns ns ns ns ns ns ns ns
9
Specifications ispLSI 5256VE
Absolute Maximum Ratings 1, 2
Supply Voltage Vcc .................................. -0.5 to +5.4V Input Voltage Applied ............................... -0.5 to +5.6V Tri-Stated Output Voltage Applied ........... -0.5 to +5.6V Storage Temperature ................................ -65 to 150C Case Temp. with Power Applied .............. -55 to 125C Max. Junction Temp. (TJ) with Power Applied ... 150C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). 2. Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement.
DC Recommended Operating Condition
SYMBOL PARAMETER Supply Voltage I/O Reference Voltage Commercial Industrial TA = 0C to +70C TA = -40C to +85C MIN. 3.00 3.00 2.3 MAX. 3.60 3.60 3.60 UNITS V V V
Table 2-0005/5KVE
VCC VCCIO
Capacitance (TA=25C,f=1.0 MHz)
SYMBOL PARAMETER I/O Capacitance Clock Capacitance Global Input Capacitance TYPICAL 10 10 10 UNITS pf pf pf TEST CONDITIONS VCC = 3.3V, VI/O = 0.0V VCC = 3.3V, VCK = 0.0V VCC = 3.3V, VG = 0.0V
Table 2-0006/5KVE
C1 C2 C3
Erase Reprogram Specification
PARAMETER ispLSI Erase/Reprogram Cycles MINIMUM 10000 MAXIMUM - UNITS Cycles
Table 2-0008/5KVE
10
Specifications ispLSI 5256VE
Switching Test Conditions
Figure 9. Test Load
Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Ouput Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. GND to VCCIOmin 1.5ns 10% to 90% 1.5V 1.5V See Figure 9
Table 2-0003/5KVE
VCCIO R1 Device Output R2 C L* Test Point
Output Load Conditions (See Figure 9)
3.3V TEST CONDITION A B Active High Active Low Active High to Z at VOH -0.5V Active Low to Z at VOL+0.5V Slow Slew R1 316 316 316 R2 348 348 348 R1 511 511 511 2.5V R2 CL 475 35pF 475 35pF 475 35pF 5pF 5pF 35pF
*CL includes Test Fixture and Probe Capacitance.
0213D
C D
Table 2-0004A/5KVE
DC Electrical Characteristics for 3.3V Range1
Over Recommended Operating Conditions
SYMBOL PARAMETER I/O Reference Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VCCIO = min, IOL = 8 mA VCCIO = min, IOH = -4 mA CONDITION MIN. 3.0 -0.3 2.0 - 2.4 TYP. - - - - - MAX. UNITS 3.6 0.8 5.25 0.4 - V V V V V
VCCIO VIL VIH VOL VOH
1. I/O voltage configuration must be set to VCC.
Table 2-0007/5KVE
11
Specifications ispLSI 5256VE
DC Electrical Characteristics for 2.5V Range1
Over Recommended Operating Conditions
SYMBOL PARAMETER I/O Reference Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
VCCIO=min, IOL= 100A VCCIO=min, IOL= 2mA VCCIO=min, IOH= -100A VCCIO=min, IOH= -2mA
CONDITION
MIN. 2.3 -0.3 1.7 - - 2.1 1.8
TYP. - - - - - - -
MAX. UNITS 2.7 0.7 5.25 0.2 0.6 - - V V V V V V V
2.5V/5KVE
VCCIO VIL VIH VOL VOH
1. I/O voltage configuration must be set to VCCIO.
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL PARAMETER Input or I/O Low Leakage Current Input or I/O High Leakage Current
1
CONDITION 0V VIN VIL(Max.) (VCCIO-0.2)V VIN VCCIO VCCIO VIN 5.25V 0V VIN VIL VIN = VIL(max) VIN = VIH(min) 0V VIN VCCIO 0V VIN VCCIO All I/Os Pulled-up, (Total I/Os * IPUmax)
MIN. - - - - 40 -40 - - VIL -
TYP. - - - - - - - - - -
MAX. UNITS -10 10 50 -200 - - 550 -550 VIH 30 A A A A A A A A V mA
DC Char_5KVE
IIL IIH IPU IBHL IBHH IBHLO IBHLH IBHT IVCCIO
I/O Active Pullup Current Bus Hold Low Sustaining Current Bus Hold High Sustaining Current Bus Hold Low Overdrive Current Bus Hold High Overdrive Current Bus Hold Trip Points Current Needed for VCCIO Pin
1. Pullup is capable of pulling to a minimum voltage of VOH under no-load conditions.
12
Specifications ispLSI 5256VE
External Switching Characteristics
Over Recommended Operating Conditions
PARAM. TEST3 COND.
DESCRIPTION Data Prop. Delay, 5PT Bypass Data Propagation Delay Clock Frequency with Internal Feedback Clock Frequency, Max Toggle
2 1
4,5
-165 -- -- 165 118 200 4.0 -- 0.0 5. 5 0. 0 2.5 0. 5 -- 4.0 -- -- -- -- 2.5 2.5 6.0 7.5 -- -- -- -- 3. 0 -- -- -- -- -- 8.0 -- 7.0 12.0 4.5 7.5 -- -- -- --
-125 7.5 9.5 -- -- -- -- 4.5 -- -- -- -- -- 10.0 -- 8.5 14.0 5.5 10.5 -- --
MIN. MAX. MIN. MAX.
UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tpd16 tpd26 fmax fmax (Ext.) fmax (Tog.) tsu1 tco16 th1 tsu2 th2 tsu3 th3 tr1 trw17 tpten/dis6 tgpten/dis6 tgen/dis tten/dis twh twl
6 6
A A A -- -- -- A -- -- -- -- -- A -- B/C B/C B/C B/C -- --
125 87 167 5.0 -- 0.0 7.0 0.0 3.5 0.5 -- 5.0 -- -- -- -- 3.0 3.0
Clock Freq. with Ext. Feedback,1/(tsu2 + tco1) GLB Reg. Setup Time before Clk, 5PT bypass GLB Reg. Clock to Output Delay GLB Reg. Hold Time after Clock, 5PT bypass GLB Reg. Setup Time before Clock GLB Reg. Hold Time after Clock GLB Reg. Setup Time before Clock, Input Reg. Path GLB Reg. Hold Time after Clock, Input Reg. Path Ext. Reset Pin to Output Delay Ext. Reset Pulse Duration Local Product Term Output Enable/Disable Global Product Term Output Enable/Disable Global OE Input to Output Enable/Disable Test OE Input to Output Enable/Disable Ext. Sync. Clock Pulse Duration, High Ext. Sync. Clock Pulse Duration, Low
Timing Ext.5256ve1.eps 1. Standard 16-bit counter using GRP feedback. 2. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. Timing v.2.0 3. Reference Switching Test Conditions section. 4. Unless noted otherwise, all timing numbers are taken with worst case PTSA fanout, a GRP load of 1 GLB, CLK0, and highspeed AND array. 5. Timing parameters measured using normal active output driver. 6. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is used as I/O voltage reference. 7. Pulse widths less than minimum may cause unknown output behavior.
13
Specifications ispLSI 5256VE
External Switching Characteristics
Over Recommended Operating Conditions
PARAM. TEST3 COND.
DESCRIPTION 4,5 Data Prop. Delay, 5PT Bypass Data Propagation Delay Clock Frequency with Internal Feedback Clock Frequency, Max Toggle
2 1
-100 -- -- 100 67 125 7.0 -- 0.0 9.0 0.0 4.5 1.0 -- 6.5 -- -- -- -- 4.0 4.0 10.0 12.0 -- -- -- -- 6.0 -- -- -- -- -- 11.5 -- 10.0 15.5 7.5 11.5 -- -- -- -- 80 56
-80 12.0 15.0 -- -- -- -- 7.0 -- -- -- -- -- 13.0 -- 12.0 17.0 9.0 12.5 -- --
MIN. MAX. MIN. MAX.
UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tpd16 tpd26 fmax fmax (Ext.) fmax (Tog.) tsu1 tco16 th1 tsu2 th2 tsu3 th3 tr1 trw17 tpten/dis6 tgpten/dis6 tgen/dis6 tten/dis twh twl
6
A A A -- -- -- A -- -- -- -- -- A -- B/C B/C B/C B/C -- --
Clock Freq. with Ext. Feedback,1/(tsu2 + tco1) GLB Reg. Setup Time before Clk, 5PT bypass GLB Reg. Clock to Output Delay GLB Reg. Hold Time after Clock, 5PT bypass GLB Reg. Setup Time before Clock GLB Reg. Hold Time after Clock GLB Reg. Setup Time before Clock, Input Reg. Path GLB Reg. Hold Time after Clock, Input Reg. Path Ext. Reset Pin to Output Delay Ext. Reset Pulse Duration Local Product Term Output Enable/Disable Global Product Term Output Enable/Disable Global OE Input to Output Enable/Disable Test OE Input to Output Enable/Disable Ext. Sync. Clock Pulse Duration, High Ext. Sync. Clock Pulse Duration, Low
100 8.0 -- 0.0 11.0 0.0 5.5 1.0 -- 8.0 -- -- -- -- 5.0 5.0
Timing Ext.5256ve2.eps 1. Standard 16-bit counter using GRP feedback. 2. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. Timing v.2.0 3. Reference Switching Test Conditions section. 4. Unless noted otherwise, all timing numbers are taken with worst case PTSA fanout, a GRP load of 1 GLB, CLK0, and highspeed AND array. 5. Timing parameters measured using normal active output driver. 6. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is used as I/O reference. 7. Pulse widths less than minimum may cause unknown output behavior. used as I/O voltage reference.
14
Specifications ispLSI 5256VE
Internal Timing Parameters
Over Recommended Operating Conditions
PARAMETER In/Out Delays DESCRIPTION Input Buffer Delay Global Clock Buffer Input Delay (clk0) Global Reset Pin Delay Global OE Pin Delay Output Buffer Delay Output Enable Delay Output Disable Delay GRP and Logic Delay 5-pt Bypass Propagation Delay Combinatorial Propagation Delay Product Term Sharing Array Internal Feedback Delay Input Buffer to Macrocell Register Delay Register Setup Time Register Setup Time (Product Term Clock) Register Hold Time Register Clock to GLB Output Delay Latch Setup Time Latch Hold Time Latch Gate to GLB Output Delay GLB Latch propagation Delay Clock Enable Setup Time Clock Enable Hold Time Asynchronous Set/Reset to GLB Output Delay Asynchronous Set/Reset Recovery Time Macrocell PT Clock Delay Block PT Clock Delay Macrocell PT Set/Reset Delay Block PT Set/Reset Delay Macrocell PT OE Delay Global PT OE Delay -165 -125 -100 -80 MIN MAX MIN MAX MIN MAX MIN MAX UNIT - - - - - - - - - - - - - 0.6 0.6 2.4 - 0.6 2.4 - - 4.1 0.9 - 0.8 - - - - - - 0.6 0.7 4.9 3.2 1.9 1.3 1.3 3.2 0.3 0.0 1.8 0.0 2.0 - - - 0.4 - - 0.4 1.0 - - 1.2 - 0.4 1.4 2.1 3.1 1.9 6.9 - - - - - - - - - - - - - 1.0 1.0 3.0 - 1.0 3.0 - - 4.3 1.7 - 1.2 - - - - - - 1.3 1.3 6.6 3.9 2.2 1.6 1.6 3.6 0.4 0.0 2.4 0.0 2.5 - - - 1.0 - - 1.0 1.5 - - 1.2 - 0.4 1.9 3.7 5.7 2.0 7.5 - - - - - - - - - - - - - 1.5 1.5 4.0 - 1.5 4.0 - - 5.3 2.7 - 1.2 - - - - - - 2.3 1.8 7.1 5.9 2.7 1.6 1.6 4.0 1.0 0.0 3.0 0.0 2.5 - - - 1.5 - - 1.5 2.0 - - 1.7 - 0.5 2.5 4.8 6.8 2.1 7.6 - - - - - - - - - - - - - 1.5 1.5 5.0 - 1.5 5.0 - - 6.3 3.7 - 2.2 - - - - - - 2.3 1.8 7.1 7.4 3.7 1.6 1.6 4.5 1.5 0.0 4.5 0.5 3.5 - - - 1.5 - - 1.5 2.5 - - 2.2 - 0.5 2.5 4.8 6.8 3.6 8.6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Timing v.2.0
tin tgclk_in trst tgoe tbuf ten tdis troute tpdb tpdi tptsa tfbk tinreg ts ts_pt th tcoi tsl thl tgoi tpdli tces tceh tsri tsrr
Control Delays
Routing/GLB Delays
Register/Latch Delays
tptclk tbclk tptsr tbsr tptoe tgptoe
Note: Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for further details.
15
Specifications ispLSI 5256VE
ispLSI 5256VE Timing Parameters (continued)
ADDER ADDER TYPE Routing Adders BASE PARAMETER -165 1.0 1.4 1.4 1.4 4.0 0.0 0.5 0.0 0.1 0.1 0.2 0.3 0.4 0.4 0.5 -125 1.5 1.7 1.7 1.7 4.0 0.0 0.5 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 -100 1.5 1.7 1.7 1.7 4.0 0.0 0.5 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 -80 1.5 1.7 1.7 1.7 4.0 0.0 0.5 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Timing Table/5256VE Timing v.2.0
tlp
Tioi Input Adders clk1 clk2 clk3 Tioo Output Adders1 Slow Slew I/O LVTTL_out LVCMOS25_out LVCMOS33_out 1 2 3 4 5 6 7
troute tgclk_in tgclk_in tgclk_in tbuf, ten tbuf, ten, tdis tbuf, ten, tdis tbuf, ten, tdis troute troute troute troute troute troute troute
Tbla Additional Block Loading Adders
1Timing for open drain configurations is the same as non-open drain configurations.
Note: Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for details.
16
Specifications ispLSI 5256VE
ispLSI 5256VE Timing Model
Routing/ GLB Delays From Feedback tPDb Feedback tPDi tROUTE
IN
tFBK tBUF tEN tDIS tIOO In/Out Delays
tIN tINREG tGCLK_IN tIOI
tBLA tLP
tPTSA
DATA
OUT
Q
CLK
tPTCLK tBCLK
CE
tPTSR tBSR
S/R MC Reg
RST
tRST tGPTOE tPTOE
Register/ Latch Delays
OE
tGOE Control Delays In/Out Delays
5000VE Timing Model
Note: Italicized parameters are delay adders above and beyond default conditions (i.e. GRP load of one GLB, CLK0, high-speed AND Array and VCC I/O option).
17
Specifications ispLSI 5256VE
Power Consumption
Power consumption in the ispLSI 5256VE device depends on two primary factors: the speed at which the device is operating and the number of product terms used. The product terms have a fuse-selectable speed/ power tradeoff setting. Each group of five product terms has a single speed/power tradeoff control fuse that acts on the complete group of five. The fast "high-speed" setting operates product terms at their normal full power consumption. For portions of the logic that can tolerate longer propagation delays, selecting the slower "lowpower" setting will reduce the power dissipation for these product terms. Figure 10 shows the relationship between power and operating frequency.
Figure 10. Typical Device Power Consumption vs fmax
300 275 250
ispLSI 5256VE High Speed Mode
ICC (mA)
225 200 175 150 0
ispLSI 5256VE Low Power Mode
25
50
75
100
125
150
175
200
fmax (MHz)
Notes: Configuration of 16 16-bit Counters Typical Current at 3.3V, 25 C
ICC can be estimated for the ispLSI 5256VE using the following equation: High Speed Mode: ICC = 21 + (# of PTs * 0.313) + (# of nets * Fmax * 0.00282) Low Power Mode: ICC = 21 + (# of PTs * 0.258) + (# of nets * Fmax * 0.00282) # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Fmax = Highest Clock Frequency to the device The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption of one GLB load on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified. 0127/5256VE
18
Specifications ispLSI 5256VE
Signal Descriptions
Signal Name TMS TCK TDI TDO TOE / I/O0 GOE0, GOE1 RESET I/O GND NC1 VCC CLK0, CLK1 CLK2 / I/O, CLK3 / I/O VCCIO Description Input - This pin is the Test Mode Select input, which is used to control the JTAG state machine. Input - This pin is the Test Clock input pin used to clock through the JTAG state machine. Input - This pin is the JTAG Test Data In pin used to load data. Output - This pin is the JTAG Test Data Out pin used to shift data out. Input/Output - This pin functions as either the Test Output Enable pin or an I/O pin based upon customer's design. TOE tristates all I/O pins when a logic low is driven. Input - These two pins are the Global Output Enable input pins. Dedicated Reset Input - This pin resets all registers in the device. The global polarity (active high or low input) for this pin is selectable. Input/Output - These are the general purpose I/O used by the logic array. Ground No connect. Vcc Dedicated clock inputs for all registers. Both clocks are muxed before being used as the clock input to all registers in the device. Input/Output - These pins share functionality. They can be used as dedicated clock inputs for all registers, as well as I/O pins. Input - This pin is used for optional 2.5V outputs. Every I/O can independently select either 3.3V or the optional voltage as its output level. If the optional output voltage is not required, this pin must be connected to the Vcc supply. Programmable pull-up resistors and bus-hold latches only draw current from this supply.
1. NC pins are not to be connected to any active signals, VCC or GND.
19
Specifications ispLSI 5256VE
Pin Configuration
ispLSI 5256VE 100-Pin TQFP (0.5mm Lead Pitch / 14.0mm x 14.0mm Body Size)
I/O 60 VCC I/O 59 GND I/O 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O 53 VCC CLK1 CLK0 I/O 52 GND I/O 51 I/O 50 I/O 49/CLK3 I/O 48 I/O47 I/O 46 I/O 45 GND I/O 44/CLK2 I/O 43
I/O 61 I/O 62 I/O 63 I/O 64 I/O 65 GND I/O 66 VCC I/O 67 I/O 68 I/O 69 I/O 70 I/O 71 GND TMS TCK TDI VCC I/O 0/TOE I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
ispLSI 5256VE
Top View
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
I/O 7 I/O 8 I/O 9 GND I/O 10 VCC I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 GND GOE 0 GOE 1 VCC I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VCC I/O 42 I/O 41 I/O 40 I/O 39 I/O 38 I/O 37 I/O 36 VCC RESET VCCIO TDO GND I/O 35 I/O 34 I/O 33 I/O 32 I/O 31 I/O 30 I/O 29 I/O 28 I/O 27 GND I/O 26 VCC
100 TQFP/5256VE
20
Specifications ispLSI 5256VE
Pin Configuration
ispLSI 5256VE 128-Pin TQFP (0.4mm Lead Pitch / 14.0mm x 14.0mm Body Size)
I/O 81 I/O 80 I/O 79 VCC I/O 78 GND I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 I/O 71 VCC CLK1 CLK0 I/O 70 I/O 69 GND I/O 68 I/O 67 I/O 66 I/O 65/CLK3 I/O 64 I/O 63 I/O 62 I/O 61 I/O 60 GND I/O 59/CLK2 I/O 58 I/O 57 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 I/O 82 I/O 83 I/O 84 I/O 85 I/O 86 I/O 87 GND I/O 88 VCC I/O 89 I/O 90 I/O 91 I/O 92 I/O 93 I/O 94 I/O 95 GND TMS TCK TDI VCC I/O 0/TOE I/O 1 I/O 2 I/O 3 I/O 4 GND I/O 5 VCC I/O 6 I/O 7 I/O 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
ispLSI 5256VE
Top View
VCC I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 VCC RESET VCCIO TDO GND I/O 47 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 VCC I/O 41 GND I/O 40 I/O 39 I/O 38 I/O 37 I/O 36 GND I/O 35 VCC
I/O 9 I/O 10 I/O 11 I/O 12 GND I/O 13 I/O 14 VCC I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 GND GOE0 GOE1 VCC I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 I/O 34
128 TQFP/5256VE
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
21
Specifications ispLSI 5256VE
Signal Configuration
ispLSI 5256VE 256-Ball fpBGA (1.0mm Ball Pitch / 17.0mm x 17.0mm Body Size)
16 15 14 13 12 11 10 9 8 7 CLK0 6 5 4 3 2 1
A B
C D E F G H J K L M N P R T
I/O 113 I/O 108 I/O 106 I/O 105 I/O 104 I/O 100 I/O 96 I/O 94 I/O 93 I/O 89 I/O 85 I/O 81 I/O 78 I/O 73 I/O 72 I/O 61
16
I/O 116 I/O 115 I/O 114 I/O 109 NC1 I/O 102 I/O 98
I/O 121
I/O 125
I/O I/O 131/ I/O 126 CLK3 133 I/O 124 I/O 123 GND NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1
GND
I/O 139 I/O 136 I/O 138
VCC
I/O 140 CLK1 I/O 141 GND NC1 NC1 GND
VCC VCC GND
I/O 145 I/O 149 I/O 148
VCC
I/O 147 I/O 156 I/O 155 GND NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1
I/O 151 I/O 157 I/O 159
VCC
I/O 152 I/O 163 I/O 160 I/O 169 I/O 173 I/O 181 I/O 185 I/O 184 I/O 191
TDI
I/O 153 I/O 164 I/O 161 I/O 167 I/O 171 I/O 176 I/O 180 I/O 183 I/O 190
TCK
I/O 165 I/O 168 I/O 172 I/O 175 I/O 177 I/O 179 I/O 187 I/O 188
TMS
A
B C D E F G H J K L M N P R T
I/O I/O 119/ 117 CLK2 NC1 I/O 111 I/O 101 I/O 97 TDO I/O 120 GND VCC GND VCC
I/O 129 I/O 128 VCC NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1
VCC
I/O 132 I/O 135 GND NC1 NC1
VCC GND GND VCC
I/O 144 I/O 143 GND NC1 NC1 VCC
GND GND VCC
NC1 NC1 GND
VCC VCC GND
NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1
VCC
GND
VCC
GND
VCC GND VCC GND VCC
VCCIO RESET GND
I/O 92 I/O 88 I/O 84 I/O 80 I/O 74 I/O 70 I/O 69 I/O 60
15
I/O 90 I/O 86 I/O 82 I/O 77 I/O 76 I/O 65 I/O 62 I/O 54
14
GND VCC GND GND VCC
I/O 0/ TOE I/O 2 I/O 5 I/O 9 I/O 14 I/O 16 I/O 21
1
NC1 NC1
GND
NC1 NC1
VCC
NC1 NC1
GND
NC1 NC1
GND
I/O 4 I/O 8 I/O 11 I/O 20 I/O 18 I/O 30
3
I/O 1 I/O 6 I/O 12 I/O 13 I/O 17 I/O 28
2
GND GND
I/O 66 I/O 67 I/O 53
13
I/O 57 I/O 64 I/O 52
12
I/O 56 I/O 58 I/O 50
11
GOE1 GOE0
I/O 41 I/O 40 I/O 44
8
I/O 42 I/O 34 I/O 38
7
I/O 36 I/O 29 I/O 37
6
I/O 26 I/O 25 I/O 33
5
I/O 22 I/O 24 I/O 32
4
I/O 48 I/O 49
10
I/O 46 I/O 45
9
ispLSI 5256VE
Bottom View
1. NCs are not to be connected to any active signals, VCC or GND. Note: Ball A1 indicator dot on top side of package.
22
Specifications ispLSI 5256VE
Signal Configuration
ispLSI 5256VE 272-Ball BGA (1.27mm Ball Pitch / 27.0mm x 27.0mm Body Size)
20 A B C D E F G H J K L M N P R T U V W Y
I/O 114
19
18
17
16
NC1 I/O 121 I/O 120
15
I/O 126 I/O 125 I/O 123
14
I/O 129
13
I/O 132
12
I/O 136
11
I/O 139 NC1
10
I/O 140 I/O 141
9
NC1 I/O 143
8
NC1 I/O 147 I/O 148
7
I/O 149 NC1 I/O 152
6
I/O 151 I/O 153 I/O 156
5
NC1 I/O 157 NC1
4
NC1 I/O 159 NC1
3
I/O 160 NC1
2
1 A B C D E F G H J K L M N P R T U V W Y
I/O I/O 119/ NC1 115 CLK2 NC1 NC1 I/O 116 I/O 117
I/O GND 164 I/O 163 I/O 165 I/O 169 NC1 I/O 172 I/O 176 I/O 179 NC1 NC1 NC1 I/O 190
NC1 NC1 I/O 111 I/O 109 I/O 105 I/O 102 I/O 100 I/O 97 NC1 NC1 I/O 108 I/O 104 I/O 101 I/O 98
I/O I/O 131/ I/O 128 CLK3 135 NC1 NC1 NC1
I/O I/O CLK0 138 144
NC1 NC1 I/O 167 NC1 I/O 175 NC1 I/O 181 I/O 185 I/O 187 I/O 191
I/O I/O I/O I/O I/O I/O GND NC1 VCC GND VCC CLK1 GND VCC GND NC1 113 124 133 145 155 161 NC1 NC1 NC1 VCC NC1 I/O 106 I/O 168 I/O 171 I/O 173 I/O 177 I/O 180 I/O 184 I/O 188
ispLSI 5256VE
Bottom View
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
VCC NC1 GND I/O 183 VCC
NC1 GND
I/O TDO VCCIO RESET 96 I/O 92 NC1 I/O 88 I/O 84 I/O 81 NC1 I/O 93 I/O 89 NC1 NC1 NC1 I/O 78 I/O 94 I/O 90 I/O 86 I/O 82 I/O 80 I/O 76 I/O 74 NC1 VCC I/O 85 GND I/O 77 VCC NC1 I/O 64 I/O 62 I/O 60 I/O 57 VCC I/O 58 GND NC1 I/O 50 I/O 49
TCK TMS I/O 2 GND I/O 12 I/O 1 I/O 5 I/O 9
I/O 0/ TDI TOE I/O 4 NC1 NC1 I/O 6 I/O 8 I/O 11
VCC NC1 NC1 NC1 I/O GOE1 VCC 48 NC1 GOE0 I/O 42 I/O 46 NC1 I/O 45 I/O 44 I/O 41 NC1 I/O 37 I/O 38 NC1 I/O 40 GND I/O 34 NC1 I/O 36 I/O 28 VCC I/O 21 I/O 24 I/O 25 I/O 26 I/O 14 I/O 13
NC1 NC1 I/O 73 I/O 72 I/O 70 I/O 69
NC1 GND NC1 I/O 66 NC1 I/O 65 NC1 I/O 61
GND NC1 NC1 NC1 I/O 20 NC1 NC1 I/O 17 I/O 16 NC1
NC1 NC1 I/O 56 I/O 54 I/O 53 I/O 52
NC1 NC1 I/O 32 I/O 33 I/O 29 I/O 30
NC1 NC1 NC1 I/O 67
NC1 NC1 NC1 I/O 22 NC1 I/O 18
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1. NCs are not to be connected to any active signals, Vcc or GND. Note: Ball A1 indicator dot on top side of package.
23
Specifications ispLSI 5256VE
Part Number Description
ispLSI 5256VE - XXX X XXXX X
Device Family Device Number Speed 165 = 165 MHz fmax 125 = 125 MHz fmax 100 = 100 MHz fmax 80 = 80 MHz fmax Grade Blank = Commercial I = Industrial Package T100 = 100-Pin TQFP T128 = 128-Pin TQFP F256 = 256-Ball fpBGA B272 = 272-Ball BGA Power L = Low
0212/5256ve
Ordering Information
COMMERCIAL
FAMILY fmax (MHz) 165 165 165 165 125 ispLSI 125 125 125 100 100 100 100 tpd (ns) 6.0 6.0 6.0 6.0 7.5 7.5 7.5 7.5 10 10 10 10 ORDERING NUMBER ispLSI 5256VE-165LT100 ispLSI 5256VE-165LT128 ispLSI 5256VE-165LF256 ispLSI 5256VE-165LB272 ispLSI 5256VE-125LT100 ispLSI 5256VE-125LT128 ispLSI 5256VE-125LF256 ispLSI 5256VE-125LB272 ispLSI 5256VE-100LT100 ispLSI 5256VE-100LT128 ispLSI 5256VE-100LF256 ispLSI 5256VE-100LB272 PACKAGE 100-Pin TQFP 128-Pin TQFP 256-Ball fpBGA 272-Ball BGA 100-Pin TQFP 128-Pin TQFP 256-Ball fpBGA 272-Ball BGA 100-Pin TQFP 128-Pin TQFP 256-Ball fpBGA 272-Ball BGA
Table 2-0041A/5256VE
INDUSTRIAL
FAMILY fmax (MHz) 125 125 125 125 100 ispLSI 100 100 100 80 80 80 80 tpd (ns) 7.5 7.5 7.5 7.5 10 10 10 10 12 12 12 12 ORDERING NUMBER ispLSI 5256VE-125LT100I ispLSI 5256VE-125LT128I ispLSI 5256VE-125LF256I ispLSI 5256VE-125LB272I ispLSI 5256VE-100LT100I ispLSI 5256VE-100LT128I ispLSI 5256VE-100LF256I ispLSI 5256VE-100LB272I ispLSI 5256VE-80LT100I ispLSI 5256VE-80LT128I ispLSI 5256VE-80LF256I ispLSI 5256VE-80LB272I PACKAGE 100-Pin TQFP 128-Pin TQFP 256-Ball fpBGA 272-Ball BGA 100-Pin TQFP 128-Pin TQFP 256-Ball fpBGA 272-Ball BGA 100-Pin TQFP 128-Pin TQFP 256-Ball fpBGA 272-Ball BGA
Table 2-0041B/5256VE
The ispLSI 5256VE is dual-marked with both Commercial and Industrial grades. The Commercial speed grade is faster (i.e. ispLSI 5256VE-165LF256) than the Industrial speed grade (i.e. ispLSI 5256VE-125LF256I).
24

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