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HV9608
Initial Release
Active Clamp Current-Mode PWM Controller
Features
Peak current-mode PWM Controller Two complementary MOSFET drivers Programmable deadtime between drivers High current gate drivers for main and auxiliary outputs Internal high voltage (12V to 250V) start-up regulator Programmable VIN undervoltage lockout and hysteresis VDD supply operation from 7.8V to 12V Fixed frequency PWM operation from 25KHz to 800KHz >50% duty cycle operation (up to 95%) Programmable slope compensation Programmable max duty-cycle/volt-second clamp Capacitor programmable soft-start Cycle-by-cycle current limiting 100ns current sense leading edge blanking 2 MHz error amplifier
Description
The HV9608 provides a single chip, optimized peak current mode control solution for design of high performance PWM converters using the active-clamp transformer flux reset. Due to its programmable slope compensation feature, the HV9608 allows operation beyond 50% duty cycle. Zerovoltage switching can be accomplished through using the programmable deadtime timers. The switching frequency can be programmed from 25kHz to 800kHz using a single resistor. The internal high voltage startup circuit can ensure start-up from the input voltage from 12V to 250V. It can also maintain the HV9608 in operation when the external "bootstrap" power supply is not available. The startup regulator is disconnected as soon as the HV9608 becomes powered from the bootstrap winding. The HV9608 offers a programmable soft start feature using a single external capacitor. The cycle by cycle current limit feature can protect the converter from overheating and damage by limiting the output over current. The HV9608 will maintain the cycle-by-cycle current limiting mode for a period of time programmed by the soft start capacitor value. The HV9608 includes a single pin UVLO circuit that allows independent accurate setting of both the turn-on and the turn-off threshold voltage. A programmable volt-second clamp reduces voltage stress of the switching devices. The HV9608 is available in a space-saving TSSOP-16 package.
Applications
Networking Telecommunication Systems and Terminals IEEE 802.3af PoE PD Devices SANS, Servers & Workstations High Efficiency Instrumentation Supplies High Efficiency Supplies for Portable Equipment
Typical Application Circuit
VIN LF CIN
1
Vo +
T1 HV9608 VIN VDD
16
VDD C2
R3
R1 R2
2
UVLO
DT1
Q4
15
RVS
RDT1 C1
3
Q1
CF
REF
AGATE
14
CSS
4
R4 SS GATE
13
Q3 RDT2 RS
RSC1
5
SC
DT2
12
RT
6
RT
GND
11
C3 RSC2
7
VS
CS
10
Q2
8
COMP
FB
9
C4
CZ CP
RP
A122104
Supertex, Inc.
* 1235 Bordeaux Drive, Sunnyvale, CA 94089 * Tel: (408) 222-8888 * FAX: (408) 222-4895 * www.supertex.com
HV9608
Ordering Information
Package Options DEVICE 16-Pin TSSOP HV9608 HV9608TS
Absolute Maximum Ratings*
Input Voltage, VIN Supply Voltage, VDD Operating Ambient Temperature Range Operating Junction Temperature Range Storage Temperature Range Power Dissipation @ 25C, TSSOP -0.3V to +250V +13.5V max -40C to +85C -40C to +125C -65 to +150C 1000mW
*All voltages referenced to GND pin. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
(The * denotes the specifications which apply over the full operating temperature range of -40C < TA < +85C, otherwise the specifications are at TA = 25C, VD D = 10V, unless otherwise noted)
Electrical Characteristics
VIN_Pre-Regulator/Start-up/ VDD_Supply Symbol Parameter VIN Regulator input voltage IIN,MAX Maximum regulator current VDD,REG Regulator output voltage VDD, MAX Supply voltage range VDD,STOP VDD under voltage threshold VDD,START VDD startup voltage IDD,OFF
Min 12 20 9.27 7.58 8.33
Typ.
Max 250 9.65 12 7.90 8.67 1.8
9.46 7.74 8.5 1.25
Units V mA V V V V mA
Conditions VIN = 24V, VDD = 9.2V VIN [12V - 250V] To guarantee table parameters VDD falling VDD rising RT = 110 K; RDT1= 80K; RDT1= 80K; UVLO tied to ground;
Supply standby quiescent current
Under Voltage Lockout (UVLO) Symbol Parameter Vth,UVLO UVLO threshold voltage IHYS,UVLO UVLO hysteresis current GATE/AGATE_MOSFET Driver Output Symbol Parameter tR1 Main gate rise time tF1 Main gate fall time tR2 Auxiliary gate rise time tF2 Auxiliary gate fall time RDT1, RDT2 Dead time control resistor range Rising edge delay from AGATE to d1 GATE Falling edge delay from GATE to d2 AGATE
Min 1.112
Typ. 1.135 14
Max 1.158
Units Conditions V * Guaranteed by design A
Min
Typ 40 20 40 20 105
40 80 100
Max 60 30 60 30 400 130 400
Units nSec nSec nSec nSec K nSec nSec
Conditions CLOAD = 1nF CLOAD = 1nF CLOAD = 0.5nF CLOAD = 0.5nF RDT1 = 80K RDT2 = 80K
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HV9608
(continued from page 2) (The * denotes the specifications which apply over the full operating temperature range of -40C < TA < +85C, otherwise the specifications are at TA = 25C, VDD = 10V, unless otherwise noted)
Electrical Characteristics
RT_Oscillator Symbol Parameter fOSC,MIN Minimum operating frequency fOSC,MAX Maximum operating frequency fOSC Frequency variation VDD supply voltage stability of f/f frequency PWM Symbol DMAX DMAX DMIN DMIN
Min
220
Typ 25 800 250
Max
280 3
Units KHz KHz KHz * %
Conditions RT = 1.862M RT = 52.3K RT = 169K RT = 169K, 7.8V < VDD < 12V
Parameter Maximum GATE duty cycle Maximum GATE duty cycle Minimum GATE duty cycle Minimum GATE duty cycle
Min 95 85
Typ
Max
0 0
Units Conditions % * fOSC = 100KHz (RT = 453K) % * fOSC = 800KHz (RT = 52.3K) % %
Reference Symbol Parameter VREF Reference output voltage ISRC Maximum sourcing current VREF Load regulation VREF Line regulation Current Sensing Symbol Parameter VCS Current limit threshold voltage Leading edge current sense tBLANK blanking time tDELAY Current limit delay to output
Min 1.112 2
Typ 1.135
Max 1.158 5 20
Units Conditions V * mA mV 0 < IREF < 2 mA mV 7.8V < VDD < 12V
Min 0.58
Typ 0.6 100 70
Max 0.62
Units V nSec
Conditions
120
nSec
VCS = 0 to 1V step after blanking time
Error Amplifier Symbol Parameter IFB Input bias current VFB FB input voltage AVOL Open loop voltage gain BW Unity gain bandwidth ISOURCE Maximum output current sourcing ISINK Maximum output current sinking VCOMP Output clamped voltage Soft Start Symbol VSS,LOW VSS,HI ISS,HI tF I SS,LO
Min 1.112 70 2 2 4 3.3
Typ 25 1.135
Max 200 1.158
3.45
3.6
Units nA V dB MHz mA mA V
Conditions VFB = VCOMP VFB = VCOMP
Parameter Soft start low output Soft start high output Soft start output current Soft start output fall time Pulse-by-pulse current limit mode sink current
Min 5.25
Typ 5.45 7 7
Max 0.1 5.65 10
Units V V A Sec A
Conditions
CSS = 0.1F; VFB = VCOMP;
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HV9608
(continued from page 3) (The * denotes the specifications which apply over the full operating temperature range of -40C < TA < +85C, otherwise the specifications are at TA = 25C, VDD = 10V, unless otherwise noted)
Electrical Characteristics
Slope Compensation Symbol Parameter RSC Slope compensation resistor range Slope compensation ramp peak IRAMP,PEAK current Max Duty-Cycle/Voltage-Second Clamp Parameter Symbol Iin VS pin input current range DVS DVS DVS Duty cycle of gate signal Duty cycle of gate signal Duty cycle of gate signal
Min 5 125
Typ 150
Max 175
Units k A
Conditions RT = 453K; RCS = 500; RSC = 40K; Full duty cycle
Min 50 50 23 21.5
Typ 55.5 25.5 25.5
Max 3m 61 28 29
Units A % % %
Conditions Ivs = 250A, RDT1 = RDT2 = 80K; RT = 169K Ivs = 510A, RDT1 = RDT2 = 80K; RT=169K Ivs = 510A, RDT1 = RDT2 = 80K; * RT=169K
Pinout
VIN
1 16
VDD
REF - This pin provides a 2% accurate reference voltage that can source up to 2mA of current. SS - A capacitor connected to this pin determines the soft start time. The soft start capacitor is fully discharged upon detection of the under voltage condition at VDD or UVLO pins. VS - The resistor connected from this pin to VIN sets the charging current to an internal capacitor, which is matched with the oscillator capacitor. The voltage on the capacitor is compared with a reference voltage of 1.2V, and sets the maximum duty ratio of the PWM controller. SC - The resistor connected from this pin to GND sets the ramp current sourced from the CS pin for slope compensation. RT - The resistor connected from this pin to GND programs the frequency of the internal oscillator by setting the charging current for the internal timing capacitor. GND - Common connection for all Logic and Analog circuits.
UVLO
2
15
DT1
REF
3
14
AGATE
SS
4
13
GATE
HV9608
SC
5 12
DT2
RT
6
11
GND
VS
7
10
CS
COMP
8
9
FB
Pin Descriptions
VIN - This is the high voltage linear regulator input. It can accept DC input voltages in the range of 12V to 250V, and supplies a regulated voltage of 9.5V to the VDD pin. UVLO - This pin can be used for enabling/disabling the HV9608, or as an under voltage lockout input. Both the turn-on and the turn-off thresholds are independently programmable. By selecting appropriate resistor values, a corresponding voltage divider is connected to this pin. When the voltage on this pin falls below a threshold, the high voltage regulator turns-off and the HV9608 becomes disabled. VDD - This is the power supply pin for the PWM logic and analog circuits. When the input voltage to the VIN pin exceeds the start voltage of 8.5V, the input regulator will bias the voltage at this pin to a nominal of 9.5V. After the PWM has started, an external bootstrap supply can overdrive the output voltage of the regulator disconnecting it from VIN. Bypass this pin to GND using a low impedance high frequency capacitor.
AGATE - This push-pull CMOS output is designed to drive the gate of an external P-Channel power MOSFET. GATE - This push-pull CMOS output is designed to drive the gate of an external N-Channel power MOSFET. DT2 - This pin is used to set the dead time between the falling edge of GATE signal and AGATE signal. DT1 - This pin is used to set the dead time between the rising edge of AGATE signal and GATE signal. FB - High impedance inverting input of the error amplifier. COMP - The output of the error amplifier. CS - A resistor connected from this pin to a current sense voltage programs the amount of slope compensation ramp and feeds this current sense voltage to the PWM comparator. A leading edge blanking of 100ns is provided. Voltage of 0.6V at this pin triggers the current limit comparator.
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A122104
HV9608 Functional Block Diagram
VIN
High Voltage startup regulator
1.135V
VDD + -
POR
UVLO + 1.135V -
REF
Bandgap reference
RT
Oscillator
S R R
Q
Delay Logic driver
GATE
VS + 1.135V pwm -
AGATE
DT1
Comp 0.6V 1.135V FB 5.45V + + eAmp
+
DT2
100ns blanking
CS
3.85V
+ UVLO + 0.6V ramp -
GND
SS
SC
Functional Description
HIGH VOLTAGE REGULATOR
When DC voltage from 12 to 250V is applied to the VIN pin, an internal high voltage linear regulator provides a regulated output voltage of 9.3V at the VDD pin. This voltage can be used to start the DC/DC converter. Applying external voltage to the VDD pin that is higher than its output voltage will disable the regulator. Therefore, the VIN pin will draw negligible current once the DC/DC converter has started, and a "bootstrap" voltage has developed at the VDD pin. Alternatively, the high voltage regulator can continuously supply bias current up to 20mA powering the gate driver and all internal circuits of HV9608. The need for a bootstrap power supply would be eliminated in this case. However, caution must be taken to maintain the HV9608 within its package power dissipation limits. The output of the linear regulator is equipped with an under voltage protection comparator that disables all internal circuits when the voltage at the VDD pin falls below 7.62V. Hysteresis of 0.76V is provided.
the hysteresis that can be calculated in accordance with the following equation:
VUVLO = 14 A
R1 R2 , R1 + R2
where R1 and R2 are the input voltage divider resistors.
OSCILLATOR FREQUENCY
The switching frequency of the HV9608 can be programmed using a single resistor connected to the RT pin:
1 -9 F [ Hz ] - 300 10 OSC RT = CT [ F ]
SOFT START
As soon as the voltage at the VDD pin exceeds the turn-on threshold, a 7A current is sourced from the SS pin into an external soft-start capacitor CSS. As the voltage across CSS ramps up linearly, the output of the error amplifier (COMP) gradually increases until regulation of the output voltage is achieved. Sizing CSS programs the time duration of the soft start mode. When CSS is sized properly, no overshoot of the output voltage or excessive input inrush current will occur. When the voltage at the VDD pin falls below the under voltage protection threshold, CSS is rapidly discharged to zero.
INPUT UNDER VOLTAGE LOCKOUT (UVLO)
The HV9608 provides a programmable under voltage protection input (UVLO pin) that allows independent setting of the turn-on and the turn-off limits for the input voltage of the DC/DC converter. When the voltage applied to the UVLO pin exceeds 1.135V, the gate driver and the reference voltage at the VREF pin are enabled, and the DC/DC converter starts switching. At the same time, a current of 14A is sourced from the UVLO pin. This current sets
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A122104
HV9608
SLOPE COMPENSATION
The HV9608 PWM controller uses an internal slope compensation scheme that is externally programmable by appropriately selecting two resistors RSC1 and RCS2. The slope compensation ramp generated at the CS pin can be calculated as: where d1 is the leading edge delay, d2 is the trailing edge delay. (Refer to Fig. 2.)
GATE
m SC [V / s] = 5.7 10 -6 FOSC [Hz ]
R SC 2 R SC1
AGATE
RSC1 must be selected greater than 5 k. When a current sense RC filter is needed at the SC pin, the value of RCS2 will be dictated by the filter capacitor and the corner frequency of the filter. The filter capacitor externally connected to the CS pin is discharged prior to each switching cycle. It is not recommended to use a capacitor larger than 220pF for this reason.
d 1 d 2
Figure 2. Gate Drive Output timing diagram. VOLT-SECOND CLAMP The duty cycle of the active DC-DC converter may become very large during load transients. This condition may cause saturation of the power transformer or excessive voltage stress at the clamp capacitor C3, potentially damaging for all switching devices. In order to prevent this condition, the HV9608 includes a volt-second clamp circuit that can be programmed to limit the maximum duty cycle of the PWM controller, which is inversely proportional to the input voltage of the DC-DC converter. The maximum duty cycle DMAX is set by merely connecting a single resistor RVS between the positive input terminal of the converter and the VS pin. RVS can be calculated with the following equation.
GATE DRIVE OUTPUTS
The HV9608 provides two gate-drive outputs that are configured for driving a low-side clamp DC-DC converter, having a main switching N-channel MOSFET (Q1) and an auxiliary active clamp P-channel MOSFET (Q2). The GATE output is designed to drive the main N-channel MOSFET Q1, while the AGATE output drives Q2 via a negative output charge pump circuit C4, D1, R5. Delays between the leading and the trailing edges of the gate drive outputs can be programmed using external resistors RDT1 and RDT2 connected to the DT1 and DT2 pins, respectively. The values of RDT1 and RDT2 can be calculated according to the following equations:
R DT1 = 8 x 1011 d1 [s] ,
R DT 2 = 8 x 1011 d 2 [s ] ,
DMAX -8 RVS = 1.72 x 109 (VIN [V ] - 0.7 ) F [ Hz ] + d1 [ s ] + 2 x 10 OSC
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Doc. #: DSFP-HV9608 A122104
A122104

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