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EM78M680
USB Full Speed Microcontroller
Product Specification
DOC. VERSION 1.1
ELAN MICROELECTRONICS CORP.
February 2007
Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation.
Copyright (c) 2006 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters: No. 12, Innovation Road 1 Hsinchu Science Park Hsinchu, Taiwan 30077 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw Hong Kong: Elan (HK) Microelectronics Corporation, Ltd. Flat A, 19F., World Tech Centre 95 How Ming Street, Kwun Tong Kowloon , HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 elanhk@emc.com.hk Shenzhen: Elan Microelectronics Shenzhen, Ltd. SSMEC Bldg., 3F, Gaoxin S. Ave. Shenzhen Hi-Tech Industrial Park Shenzhen, Guandong, CHINA Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 USA: Elan Information Technology Group (USA) 1821 Saratoga Ave., Suite 250 Saratoga, CA 95070 USA Tel: +1 408 366-8225 Fax: +1 408 366-8220
Europe: Elan Microelectronics Corp. (Europe) Siewerdtstrasse 105 8050 Zurich, SWITZERLAND Tel: +41 43 299-4060 Fax: +41 43 299-4079 http://www.elan-europe.com
Shanghai: Elan Microelectronics Shanghai, Ltd. 23/Bldg. #115 Lane 572, Bibo Road Zhangjiang Hi-Tech Park Shanghai, CHINA Tel: +86 21 5080-3866 Fax: +86 21 5080-4600
Contents
Contents
1 2 3 General Description .................................................................................................. 1 Features ..................................................................................................................... 1 Pin Assignment ......................................................................................................... 4 3.1 4 5 6 Function Type Description .................................................................................. 4 3.2 Pin Configuration................................................................................................ 4 Pin Description.......................................................................................................... 6 Block Diagram ........................................................................................................... 7 Function Description ................................................................................................ 7 6.1 6.2 Program Memory................................................................................................ 7 Data Memory ...................................................................................................... 8
6.2.1 Operational Registers........................................................................................10 6.2.1.1 R0 (Indirect Address Register) ........................................................... 10 6.2.1.2 R1 (Timer/Clock Counter, TCC) ......................................................... 10 6.2.1.3 R2 (Program Counter & Stack)........................................................... 10 6.2.1.4 R3 (Status Register) ........................................................................... 11 6.2.1.5 R4 (RAM Select Register) .................................................................. 12 6.2.1.6 R5 (Port 5 I/O Register)...................................................................... 13 6.2.1.7 R6 (Port 6 I/O Register)...................................................................... 13 6.2.1.8 R7 (Port 7 I/O Register)...................................................................... 13 6.2.1.9 R8 (Port 8 I/O Register)...................................................................... 13 6.2.1.10 R9 (Port 9 I/O Register)...................................................................... 13 6.2.1.11 RA (USB Endpoint 0 Status Register)................................................ 13 6.2.1.12 RC (FIFO Indirect Index Register)...................................................... 14 6.2.1.13 RD (FIFO Indirect Data Register) ....................................................... 14 6.2.1.14 RE (Interrupt Status Register) ............................................................ 15 6.2.1.15 RF (Interrupt Status Register) ............................................................ 15 6.2.1.16 R10 (USB Endpoint Status Register) ................................................. 15 6.2.1.17 R11 (AD Controller/AD Selection Pin)................................................ 16 6.2.1.18 R12 (Dual Mode Control).................................................................... 17 6.2.1.19 R14 (ADC Output Data) : ADC Output Data for Selecting Pin ........... 17 6.2.1.20 R17 (EEPROM Control Register) ....................................................... 18 6.2.1.21 R18~R1F (General Purpose Register) ............................................... 18 6.2.1.22 R20~R3F (General Purpose Register) ............................................... 18 A (Accumulator).................................................................................................19 CONT (Control Register)...................................................................................19 IOC5 ~ IOC9 (I/O Port Control Register) ..........................................................20 IOCA (RFCNT: RF Control Register).................................................................20 IOCB (PWM_CNT: PWM Controller).................................................................20
6.3
Special Function Registers............................................................................... 19
6.3.1 6.3.2 6.3.3 6.3.4 6.3.5
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6.3.6 6.3.7 6.3.8 6.3.9
IOCC (Reserve).................................................................................................21 IOCD (Port 9 Pull High Control Register)..........................................................21 IOCE (MCU Control Register)...........................................................................21 IOCF (Interrupt Mask Register).........................................................................22
6.4 6.5 6.6
USB Device Controller ..................................................................................... 23 Device Address and Endpoints......................................................................... 23 Reset ................................................................................................................ 23
6.6.1 6.6.2 6.6.3 Power-on Reset.................................................................................................23 Watchdog Reset................................................................................................23 USB Reset.........................................................................................................24 Power Down Mode ............................................................................................24 Dual Clock Mode ...............................................................................................24
6.7
Saving Power Mode ......................................................................................... 24
6.7.1 6.7.2
6.8 6.9
Interrupt ............................................................................................................ 25 Pattern Detect Application (PDA) ..................................................................... 26
Function Description..........................................................................................26 Control Register ................................................................................................26 6.9.2.1 IOCF [2~3] PDA Enable Control Bit t ................................................. 26 6.9.2.2 IOCA (PDA Control Register) ............................................................. 26 6.9.2.3 R15 ERAM1 (P.92 Low Pattern Counter)........................................... 26 6.9.2.4 R16 ERAM1 (P.92 High Pattern Counter).......................................... 26 6.9.2.5 R17 ERAM1 (P.93 Low Pattern Counter)........................................... 26 6.9.2.6 R18 ERAM1 (P.93 High Pattern Counter).......................................... 27 6.9.3 Sampling Rate and Debounce Length ..............................................................27 6.9.1 6.9.2
6.10 Pulse Width Modulation (PWM) ....................................................................... 28
6.10.1 Function Description..........................................................................................28 6.10.2 Duty Cycle .........................................................................................................29 6.10.3 Control Register ................................................................................................29 6.10.3.1 R15 (PWM1 Duty Cycle Register) ...................................................... 29 6.10.3.2 R16 (PWM2 Duty Cycle Register) ...................................................... 29 6.10.3.3 IOCB (PWM Control Register)............................................................ 29
6.11 Analog-To-Digital Converter (ADC) .................................................................. 30
6.11.1 Function Description..........................................................................................30 6.11.2 Control Register ................................................................................................30 6.11.2.1 R11 (AD Channel Select Register)..................................................... 30 6.11.2.2 R13 (AD LSB Data Register).............................................................. 31 6.11.2.3 R14 (AD MSB Data Register)............................................................. 31
7 8
Absolute Maximum Ratings ................................................................................... 31 DC Electrical Characteristic ................................................................................... 32
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APPENDIX
A B C D Special Registers Map ............................................................................................ 34 Instruction Set ......................................................................................................... 41 Code Option............................................................................................................. 44 Application Circuit...................................................................................47
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Specification Revision History
Doc. Version 0.9 Revision Description Preliminary version Date 2006/08/29
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Contents
1
General Description
The EM78M680 is a series of 8-bit Universal Serial Bus, RISC architecture, Multi-Time Programming (MTP) microcontrollers. It is specifically designed for USB full speed device application. The EM78M680 also supports one device address and five endpoints. The EM78M680 has eight-level stack and four sets of interrupt sources. It has a maximum of 36 General Input/Output pins with the capacity of sinking large current. Each device has 271 bytes of general purpose SRAM, 6K bytes of program ROM, and is embedded with 32 bytes of EEPROM. These series of ICs have special features that meet user's requirements. Such features are: Dual Clock mode which allows the device to run on very low power. Pattern Detect Application function which is used in serial transmission to count waveform width Pulse Width Modulation that can generate a duty-cycle-programmable signal 24-channel AD converter with up to 10 bits resolution
2
Features
Operating voltage: 4.4V ~ 5.25V USB Specification Compliance
* Universal Serial Bus Specification Version 1.1 * USB Device Class Definition for Human Interface Device (HID), Firmware
Specification Version 1.1
* Supports one device address and five endpoints
USB Application
* * * *
P74 (D+) has an internal pull-high resistor (1.5K) USB protocol handling USB device state handling Identifies and decodes Standard USB commands to Endpoint Zero
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Built-in 8-bit RISC MCU
* * * * * *
8-level stacks for subroutine nesting, and interrupt 4 sets of interrupts 8-bit real time clock/counter (TCC) with overflow interrupt Built-in RC oscillator free running for Watchdog Timer and Dual clock mode Two independent programmable prescalers for WDT and TCC Two methods of power saving: - Power-down mode (Sleep mode) - Dual clock mode
* Two clocks per instruction cycle * Multi-time programmable
Set 1 INT : (jump to 0x08)
* * * * * * * * *
TCC overflow interrupt EP0 command in interrupt USB suspend interrupt USB reset interrupt USB HOST resume interrupt
Set 2 INT : (jump to 0x10) RF1 low pattern interrupt RF1 high pattern interrupt RF2 low pattern interrupt RF2 high pattern interrupt
Set 3 INT : (jump to 0x18)
* P77 port change interrupt * P76 port change interrupt
Set 4 INT : (jump to 0x20) EP1~5 output Endpoint received O.K interrupt I/O Ports
* 3 LED sink pins * Each GPIO pin in Ports 5, 6, 8, P90~P93, P95, P96, P70~P72 and
P76~P77, has an internal programmable pull-high resistor (25 K)
* Each GPIO pin of Port 6, P76~P77, and Port 9 can wakeup the MCU from
sleep mode by input state change
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Internal Memory
* * * *
Built-in 6Kx13 bits Program ROM Built-in 271 bytes general purpose registers (SRAM) Built-in USB Application FIFOs Built-in 32 bytes E PROM
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Operation Frequency
* Normal Mode: MCU runs on an external oscillator frequency of 4MHz,
Internal system frequency of 8MHz, 16MHz or 24MHz
* Dual Clock Mode: MCU runs at a frequency of 256kHz (or 32kHz, 4kHz,
500Hz), using an internal oscillator with an external crystal resonator turned off to save power Built-in Pattern Detecting Application for serial signal transmission Built-in Pulse Width Modulation (PWM)
* 2 channels PWM function on P.92 (PWM1) and P.93 (PWM2) * 8-bit resolution of PWM output * 8 selections of duty cycles
Built-in 24-Channel Analog-to-Digital Converter (ADC)
* Built-in AD Converter with 10-bit resolution * 4 types of ADC clock source selection: 256K/128K/64K/32K
Built-in 3.3V Voltage Regulator
* For UDC power supply * Pull-up source for the external USB resistor on D+ pin
Package Type
* * * * * *
44-pin QFP (EM78M680 (A/D) AQ) 40-pin DIP 600mil (EM78M680 (A/D) AP) 24-pin DIP 600mil (EM78M680 (A/D) CP) 24-pin SOP 300mil (EM78M680 (A/D) CM) 20-pin DIP 300mil (EM78M680 (A/D) BP) 20-pin SOP 300mil (EM78M680 (A/D) BM)
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3
Pin Assignment
3.1 Function Type Description
The EM78M680 series has four types of packaging. Each type is divided into two modules, namely; original, and with both E PROM and A/D Converter. Hence, packaging configuration for each series is defined. Table 3.1 below summarizes which series of the EM78M680 belong to which module. Table 3-1 Packaging Summary of EM78M680 Series IC
Original EM78M680A With Both EM78M680D
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3.2 Pin Configuration
P56 P57 P60 P61 P62 P63 P77 VDD OSCI OSCO
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
P55 P54 VNN P94/VPP P93/SE2/PWM2 P92/SE1/PWM1 DD+ V3.3 VSS
Fig. 3-1 EM78M680*BP/*BM (20-Pin DIP/SOP)
OSCO VSS V3.3 D+ DP92/SE1/PWM1 P93/SE2/PWM2 P94/VPP VNN P54 P55 P56
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
OSCI VDD P76 P77 P66 P65 P64 P63 P62 P61 P60 P57
Fig. 3-2 EM78M680*CP/*CM (24-Pin DIP/SOP)
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VSS V3.3 D+ DP90 P91 P92/SE1/PWM1 P93/SE2/PWM2 P94/VPP VNN P50 P51 P52 P53 P54 P55 P56 P57 P80 P81
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
OSCO OSCI VDD P70 P71 P72 P67 P66 P65 P64 P63 P62 P61 P60 P87 P86 P85 P84 P83 P82
Fig. 3-3 EM78M680*AP (40-Pin DIP)
OSCO
OSCI
VDD
V3.3
VSS
P90
P76
44 43 42 41 40 39 38 37 36 35 34 P91 P92/SE1/PWM1 P93/SE2/PWM2 P94/VPP P95 P96 VNN P50 P51 P52 P53 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 P54 P55 P56 P57 P80 P81 P82 P83 P84 P85 P86 33 32 31 30 29 28 27 26 25 24 23 P71 P72 P67 P66 P65 P64 P63 P62 P61 P60 P87
P77
P70
D+
D-
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Contents Fig. 3-4 EM78M680*AQ (44-Pin QFP)
4 Pin Description
Symbol I/O Function General 8-bit bidirectional input/output port. All pins on this port can be internally pulled-high by register IOCE Bit 0. All Port 5 input/output pins can be used for ADC function. General 8-bit bidirectional input/output port. All pins on this port can be internally pulled-high by register IOCE Bit 1. All Port 6 input/output pins can be used for ADC function. P70 ~ P72 P76 ~ P77 General 8-bit bidirectional input/output port. All pins on this port can be internally pulled-high by register IOCE Bit 3. The sink current of P70 ~ P72 are used for driving LED. General 8-bit bidirectional input/output port. All pins on this port can be internally pulled-high by register IOCE Bit 2. All Port 8 input/output pins can be used for ADC function. P94 / VPP I MTP program pin. Used in programming the on-chip ROM. P94 functions as an input pin only (without an internally pulled-high resistor). General bidirectional input/outpu port. Each pin can be internally pulled-high by register IOCD. P92 ~ P93 can be used for PWM (pulse width modulation) or PDA (serial signal transmission application) function. USB D+ pin. Built-in internal 1.5K pulled-high resistor to V3.3 USB D- pin. 4MHz crystal resonator input. Return path for 4MHz crystal resonator. MTP program pin. Used in programming the on-chip ROM. During normal operation, this pin is connected to Ground. 3.3V DC voltage output from an internal regulator. This pin has to be tied to a 4.7sF capacitor. Connect to the USB power source or to a nominal 5V-power supply. Actual VDD range can vary between 4.4V and 5.25V. Connect to ground.
P50 ~ P57
I/O
P60 ~ P67
I/O
I/O
P80 ~ P87
I/O
P90 ~ P93 P95 ~ P96
I/O
USB D+ USB DOSCI OSCO VNN V3.3 VDD VSS
I/O I/O I I/O - O - -
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Block Diagram
OSCI OSCO VDD V3.3 D+ DR2 (PC) Stack1 Stack2 Stack3 Stack4 Stack5 Stack6 Stack7 Stack8 R3 (Status)
Built-in RC
Oscillator Timing Control
3.3V Regulator
Transceiver ROM
RC,RD
USB Device Controller EEPROM EP FIFO Instruction register Interrupt Control Instruction Decoder
Prescaler WDT Reset & Sleep & Wake up Control
Prescaler TCC
RAM
ALU
WDT Timer
R1 (TCC)
R4 (RSR)
ACC
DATA & CONTROL BUS
PWM
ADC
P90 P91 P92/PWM1/SE1 P93/PWM2/SE2 P94/Vpp P95 P96 P80/AD P81/AD P82/AD P83/AD P84/AD P85/AD P86/AD P87/AD P60/AD P61/AD P62/AD P63/AD P64/AD P65/AD P66/AD P67/AD P50/AD P51/AD P52/AD P53/AD P54/AD P55/AD P56/AD P57/AD
I/O Port 7
P70 P71 P72 P76 P77
Pattern Detect Application
I/O Port 9
I/O Port 8
I/O Port 6
I/O Port 5
6
Function Description
The EM78M680 memory is organized into four spaces, namely; User Program memory in 6Kx13 bits ROM space, Data Memory in 271 bytes SRAM space, EEPROM space, and USB Application FIFOs for Endpoint 0, Endpoint 1, Endpoint 2, Endpoint 3, Endpoint 4, Endpoint 5. Furthermore, several registers are used for special purposes.
6.1 Program Memory
The program space of the EM78M680 is 6K bytes, and is divided into six pages. Each page is 1K bytes long. After a Reset, the 13-bit Program Counter (PC) points to location zero of the program space. The Interrupt Vectors are at 0x0008 (USB and TCC interrupts), 0x0010 (RF interrupt), 0x0018 (P76 P77 port change interrupt) and 0x020 (EP1~5 output endpoint interrupt).
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After an interrupt, the MCU will auto push the RAM bank value (RSR Bits 6, 7) (RA,7), page selector (Status Bits 5, 6, 7), and Accumulator (A) and fetch the next instruction from the corresponding address as illustrated in the following diagram. After reset
PC
Address Reset Vector First set of Interrupt Vector
0x0010
0x0000 0x0008
Second set of Interrupt Vector Third set of Interrupt Vector Fourth set of Interrupt Vector Page 0 Page 1
0x0018
0x0020 0x03FF 0x0400 0x07FF 0x0800
Page 2
0x0BFF 0x0C00
Page 3
0x0FFF 0x1000
Page 4
0x13FF 0x1400
Page 5
0x17FF
Fig 6-1 EM78M680 Data RAM Organization
6.2 Data Memory
The Data Memory has 271 bytes SRAM space. It is also equipped with USB Application FIFO space for USB Application. Figure 6.2 shows the organization of the Data Memory Space.
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Fig. 6-2 Data Memory Configuration
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6.2.1 Operational Registers
6.2.1.1 R0 (Indirect Address Register)
R0 is not a physically implemented register. It is used as an indirect addressing pointer. Any instruction using R0 as register actually accesses data pointed by the RAM Select Register (R4). 6.2.1.2 R1 (Timer/Clock Counter, TCC)
This register TCC, is an 8-bit timer or counter. It is incremented by the instruction cycle clock, and is readable and writable as any other register. 6.2.1.3 R2 (Program Counter & Stack)
R2 and the hardware stacks are 13 bits wide. The structure is depicted in Fig. 3. Generates 6Kx13 on-chip ROM addresses to the relative programming instruction codes. One program page is 1024 words long. All the R2 bits are set to "0"s when a reset condition occurs. "JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows jump to any location on one page. "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed onto the stack. Thus, the subroutine entry address can be located anywhere within a page "RET" ("RETL k", "RETI") instruction loads the program counter with the contents at the top of stack. "MOV R2, A" allows the loading of an address from the "A" register to the lower 8 bits of PC, and the ninth and tenth bits (A8~A9) of PC are cleared. "ADD R2, A" allows a relative address to be added to the current PC, and the ninth and tenth bits of PC are cleared. Any instruction that is written to R2 (e.g. "ADD R2, A", "MOV R2, A", "BC R2,6",etc), except "TBL" will cause the ninth and tenth bits (A8~A9) of the PC to be cleared. Thus, the computed jump is limited to the first 256 locations of any program page. "TBL" allows a relative address to be added to the current PC (R2+AR2), and contents of the ninth and tenth bits (A8~A9) of the PC are not changed. Thus, the computed jump can be on the second (third, or 4th) 256 locations on one program page. For the EM78M680, the most significant bits (A10~A12) will be loaded with the contents of bits PS0~PS2 in the status register (R3) upon the execution of a "JMP", "CALL", or any other instructions which writes to R2.
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All instructions are single instruction cycle except for the instruction that would change the contents R2. Such instruction will need one more instruction cycle.
CALL PC A12~A10 A9~A8 A7 ~ A0 RET RETL RETI 000 001 010 011
0000 03FF 0400 07FF 0800 0BFF 0C00 0FFF
Stack 1 Stack 2 Stack 3 Stack 4 Stack 5 Stack 6 Stack 7 Stack 8
Page 0
Page 1
0000:Reset Location
Page 2
Interrupt Location
Page 3 Page 4
0008:RAM Module 0 interrupt 0010:RAM Module 1 interrupt 0018:RAM Module 2 interrupt 0020:RAM Module 3 interrupt
100 101
1000 13FF 1400 17FF
Page 5
6.2.1.4
Bit 7 PS2
R3 (Status Register)
Bit 6 PS1 Bit 5 PS0 Bit 4 T Bit 3 P Bit 2 Z Bit 1 DC Bit 0 C
After an interrupt occurs, MCU will save R3 bit5~7 first and clear PS0~PS2 automatically. R3 [0] R3 [1] R3 [2] R3 [3] Carry flag Auxiliary carry flag Zero flag. It will be set to 1 when the result of an arithmetic or logic operation is zero. Power down flag. It will be set to 1 during Power-on phase or by "WDTC" command and cleared when the MCU enters into Power-down mode. It remains in its previous state after a Watchdog Reset. "0" : Power-down mode "1" : Power on Values of RST, T and P after a Reset
Reset Type Power on WDT during Operation mode WDT wake-up during Sleep 1 mode T 1 0 0 P 1 P 0
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Contents WDT wake-up during Sleep 2 mode Wake-up on pin change during Sleep 2 mode 0 P P P
*P: Previous value before reset Status of RST, T and P Being Affected by Events
Event Power on WDTC instruction WDT time-out SLEP instruction Wake-Up on pin change during Sleep 2 mode T 1 1 0 1 P P 1 1 *P 0 P
*P: Previous value before reset R3 [4] Time-out flag. It will be set to 1 during Power-on phase or by "WDTC" command. It is reset to 0 by WDT time-out. "0" : Watchdog timer with overflow "1" : Watchdog timer without overflow R3 [5~7] Page selection bits. These three bits are used to select the page of the program memory.
PS2 0 0 0 0 1 1 PS1 0 0 1 1 0 0 PS0 0 1 0 1 0 1 Program Memory Page [Address] Page 0 [000-3FF] Page 1 [400-7FF] Page 2 [800-BFF] Page 3 [C00-FFF] Page 4 [1000-13FF] Page 5 [1400-17FF]
6.2.1.5 R4 (RAM Select Register)
Bit 7 BK1 Bit 6 BK0 Bit 5 Ad5 Bit 4 Ad4 Bit 3 Ad3 Bit 2 Ad2 Bit 1 Ad1 Bit 0 Ad0
R4 (RAM select register) contains the address of the registers. When interrupt occurs , the MCU will save R4 value automatically. R4 [0~5] are used to select registers (address: 0x00h~0x3Fh) in indirect addressing mode. R4 [6~7] are used to determine which bank is activated among the 8 banks. To select a register bank, refer to the table below:
R4[7]BK1 0 0 R4[6]BK0 0 1 RAM Bank # Bank 0 Bank 1
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6.2.1.6
Bit 7 P57
R5 (Port 5 I/O Register) Default Value: (0B_0000_0000)
Bit 6 P56 Bit 5 P55 Bit 4 P54 Bit 3 P53 Bit 2 P52 Bit 1 P51 Bit 0 P50
6.2.1.7
Bit 7 P67
R6 (Port 6 I/O Register) Default Value: (0B_0000_0000)
Bit 6 P66 Bit 5 P65 Bit 4 P64 Bit 3 P63 Bit 2 P62 Bit 1 P61 Bit 0 P60
6.2.1.8
Bit 7 P77
R7 (Port 7 I/O Register) Default Value: (0B_0000_0000)
Bit 6 P76 Bit 5 DBit 4 D+ Bit 3 - Bit 2 P72 Bit 1 P71 Bit 0 P70
6.2.1.9
Bit 7 P87
R8 (Port 8 I/O Register) Default Value: (0B_0000_0000)
Bit 6 P86 Bit 5 P85 Bit 4 P84 Bit 3 P83 Bit 2 P82 Bit 1 P81 Bit 0 P80
6.2.1.10 R9 (Port 9 I/O Register) Default Value: (0B_0000_0000)
Bit 7 - Bit 6 P96 Bit 5 P95 Bit 4 P94 Bit 3 P93 Bit 2 P92 Bit 1 P91 Bit 0 P90
6.2.1.11 RA (USB Endpoint 0 Status Register): Default Value: (0B0000_0000)
Bit 7 Extr _R Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Remote Status EP0_W EP0_R Dev _Resume UDC_Suspend UDC_Writing STALL
RA [0]
STALL flag. When the MCU receives an unsupported command or invalid parameters from host, this bit will be set to 1 by the firmware to notify the UDC to return a STALL handshake. When a successful setup transaction is received, this bit is cleared automatically. This bit is both readable and writable. UDC Writing flag. Read only. When this bit is equal to "1," it indicates that the UDC is writing da0ta into the EP0's FIFO or reading data from it. During this time, the firmware will avoid accessing the FIFO until the UDC finishes writing or reading. This bit is only readable. 1 : EP0's FIFO is busy 0 : EP0's FIFO is free for data transition. ACK, NAK are reset.
RA [1]
RA [2]
UDC Suspend flag. If this bit is equal to 1, it indicates that the USB bus has no traffic for a specified period of 3.0 ms. This bit will also be cleared automatically when a bus activity takes place. This bit is only readable.
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RA [3]
Device resume flag. This bit is set by firmware to generate a signal to wake up the USB host and is cleared as soon as the USB Suspend signal becomes low. This bit can only be set by firmware and cleared by hardware. It cam only be used under dual mode. This bit is both readable and writable. EP0_R flag. This bit informs the UDC to read the data written by the firmware from the FIFO. Then the UDC will automatically send the data to the Host. After the UDC finishes reading the data from the FIFO, this bit will be cleared automatically. Therefore, before writing data into FIFO, the firmware will first check this bit to avoid overwriting the data. This bit can only be set by the firmware and cleared by the hardware.
RA [4]
RA [5]
EP0_W. After the UDC completes writing data to the FIFO, this bit will be set automatically. The firmware will clear it as soon as it gets the data from EP0's FIFO. Only when this bit is cleared will the UDC be able to write a new data into the FIFO. Therefore, before the firmware can write a data into the FIFO, this bit must first be set by the firmware to prevent the UDC from writing data at the same time. This bit is both readable and writable.
RA [6]
Remote wake-up status. Pass device remote wake-up setting from the PC. Extra RAM switch. RAM block switch 0: Switch to Bank 0~Bank 3 and external RAM0 1: Switch to Bank 4~Bank 7 and external RAM1
RA [7]
6.2.1.12 RC (FIFO Indirect Index Register)
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 UAD4 Bit 3 UAD3 Bit 2 UAD2 Bit 1 UAD1 Bit 0 UAD0
RC [0~4] Application FIFO address registers. These five bits are the address pointer of Application FIFO. RC [5~7] Undefined registers. 6.2.1.13 RD (FIFO Indirect Data Register)
Bit 7 UAD7 Bit 6 UAD6 Bit 5 UAD5 Bit 4 UAD4 Bit 3 UAD3 Bit 2 UAD2 Bit 1 UAD1 Bit 0 UAD0
RD (Application FIFO data register) contains the data in the register of which address is pointed by RC.
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6.2.1.14 RE (Interrupt Status Register)
Bit 7 P77_IF Bit 6 P76_IF Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved Reserved RF2_High RF2_Low RF1_High RF1_Low
RE [0] RE [1] RE [2] RE [3]
RF1_Low flag: Pattern Detection interruption flag. RF1 low pattern compare flag. RF1_High flag: Pattern Detection interruption flag. RF1 high pattern compare flag. RF2_Low flag: Pattern Detection interruption flag. RF2 low pattern compare flag. RF2_High flag: Pattern Detection interruption flag. RF2 high pattern compare flag.
RE [4~5] Reserved. Do not use. RE [6] RE [7] P76_IF: P76 State Change interruption flag. P77_IF: P77 State Change interruption flag. The interrupt vector is in 0x0018 address.
6.2.1.15 RF (Interrupt Status Register)
Bit 7 OUT EP_IF Bit 6 - Bit 5 - Bit 4 Bit 3 Bit 2 Bit 1 EP0_IF Bit 0 TCC_IF Resume_IF USBReset_IF Suspend_IF
RF [0] RF [1]
TCC timer overflow interruption flag. It will be set while TCC timer overflows, and is cleared by the firmware. EndPoint Zero interruption flag. It will be set when the EM78M680 receives Vender /Customer Command to EndPoint Zero. This bit is cleared by the firmware USB Suspend interrupt flag: It will be set when the EM78M680 finds the USB Suspend Signal on USB bus. This bit is cleared by the firmware. USB Reset interrupt flag. It will be set when the Host issues the USB Reset signal. USB Host Resume interrupt flag. It will be set only under Dual clock mode when the USB suspend signal becomes low.
RF [2] RF [3] RF [4]
RF [5~6] Not used and read as "0". RF [7] OUT endpoint interrupt flag. It will be set when the fifo of outendpoint has been received data from host.
Extra RAM0 : 6.2.1.16 R10 (USB Endpoint Status Register) : Default (0b0000_0000)
Bit 7 - Bit 6 - Bit 5 - Bit 4 EP5_ST Bit 3 EP4_ST Bit 2 EP3_ST Bit 1 EP2_ST Bit 0 EP1_ST
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R10 [0~4] EPx_ST: End point state flag. These five bits inform the UDC to read the data written by the firmware from the FIFO. Then the UDC will automatically send the data to the Host. After UDC finishes reading the data from the FIFO, this bit will be automatically cleared. Therefore, before writing data into FIFO's, the firmware will first check this bit to avoid overwriting the data. These five bits can only be set by the firmware and cleared by the hardware. Readable and writable. For OUT Endpoint: After an out token is finish, and the UDC completes writing data to the FIFO, this bit will be set automatically, and run into interrupt vector 0x0020. The firmware should clear it as soon as it gets the data from OUT Endpoint's FIFO. Only when this bit is cleared will the UDC be able to write a new data into the FIFO. 6.2.1.17 R11 (AD Controller/AD Selection Pin) : Default (0b0001_1111)
Bit 7 AD_start Bit 6 AD_R1 Bit 5 AD_R0 Bit 4 AD_A4 Bit 3 AD_A3 Bit 2 AD_A2 Bit 1 AD_A1 Bit 0 AD_A0
R11 [0~4] AD channel selector: If the AD number is from zero to 0x17, the AD converter will be powered on. Otherwise, it will be powered off.
AD number AD pin AD number AD pin AD number AD pin AD number AD pin AD number AD pin AD number AD pin 00000 AD0 00100 AD4 01000 AD8 01100 AD12 10000 AD16 10100 AD20 00001 AD1 00101 AD5 01001 AD9 01101 AD13 10001 AD17 10101 AD21 00010 AD2 00110 AD6 01010 AD10 01110 AD14 10010 AD18 10110 AD22 00011 AD3 00111 AD7 01011 AD11 01111 AD15 10011 AD19 10111 AD23
R11 [5~6] AD conversion clock source. 00 : 256K 01 : 128K 10 : 64K 11 : 32K R11 [7] AD Converter ready flag. 0 1 1 : Start AD Conversion (set by firmware). 0 : When AD finishes converting and has moved digital data into the AD Data Register, this bit will be reset by hardware.
NOTE
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Hardware can enable this function only at the AD Channel Selector of the functional I/O port. After Power-on reset, the initial value of this register is 0b0001 1111.
6.2.1.18 R12 (Dual Mode Control) : Default (0b0000_1000)
Bit 7 - Bit 6 USB_Token Bit 5 LOW FR1 Bit 4 LOW FR0 Bit 3 /LOW FREQ Bit 2 - Bit 1 - Bit 0 -
R12 [3]
/LOW FREQ: Dual Clock Control bit. This bit is used to select the frequency of the system clock. When this bit is set to 0, the MCU will run on very slow frequency for power saving purposes and the UDC will stop working. 0 : slow frequency (500Hz~256kHz) 1 : Normal frequency
R12 [4~5] LOW FR0 ~ LOW FR1: Low Frequency Switches. These bits select the operation frequency in Dual Clock Mode. Four frequencies are available and can be chosen as Dual Clock Mode for running the MCU program.
Low FR1 0 0 1 1 Low FR0 0 1 0 1 Frequency 500Hz 4kHz 32kHz 256kHz
Bit 6 (USB_Token) : Set when USB Token from Host. Reset when end of the Token. 6.2.1.19 R14 (ADC Output Data) : ADC Output Data for Selecting Pin. Default (0b0000_0000). Read Only When the A/D conversion is completed, the result is loaded to R13 & R14.
Bit 7 ADB1 Bit 6 ADB0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
Bit 7 ADB9
Bit 6 ADB8
Bit 5 ADB7
Bit 4 ADB6
Bit 3 ADB5
Bit 2 ADB4
Bit 1 ADB3
Bit 0 ADB2
R15 : The high level time of the 1st PWM module that outputs to P92 (If PWM function is enabled). R16 : The high level time of the 2nd PWM module that outputs to P93(If PWM function is enabled).
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R15~R16 can be a general purpose register if the PWM function is disabled. 6.2.1.20 R17 (EEPROM Control Register) : Default (0b0000_0011)
Bit 7 - Bit 6 EE_Act Bit 5 EE_Reset Bit 4 EE_A4 Bit 3 EE_A3 Bit 2 EE_O.K Bit 1 EE_C1 Bit 0 EE_C0
This register is a general register if the EEPROM function is disabled. R17 [0~1] EE_C0 ~ EE_C1: EEPROM control bits. 00 : Read data from EEPROM to EEPROM FIFO. 01 : Write data from EEPROM FIFO to EEPROM 10 : Erase EEPROM 11 : Disable EEPROM function R17 [2] EE_O.K: EEPROM activated O.K bits. 0 : not O.K 1 : O.K R17 [3~4] EE_A4 ~ EE_A3: Bank selector. The EEPROM is divided into four banks, these two bits can select which bank of the EEPROM to read, write or erase. 00 : Byte 0 ~Byte 7 01 : Byte8~Byte 15 10 : Byte16~Byte 23 11 : Byte 24~Byte 31 R17 [ 5] EE_Reset: EEPROM FIFO Address Reset flag. 0 : Default. EE_Reset is set to 0 after FIFO address is reset 1 : Reset EEPROM FIFO address by firmware R17 [ 6] EE_Act: EEPROM activated mode switch. 0 : Activate all EEPROM 1 : Activate partial EEPROM 6.2.1.21 R18~R1F (General Purpose Register) R17~R1F are general-purpose registers. 6.2.1.22 R20~R3F (General Purpose Register) R20~R3F (including Banks 0~3) are general-purpose registers. Extra RAM1 : R10 ~ R14 (Reserved Register) : Do not use
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R15 (SE1_LOW ): low signal counter of the 1st RF module that inputted from P92. R16 (SE1_HIGH ): high signal counter of the 1st RF module that is inputted from P92. R17 (SE2_LOW ): low signal counter of the 2nd RF module that is inputted from P93. R18 (SE2_HIGH ): low signal counter of the 2nd RF module that is inputted from P93. R15 ~ R18 are RF Timing counter registers if RF function is enabled by setting Bit 2 or Bit 3 of IOCF. Otherwise, they are general registers. R19~R1F (General Purpose Register) R19~R1F are general-purpose registers. R20~R3F (General Purpose Register) R20~R3F (including Banks 4~7) are general-purpose registers.
6.3 Special Function Registers
6.3.1 A (Accumulator)
The accumulator is an 8-bit register that holds operands and results of arithmetic calculations. It is not addressable. After an interrupt occurs, the Accumulator is auto-saved by hardware.
6.3.2 CONT (Control Register)
Bit 7 - Bit 6 INT Bit 5 TSR2 Bit 4 TSR1 Bit 3 TSR0 Bit 2 PSR2 Bit 1 PSR1 Bit 0 PSR0
Except for Bit 6 (Interrupt enable control bit), the CONT register can be read by the instruction "CONTR" and written to by the instruction "CONTW". CONT [6] INT: An interrupt enable flag cannot be written by the CONTW instruction. CONT [3~5] TSR0 ~ TSR2: TCC prescaler bit CONT [0~2] PSR0 ~ PSR2: WDT prescaler bits
PSR2 0 0 0 0 1 PSR1 0 0 1 1 0 PSR0 0 1 0 1 0 TCC Rate (Base Freq: Fosc/2) 1:2 1:4 1:8 1:16 1:32 WDT Rate 1:1 1:2 1:4 1:8 1:16
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Contents 1 1 1 0 1 1 1 0 1 1:64 1:128 1:256 1:32 1:64 1:128
6.3.3 IOC5 ~ IOC9 Port Direction Control Register
These are I/O port (Port5 ~ Port7) direction control registers. Each bit controls the I/O direction of three I/O ports respectively. When these bits are set to 1, the relative I/O pins become input pins. Similarly, the I/O pins becomes outputs when the relative control bits are cleared. 0 : Output direction 1 : Input direction
6.3.4 IOCA (RFCNT: RF Control Register)
Bit 7 - Bit 6 - Bit 5 RF2 Bit 4 RF1 Bit 3 RF0 Bit 2 Bit 1 Bit 0 RF_DBN2 RF_DBN1 RF_DBN0
IOCA [0~2] RF_DBN0 ~ RF_DBN2: These are used for defining debounce times in RF pattern detecting application. IOCA [3~5] RF0 ~ RF2: RF Timing prescaler bits. Base on MCU frequency.
RF2 RF1 RF0 Timing Rate 8MHz System Clock (Time(Cnt.)) 256kHz RC Mode (Time (Cnt.)) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 0.125s (1), 31.875s (255) 0.25s (1), 63.75s (255) 0.5s (1), 127.5s (255) 1s (1), 255s (255) 2s (1), 510s (255) 4s (1), 1020s (255) 8s (1), 2040s (255) 16s (1), 4080s (255) 3.91s (1), 996.1s (255) 7.81s (1), 1992s (255) 15.625s (1), 3984s (255) 31.25s (1), 7969s (255) 62.5s (1), 15.938ms (255) 125s (1), 31.875ms (255) 250s (1), 63.75ms (255) 500s (1), 127.5ms (255)
6.3.5 IOCB (PWM_CNT: PWM Controller) : Default (0b0000_0001)
Bit 7 PW2_E Bit 6 PW1_E Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWM_SR2 PWM_SR1 PWM_SR0
IOCB [0~2] PWM_SR0 ~ PWM_SR2: PWM clock prescaler Base on MCU frequency (ex : Fosc = 8MHz)
PWM_SR2 0 0 0 0 1 1 1 PWM_SR1 0 0 1 1 0 0 1 PWM_SR0 0 1 0 1 0 1 0 Clock (Hz) Fosc / 2 Fosc / 4 Fosc / 8 Fosc / 16 Fosc / 32 Fosc / 64 Fosc / 128
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IOCB [6] (PW1_E): PW1 Enable. The 1st PWM (P92) module enable bit. 0 : Disable the PWM function of the 1st module 1 : Enable the PWM function of the 1st module IOCB [7] (PW2_E): PWM2 Enable: The 2nd PWM (P93) module enable bit. 0 : Disable the PWM function of the 2nd module 1 : Enable the PWM function of the 2nd module
6.3.6 IOCC (Reserve): Do not use 6.3.7 IOCD (Port 9 Pull High Control Register) Default Value: (0B_1111_1111)
Bit 7 1 Bit 6 /PH96 Bit 5 /PH95 Bit 4 1 Bit 3 /PH93 Bit 2 /PH92 Bit 1 /PH91 Bit 0 /PH90
IOCD [0~6] /PH90 ~ /PH96: These bits control the 25K pull-high resistor of individual pins in Port 9. If the I/O port is set as output, the pull-high function is disabled. 0 : Enable the pull-high function 1 : Disable the pull-high function
6.3.8 IOCE (MCU Control Register) : Default (0b1101_1111)
Bit 7 S7 Bit 6 /WUE Bit 5 WTE Bit 4 SLPC Bit 3 /PU7 Bit 2 /PU8 Bit 1 /PU6 Bit 0 /PU5
IOCE [0~3] /PU5~/PU8: Pull-High Control register. Default=1, Disable pull high function. If the I/O port is set as output, the pull-high function is disabled. 0 : Enable the pull-high function 1 : Disable the pull-high function IOCE [4] SLPC: This bit can be cleared by the firmware and set during power-on, or by the hardware at the falling edge of wake-up signal. When this bit is cleared, the clock system is disabled and the MCU enters into Power down mode. At the transition of wake-up signal from high to low, this bit is set to enable the clock system. 0 : Sleep mode. The device is in power down mode. 1 : Run mode. The device is working normally. IOCE [5] WTE: Watchdog timer enable bit. WDT is disabled/ enabled by the WTE bit. 0 : Disable WDT 1 : Enable WDT IOCE [6] /WUE: Enable the weak-up function as triggered by port- changed.
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0 : Enable wake-up function 1 : Disable wake-up function IOCE [7] S7 bit : S7 defines the driving ability of P70-P72 0 : Normal output 1 : Enhance the driving ability of LED
6.3.9 IOCF (Interrupt Mask Register)
Bit 7 Bit 6 Bit 5 Bit 4 Resume_IE Bit 3 RF2_IE Bit 2 RF1_IE Bit 1 USB_IE Bit 0 TCC_IE OUTEP_IE P76/P77_IE Reserved
IOCF [0] TCC_IE: TCIF interrupt enable bit 0 : Disable TCIF interrupt 1 : Enable TCIF interrupt IOCF [1] USB_IE: USB interrupt enable bit. Bits 1, 2, 3 of RF interrupt will be enabled while this bit is set. 0 : Disable USB_IE interrupt 1 : Enable USB_IE interrupt IOCF [2] RF1_IE: RF1 pattern compare interrupt enable bit. Bits 0, 1 of RE interrupt will be enabled while this bit is set. 0 : Disable RF1_IE interrupt 1 : Enable RF1_IE interrupt IOCF [3] RF2_IE: RF2 pattern compare interrupt enable bit. Bits 2, 3 of RE interrupt will be enabled while this bit is set. 0 : Disable RF2_IE interrupt 1 : Enable RF2_IE interrupt IOCF [4] Resume_IE: USB Resume interrupt enable bit 0 : Disable Resume_IE interrupt 1 : Enable Resume_IE interrupt IOCF [5] Reserved. Do not use. IOCF [6] P76/77_IE: P76/P77 port change interrupt enable bit. Bits 6, 7 of RE interrupt will be enabled while this bit is set. 0 : Disable P76/P77_IE interrupt 1 : Enable P76/P77_IE interrupt IOCF [7] OUTEP_IE: Output Endpoint interrupt enable bit 0 : disable OUTEP_IE interrupt 1 : enable OUTEP_IE interrupt
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Only when the global interrupt is enabled by the ENI instruction that the individual interrupt will work. After DISI instruction, any interrupt will not work even if the respective control bits of IOCF are set to 1. The USB Host Resume Interrupt works only under Dual clock mode. This is because when the MCU is under sleep mode, it will be waked up by the UDC Resume signal automatically
6.4 USB Device Controller
The USB Device Controller (UDC) built-in in the EM78M680 can interpret the USB Standard Command and response automatically without involving firmware. The embedded Series Interface Engine (SIE) handles the serialization and de-serialization of actual USB transmission. Thus, a developer can concentrate his efforts more in perfecting the device actual functions and spend less energy in dealing with USB transaction. The UDC handles and decodes most Standard USB commands defined in the USB Specification Rev 1.1. If the UDC receives an unsupported command, it will set a flag to notify the MCU the receipt of such command. Each time the UDC receives a USB command, it writes the command into EP0's FIFO. Only when it receives unsupported command that the UDC will notify the MCU through interrupt. Therefore, the EM78M680 is very flexible for USB applications since developers can freely choose the method of decoding the USB command as dictated by different situation.
6.5 Device Address and Endpoints
The EM78M680 supports one device address and five endpoints, EP0 for control endpoint, EP1 ~ EP5 for interrupt/bulk /isochronous endpoints. Sending data to USB host in EM78M680 is very easy. Just write data into the EP's FIFO, then set the flag, and the UDC will handle the rest. It will then confirm that the USB host has received the correct data from the EM78M680.
6.6 Reset
The EM78M680 provides three types of reset: (1) Power-on Reset, (2) Watchdog Reset, and (3) USB Reset.
6.6.1 Power-on Reset
Power-on Reset occurs when the device is attached to power and a reset signal is initiated. The signal will last until the MCU becomes stable. After a Power-on Reset, the MCU enters the following predetermined states (see below), and then, it is ready to execute the program. a. The program counter is cleared. b. The TCC timer and Watchdog timer are cleared.
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c. Special registers and Special Control registers are all set to their initial value.
6.6.2 Watchdog Reset
When the Watchdog timer overflows, it causes the Watchdog to reset. After it resets, the program is executed from the beginning and some registers will be reset. The UDC however, remains unaffected.
6.6.3 USB Reset
When the UDC detects a USB Reset signal on the USB Bus, it interrupts the MCU, then proceeds to perform the specified process that follows. After a USB device is attached to the USB port, it cannot respond to any bus transactions until it receives a USB Reset signal from the bus.
6.7 Saving Power Mode
The EM78M680 provides two options of power-saving modes for energy conservation, i.e., Power Down mode and Dual clock mode.
6.7.1 Power Down Mode
The EM78M680 enters into Power Down mode by clearing the SLPC register (IOCE[4]). During this mode, the oscillator is turned off and the MCU goes to sleep. It will wake up when signal from USB host is resumed, or when the Watchdog reset or the input port state changes. If the MCU wakes up when the I/O port status changes, the direction of I/O port should be set at input direction, then read the port status. For example: : // Set the Port 6 to input port MOV A , 0XFF IOW PORT6 // Read the status of Port 6 MOV PORT6, PORT6 // Clear the RUN bit IOR 0XE AND A , 0B11101111 IOW 0XE : : If the MCU is awaken by a USB Resume signal, the next instruction will be executed and one flag, IOCE[4] will be set to 1.
6.7.2 Dual Clock Mode
The EM78M680 has one internal oscillator for power saving application. Clearing the Bit R12 [3] of ExteraRAM0 will enable the low frequency oscillator. At the
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same time, the external oscillator will be turned off. Then the MCU will run under very low frequency to conserve power. Four types of frequency are available for selection in setting Bits R12 [4, 5]. The USB Host Resume Interrupt can only be used in this mode. If this interrupt is enabled, the MCU will be interrupted when the USB Resume signal is detected on USB Bus.
6.8 Interrupt
The EM78680 has four interrupt vectors 0x0008, 0x0010, 0x0018, 0x0020. When an interrupt occurs during an MCU running program, it will jump to the interrupt vector and execute the instructions sequentially from the interrupt vector. RE and RF is the interrupt status register, which records the interrupt status in the relative flags/bits. The interrupt condition could be one of the following: Set 1 INT: (jump to 0x08) TCC overflow interrupt EP0 command in interrupt USB suspend interrupt USB reset interrupt USB HOST resume interrupt
Set 2 INT: (jump to 0x10) RF1 low pattern interrupt RF1 high pattern interrupt RF2 low pattern interrupt RF2 high pattern interrupt
Set 3 INT: (jump to 0x18) P77 port change interrupt P76 port change interrupt
Set 4 INT: (jump to 0x20) EP5~8 output Endpoint received O.K interrupt IOCF is an interrupt mask register which can be set bit by bit. While their respective bit is written to 0, the hardware interrupt will inhibit, that is, the EM78M680 will not jump to the interrupt vector to execute instructions. But the interrupt status flags still records the conditions no matter whether the interrupt is
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masked or not. The interrupt status flags must be cleared by firmware before leaving the interrupt service routine and enabling interrupt. The global interrupt is enabled by the ENI (RETI) instruction and is disabled by the DISI instruction.
6.9 Pattern Detect Application (PDA)
6.9.1 Function Description
This function is designed for the serial signal transmission, e.g., the transmission between a wireless device and its receiver box. The EM78M680 has two sets of built-in Pattern Detect Application block that ensures the EM78M680 is equipped with a compound device, such as the receiver box controller for a wireless keyboard paired with a wireless mouse. Pattern Detect Application (PDA) can calculate the length of one pattern and interrupt the MCU while the serial signal is transiting from high to low (or vise-versa). Then the MCU reads the length value from a specified register.
6.9.2 Control Register
The PDA includes two enable control bits, one control register and four length counter registers in 0x15 ~0x18 in ExtraRAM1. 6.9.2.1 IOCF [2~3] PDA Enable Control Bit
When this bit is set, the PDA function starts and the P92 and P93 become input pin automatically to sample the serial signal.(note: Enabling these two bits also enabling the interrupt mask of PDA.) 0 : disable PDA function 1 : enable PDA function 6.9.2.2
Bit 7
IOCA (PDA Control Register) Default Value: (0B_0000_0000)
Bit 6 Bit 5 RF.2 Bit 4 RF.1 Bit 3 RF.0 Bit 2 DB2 Bit 1 DB1 Bit 0 DB0
This register is used to define two parameters of PDA function; signal sampling rate and debounce length. When a pattern ends, the value in the counter is loaded into its respective register and the RE[0~4] is set to indicate which channel and which type of pattern (high or low) is at its end or which type of pattern counter is on overflow. 0 : low pattern 1 : high pattern 6.9.2.3 R15 ExtraRAM1 (P.92 Low Pattern Counter)
This register records the length of P.92 in low status.
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6.9.2.4
R16 ExtraRAM1 (P.92 High Pattern Counter)
This register records the length of P.92 in high status. 6.9.2.5 R17 ExtraRAM1 (P.93 Low Pattern Counter)
This register records the length of P.93 in low status 6.9.2.6 R18 ExtraRAM1 (P.93 High Pattern Counter)
This register records the length of P.93 in high status. R15~R18 function as general registers if this function is not enabled. Once the enabled bit is set, these four registers will be loaded with the value of the pattern counter.
6.9.3 Sampling Rate and Debounce Length
The two pattern detect pins are separate, and each pin has its own pattern counter. Both pins use the same Sampling Rate and Debounce Length parameters. The PDA samples the serial signal for every fixed interval. The pattern counter will be incremented by one at sampling time if the signal remains unchanged. If the signal is at high state, then the "high pattern counter" will be incremented, otherwise the "low pattern counter" is incremented. As long as the signal state changes, the PDA will debounce signal and load the value of the pattern counter into the respective register for the firmware to read. For example, if the signal in P.92 is in "low" state, the low counter of P.92 will count continuously until the state of the input signal in P.92 changes. When a state change occurs (in this case, the signal changes from "low" to "high" state), the PDA will take a time break (which is equal to the result of sampling interval multiplied by the debounce length), to avoid possible noise. After the debounce length time, if the signal remains in high state, the high pattern counter will start to count and load the low pattern counter's value into R15 ExtraRAM1. At the same time, RE [0] is set to indicate that the low pattern is over. The correlation between the value of control register and debounce time are as follows:
DB.2 0 0 0 0 1 1 1 1 DB.1 0 0 1 1 0 0 1 1 DB.0 0 1 0 1 0 1 0 1 Debounce Time No Sampling clock. 1 Sampling clock 2 Sampling clock 3 Sampling clock. 4 Sampling clock 5 Sampling clock 6 Sampling clock 7 Sampling clock
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Now consider another situation of this case, where the signal of P92 always stays "low". The low pattern counter of P92 will eventually overflow. Once the counter overflows, the content of the counter will also be loaded into R15, that is, the register is written to 0xFF, then the counter is reset to count from zero again. If the hardware interrupt of PDA function is enabled, (IOCF[2] is equal to "1"), then the program will go to 0x0010 to execute interrupt routine while the content of a pattern counter is loaded into the register. The correlation between the value of control register and actual sampling rate are as shown below:
RF2 RF1 RF0 Timing Rate 8MHz System Clock (Time(Cnt.)) 256kHz RC Mode (Time (Cnt.)) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 0.125s (1), 31.875s (255) 0.25s (1), 63.75s (255) 0.5s (1), 127.5s (255) 1s (1), 255s (255) 2s (1), 510s (255) 4s (1), 1020s (255) 8s (1), 2040s (255) 16s (1), 4080s (255) 3.91s (1), 996.1s (255) 7.81s (1), 1992s (255) 15.625s (1), 3984s (255) 31.25s (1), 7969s (255) 62.5s (1), 15.938ms (255) 125s (1), 31.875ms (255) 250s (1), 63.75ms (255) 500s (1), 127.5ms (255)
User can write a default value to the High Pattern counter register and Low Pattern counter register. Then set the corresponding interrupt enable bit (IOCF [2, 3]). When the counting value of one "H" pattern is bigger than the default value of R15_ExtraRAM1, a Pattern Detecting interrupt will be generated. Similarly, if the counting value of one "L" pattern is bigger than the default value of R16_ExtraRAM1, a Low Pattern Detecting interrupt will occur. Thus, the EM78M680 is notified and aware that one effective pattern is received from P.92.
6.10 Pulse Width Modulation (PWM)
6.10.1 Function Description
In PWM mode, both of PWM1 (P.92) and PWM2 (P.93) produce plus programmable signal of up to 8 bits resolution. The PWM Period is defined as 0xFF x Timer Counter Clock. The Timer Counter clock source is controlled by control register IOCB. For example; if the clock source is 1MHz, then the Period will be 255s. Period = 255 x (1/Timer Counter Clock)
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Period (0xFF * Clock)
Duty Cycle
Fig. 7-1 PWM Output Timing Diagram
6.10.2 Duty Cycle
The PWM duty cycle is defined by writing to the R15/R16 Register of ExtraRAM0 for PWM1/ PWM2. Duty Cycle = ( R15 of ExtraRAM0/ 255 ) x 100% for PWM1 ( R16 of ExtraRAM0/ 255 ) x 100% for PWM2
6.10.3 Control Register
6.10.3.1 R15 of Extra RAM0(PWM1 Duty Cycle Register) A specified value keeps the output of PWM1 to remain at high for a period of time. 6.10.3.2 R16 of Extra RAM0 (PWM2 Duty Cycle Register) A specified value keeps the output of PWM2 to remain at high for a period of time. 6.10.3.3 IOCB(PWM Control Register) Default Value: (0B_0000_0001)
Bit 7 PW2_E Bit 6 PW1_E Bit 5 - Bit 4 - Bit 3 - Bit 2 PWM_SR2 Bit 1 PWM_SR1 Bit 0 PWM_SR0
IOCB [0~2] PWM Clock Prescaler Base on MCU frequency (ex : Fosc = 8MHz)
PWM_SR2 0 0 0 0 1 1 1 1 PWM_SR1 0 0 1 1 0 0 1 1 PWM_SR0 0 1 0 1 0 1 0 1 Clock(Hz) Fosc / 2 Fosc / 4 Fosc / 8 Fosc / 16 Fosc / 32 Fosc / 64 Fosc / 128 Fosc / 256 Period / 255 0.25s 0.5s 1s 2s 4s 8s 16s 32s
IOCB [6, 7] PWM1/PWM2 Enable Bit "0" : Disable "1" : Enable
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6.11 Analog-To-Digital Converter (ADC)
6.11.1 Function Description
The Analog to Digital converter consists of a 5-bit analog multiplexer, one Control Register (R11_ExtraRAM0), and two data registers (R13_ExtraRAM0 ~ R14_ExtraRAM0) for a 10-bit resolution. The ADC module utilizes successive approximation to convert the unknown analog signal to a digital value. The result is fed to the ADDATA. Input channels are selected by the analog input multiplexer via the ADCR/AD_Sel bits AD0~AD4. 10-bit resolution: 0x00-00~0xC0-FF (0b11000000-11111111) Start (0x00-00): 0 Vref~(1/1024)*Vref Full (0xC0-FF): (1023/1024)*Vref~Vref Conversion Time: 12 clock time of internal clock source
6.11.2 Control Register
6.11.2.1 R11 (AD Channel Select Register) Default Value: (0B_0001_1111)
Bit 7 AD_start Bit 6 AD_R1 Bit 5 AD_R0 Bit 4 AD4 Bit 3 AD3 Bit 2 AD2 Bit 1 AD1 Bit 0 AD0
R11 [0~4]: AD Channel Selector
AD4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 AD3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 AD2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 AD1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 AD0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Channel 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 I/O Port P50 P51 P52 P53 P54 P55 P56 P57 P80 P81 P82 P83 P84 P85 P86 P87 P60 P61 P62 P63 P64 P65 P66 P67
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R11 [5 6]:The Clock Source of AD Converting. 00 : 256kHz 01 : 128kHz 10 : 64kHz 11 : 32kHz R11 [7] AD Converter Start Flag 0 1 1 : Start AD Conversion (set by firmware) 0 : When AD finishes converting and has moved the digital data into the AD Data Register, this bit will be reset by hardware.
NOTE Hardware can enable this function only at AD Channel Selector of the functional I/O port. After Power-on reset, the initial value of this register is 0b0001 1111.
6.11.2.2 R13 (AD LSB Data Register) Default Value: (0B_0000_0000)
Bit 7 Bit 1 Bit 6 Bit 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
AD Digital Data LSB 2 bits 6.11.2.3 R14 (AD MSB Data Register) Default Value: (0B_0000_0000)
Bit 7 Bit 9 Bit 6 Bit 8 Bit 5 Bit 7 Bit 4 Bit 6 Bit 3 Bit 5 Bit 2 Bit 4 Bit 1 Bit 3 Bit 0 Bit 2
AD Digital Data MSB 8 bits
7
Absolute Maximum Ratings
Items Temperature under bias Storage temperature Input voltage Output voltage Min 0 -65 -0.5 -0.5 Max 70 150 6.0 6.0 Unit C C V V
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8
DC Electrical Characteristic
Ta=25C, VDD=5V, VSS=0V
Symbol VDD IIL VIH VIL VIHX VILX VOH1 Parameter Operating voltage Input Leakage Current Input High Voltage Input Low Voltage Clock Input High Voltage Clock Input Low Voltage Output High Voltage (P70~P72, P76~P77) Output High Voltage VOH2 (Ports 5, 6, 8, P90~P93, P95~P96) Output Low Voltage (P70~P72, P76~77) Output Low Voltage (P70~P72 : LED drive mode) Output Low Voltage VOL3 (Ports 5,6,8, P90~P93, P95~P96) Pull-high current IPH1 (Ports 5, 6, 7, 8, P90~P93, P95~P96) Pull-high current (P70~P72, P76~77) Pull-high current (USB D+) Operating supply current Normal operation Operating supply current Sleep mode OSCI OSCI IOH = 7.0mA VDD = 5 V IOH = 7.0mA Vreg = 3.3 V IOL = -8.0mA VDD = 5 V IOL = -8.0mA VDD = 5 V IOL = -8.0mA Vreg = 3.3 V Pull-high active, input pin at VSS Vreg=3.3V Pull-high active, input pin at VSS VDD = 5 V Pull-high active, input pin at VSS Vreg=3.3V Condition - VIN = VDD, VSS - - Min 4.4 - 2.0 - 2.5 - 2.4 Typ Max Unit 5.0 - - - - - - 5.25 1 - 0.8 - 1.0 - V A V V V V V
2.4
-
-
V
VOL1
- -
- -
0.4
V
VOL2
3.0
V
-
-
0.4
V
-20% 132 +20% A
IPH2
-20% 132 +20% A
IPH3
-
2.2
-
mA
ICC1
Fosc= 8MHz , no GPIO loading All input and I/O pin at VDD, output pin floating, WDT disabled All input and I/O pin at VDD, output pin floating, WDT disabled
-
-
10
mA
ICC2
-
-
100
A
ICC3
Operating supply current Dual clock mode - 256kHz
-
-
250
A
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Vreg
Output voltage of 3.3V regulator VDD = 4.4V ~ 5.25V
3.0
3.3
3.6
V
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APPENDIX A Special Register Map
Address Name Reset Type Bit Name Power-On N/A IOC5 /RESET and WDT Wake-Up from Pin Change Bit Name Power-On N/A IOC6 /RESET and WDT Wake-Up from Pin Change Bit Name Power-On N/A IOC7 /RESET and WDT Wake-Up from Pin Change Bit Name Power-On N/A IOC8 /RESET and WDT Wake-Up from Pin Change Bit Name Power-On N/A IOC9 /RESET and WDT Wake-Up from Pin Change Bit Name IOCA (RFCNT) Power-On /RESET and WDT Wake-Up from Pin Change Bit Name 0x0B IOCB (PWM_CNT) Power-On /RESET and WDT Wake-Up from Pin Change Bit 7 C57 1 1 P C67 1 1 P C77 1 1 P C87 1 1 P C97 1 1 P 0 0 P Bit 6 C56 1 1 P C66 1 1 P C76 1 1 P C86 1 1 P C96 1 1 P 0 0 P Bit 5 C55 1 1 P C65 1 1 P 1 1 P C85 1 1 P C95 1 1 P RF2 0 0 P 0 0 P Bit 4 C54 1 1 P C64 1 1 P 1 1 P C84 1 1 P C94 1 1 P RF1 0 0 P 0 0 P Bit 3 C53 1 1 P C63 1 1 P 1 1 P C83 1 1 P C93 1 1 P RF0 0 0 P 0 0 P Bit 2 C52 1 1 P C62 1 1 P C72 1 1 P C82 1 1 P C92 1 1 P Bit 1 C51 1 1 P C61 1 1 P C71 1 1 P C81 1 1 P C91 1 1 P Bit 0 C50 1 1 P C60 1 1 P C70 1 1 P C80 1 1 P C90 1 1 P
RF_DB2 RF_DB1 RF_DB0 0 0 P 0 0 P 0 0 P
0x0A
PW2_E PW1_E 0 0 P 0 0 P
PWM_2 PWM_1 PWM_0 0 0 P 0 0 P 0 0 P
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Address
Name
Reset Type Bit Name
Bit 7 GPB 0 0 P 1 1 P S7 1 1 P
Bit 6 GPB 0 0 P
Bit 5 GPB 0 0 P
Bit 4 GPB 0 0 P 1 1 P SLPC 1 1 1
Bit 3 GPB 0 0 P
Bit 2 0 0 P
Bit 1 0 0 P
Bit 0 0 0 P
0x0C
Power-On IOCC (Do not use) /RESET and WDT Wake-Up from Pin Change Bit Name IOCD (P9_PH) Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On IOCE (MCU Cnt) /RESET and WDT Wake-Up from Pin Change Bit Name Power-On
/PH96 /PH95 1 1 P /WUE 1 1 P 1 1 P WTE 0 0 P -0 0 P TSR2 1 1 P U P P 0 0 P 0 0
/PH93 /PH92 /PH91 /PH90 1 1 P U U U 1 1 P /PU8 1 1 P 1 1 P /PU6 1 1 P 1 1 P /PU5 1 1 P
0x0D
0x0E
OUTEP P7IE 0 0 P U U U U P P 0 0 P 0 0 0 0 P INT 0 P P U P P 0 0 P 0 0
ResuIE RF2IE RF1IE USBIE TCIE 0 0 P TSR1 1 1 P U P P 0 0 P 0 0 0 0 P TSR0 1 1 P U P P 0 0 P 0 0 0 0 P PSR2 1 1 P U P P 0 0 P 0 0 0 0 P 0 0 P
0x0F
IOCF
/RESET and WDT Wake-Up from Pin Change Bit Name Power-On
PSR1 PSR0 1 1 P U P P 0 0 P 0 0 1 1 P U P P 0 0 P 0 0
N/A
CONT
/RESET and WDT Wake-Up from Pin Change Bit Name Power-On
0x00
R0(IAR)
/RESET and WDT Wake-Up from Pin Change Bit Name Power-On
0x01
R1(TCC)
/RESET and WDT Wake-Up from Pin Change
0x02
R2(PC)
Bit Name Power-On /RESET and WDT
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Contents Address Name Reset Type Wake-Up from Pin Change Bit Name Power-On 0x03 R3 (SR) /RESET and WDT Wake-Up from Pin Change Bit Name Power-On 0x04 R4 (RSR) /RESET and WDT Wake-Up from Pin Change Bit Name Power-On 0x05 R5 (P5) /RESET and WDT Wake-Up from Pin Change Bit Name Power-On 0x06 R6 (P6) /RESET and WDT Wake-Up from Pin Change Bit Name Power-On 0x07 R7 (P7) /RESET and WDT Wake-Up from Pin Change Bit Name Power-On 0x08 R8 (P8) /RESET and WDT Wake-Up from Pin Change Bit Name Power-On 0x09 R9 (P9) /RESET and WDT Wake-Up from Pin Change 0x0A RA(USBES) Bit Name Power-On /RESET and WDT Bit 7 **P PS2 0 0 P Bit 6 **P PS1 0 0 P Bit 5 **P PS0 0 0 P U P P P55 U P P P65 U P P U P P P85 U P P P95 U P P Bit 4 **P T t t t U P P P54 U P P P64 U P P U P P P84 U P P P94 U P P Bit 3 **P P t t t U P P P53 U P P P63 U P P U P P P83 U P P P93 U P P Bit 2 **P Z U P P U P P P52 U P P P62 U P P P72 U P P P82 U P P P92 U P P Bit 1 **P DC U P P U P P P51 U P P P61 U P P P71 U P P P81 U P P P91 U P P Bit 0 **P C U P P U P P P50 U P P P60 U P P P70 U P P P80 U P P P90 U P P
RSR.1 RSR.0 0 0 P P57 U P P P67 U P P P77 U P P P87 U P P P97 U P P 0 0 P P56 U P P P66 U P P P76 U P P P86 U P P P96 U P P
Ext_R Remote EP0_W EP0_R D_Resu UDC_Su UDC_w STALL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Contents Address Name Reset Type Wake-Up from Pin Change Bit Name Power-On 0x0B GPR /RESET and WDT Wake-Up from Pin Change Bit Name Power-On RC (FIFO_Index) /RESET and WDT Wake-Up from Pin Change Bit Name Power-On RD (FIFO_Data) /RESET and WDT Wake-Up from Pin Change Bit Name Power-On 0x0E RE (ISR0) /RESET and WDT Wake-Up from Pin Change Bit Name Power-On 0x0F RF (ISR0) /RESET and WDT Wake-Up from Pin Change Bit Name Power-On R10 (USB EP stat) /RESET and WDT Wake-Up from Pin Change Bit Name 0x11 Power-On R11 (AD/Control) /RESET and WDT Wake-Up from Pin Change R12 (Dual) Bit Name Power-On /RESET and WDT Bit 7 P GPB U P P Bit 6 P GPB U P P Bit 5 P GPB U P P Bit 4 P GPB U P P Bit 3 P GPB U P P Bit 2 P GPB U P P Bit 1 P GPB U P P Bit 0 P GPB U P P
Index7 Index6 Index5 Index4 Index3 Index2 Index1 Index0 0 0 P 0 0 P 0 0 P 0 0 P 0 0 P 0 0 P 0 0 P 0 0 P
0x0C
FIFO7 FIFO6 FIFO5 FIFO4 FIFO3 FIFO2 FIFO1 FIFO0 0 0 P 0 0 P 0 0 P 0 0 P 0 0 P 0 0 P 0 0 P 0 0 P 0 0 P 0 0 P
0x0D
P77_IF P76_IF 0 0 P 0 0 P
RF2_H RF2_L RF1_H RF1_L 0 0 P 0 0 P 0 0 P 0 0 P
Out_EP GPB 0 0 P GPB U P P U P P GPB U P P
GPB ResumIF USBres Suspend EP0_IF TCCIF U P P GPB U P P 0 0 P 0 0 P 0 0 P 0 0 P 0 0 P
EP5_ST EP4_ST EP3_ST EP2_ST EP1_ST 0 0 P AD4 1 1 P 0 0 P AD3 1 1 P 0 0 P AD2 1 1 P 0 0 P AD1 1 1 P GPB U P 0 0 P AD0 1 1 P GPB U P
0x10
ADstart AD_R1 AD_R0 0 0 P 0 0 P 0 0 P
0x12
GPB USB_To Low_F1 Low_F0 /LowFre GPB U P U U 0 0 0 0 1 1 U P
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Contents Address Name Reset Type Wake-Up from Pin Change Bit Name R13 (ADLoData) Power-On /RESET and WDT Wake-Up from Pin Change Bit Name R14 (ADHiData) Power-On /RESET and WDT Wake-Up from Pin Change Bit Name R15 (PWM1_T) Power-On /RESET and WDT Wake-Up from Pin Change Bit Name R16 (PWM2_T) Power-On /RESET and WDT Wake-Up from Pin Change Bit Name R17 (EECNT) Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On 0x18~0x3F GPR /RESET and WDT Wake-Up from Pin Change Bit Name R10 (Do not use) Power-On /RESET and WDT Wake-Up from Pin Change 0x11 R11 (Do not use) Bit Name Power-On /RESET and WDT Bit 7 P Bit 6 P Bit 5 P 0 0 P Bit 4 P 0 0 P Bit 3 P 0 0 P Bit 2 P 0 0 P Bit 1 P 0 0 P Bit 0 P 0 0 P
ADD1 ADD0 0 0 P 0 0 P
0x13
ADD9 ADD8 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 0 0 P 0 0 P 0 0 P 0 0 P 0 0 P 0 0 P 0 0 P 0 0 P
0x14
PWM17 PWM16 PWM15 PWM14 PWM13 PWM12 PWM11 PWM10 0 0 P 0 0 P 0 0 P 0 0 P 0 0 P 0 0 P 0 0 P 0 0 P
0x15
PWM27 PWM26 PWM25 PWM24 PWM23 PWM22 PWM21 PWM20 0 0 P GPB U P P U P P -1 1 P GPB U P 0 0 P 0 0 P 0 0 P 0 0 P 0 0 P 0 0 P 0 0 P
0x16
EE_Act EE_rest EEA4 0 0 P U P P -1 1 P -0 P 0 0 P U P P -1 1 P -0 P 0 0 P U P P -1 1 P -0 P
EEA3 EE_OK EE_C1 EE_C0 0 0 P U P P -1 1 P -0 P 1 0 P U P P -1 1 P GPB U P 1 1 P U P P -1 1 P GPB U P 1 1 P U P P -1 1 P GPB U P
0x17
0x10
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Contents Address Name Reset Type Wake-Up from Pin Change Bit 7 P Bit 6 P Bit 5 P Bit 4 P Bit 3 P Bit 2 P Bit 1 P Bit 0 P
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Address
Name
Reset Type Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name
Bit 7 -0 0 P -0 0 P -0 0
Bit 6 -0 0 P -0 0 P -0 0
Bit 5 -0 0 P -0 0 P -0 0
Bit 4 -U P P -0 0 P -0 0
Bit 3 -0 0 P GPB U P P -0 0
Bit 2 -0 0 P -0 0 P -0 0
Bit 1 -U P P -0 0 P -0 0
Bit 0 -0 0 P -0 0 P -0 0
0x12
R12 (Do not use)
0x13
R13 (Do not use)
Power-On /RESET and WDT Wake-Up from Pin Change Bit Name
0x14
R14 (Do not use)
Power-On /RESET and WDT
Wake-Up from Pin P P P P P P P P Change Bit Name SE1_L7 SE1_L6 SE1_L5 SE1_L4 SE1_L3 SE1_L2 SE1_L1 SE1_L0 0x15 R15 (SE1_LOW) Power-On /RESET and WDT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Wake-Up from Pin P P P P P P P P Change Bit Name SE1_H7 SE1_H6 SE1_H5 SE1_H4 SE1_H3 SE1_H2 SE1_H1 SE1_H0 0x16 R16 (SE1_HIGH) Power-On /RESET and WDT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Wake-Up from Pin P P P P P P P P Change Bit Name SE2_L7 SE2_L6 SE2_L5 SE2_L4 SE2_L3 SE2_L2 SE2_L1 SE2_L0 0x17 R17 (SE2_LOW) Power-On /RESET and WDT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Wake-Up from Pin P P P P P P P P Change Bit Name SE2_H7 SE2_H6 SE2_H5 SE2_H4 SE2_H3 SE2_H2 SE2_H1 SE2_H0 0x18 R18 (SE2_HIGH) Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On 0x19~0x3F GPR /RESET and WDT Wake-Up from Pin Change 0 0 P U P P 0 0 P U P P 0 0 P U P P 0 0 P U P P 0 0 P U P P 0 0 P U P P 0 0 P U P P 0 0 P U P P
** Execute the next instruction after the "SLPC" bit status of IOCE register has been on high-to-low transition.
X: Not for use. U: Unknown or don't care. P: Previous value before reset.
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B Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one or more operands. All instructions are executed within one single instruction cycle (consisting of 2 oscillator periods), unless the program counter is changed by(a) Executing the instruction "MOV R2,A", "ADD R2,A", "TBL", or any other instructions that write to R2 (e.g. "SUB R2,A", "BS R2,6", "CLR R2", ). (b) Execute CALL, RET, RETI, RETL, JMP, Conditional skip (JBS, JBC, JZ, JZA, DJZ, DJZA) which were tested to be true. Under these cases, the execution takes two instruction cycles. In addition, the instruction set has the following features: (1). Every bit of any register can be set, cleared, or tested directly. (2). The I/O register can be regarded as general register. That is, the same instruction can operate on I/O register.
Legend: R = Register designator that specifies which one of the 64 registers (including operation and general purpose registers) is to be utilized by the instruction. Bits 6 and 7 in R4 determine the selected register bank. b = Bit field designator that selects the value for the bit located in the register R and which affects the operation. k = 8 or 10-bit constant or literal value Binary Instruction 0 0000 0000 0000 0 0000 0000 0001 0 0000 0000 0010 0 0000 0000 0011 0 0000 0000 0100 0 0000 0000 rrrr 0 0000 0001 0000 0 0000 0001 0001 0 0000 0001 0010 0 0000 0001 0011 0 0000 0001 0100 0 0000 0001 rrrr 0 0000 0010 0000 0 0000 01rr rrrr 0 0000 1000 0000 0 0000 11rr rrrr Hex 0000 0001 0002 0003 0004 000r 0010 0011 0012 0013 0014 001r 0020 00rr 0080 00rr Mnemonic NOP DAA CONTW SLEP WDTC IOW R ENI DISI RET RETI CONTR IOR R TBL MOV R,A CLRA CLR R Operation No Operation Decimal Adjust A A CONT 0 WDT, Stop oscillator 0 WDT A IOCR Enable Interrupt Disable Interrupt [Top of Stack] PC [Top of Stack] PC, Enable Interrupt CONT A IOCR A R2+A R2, Bits 8~9 of R2 unchanged AR 0A 0R Status Affected None C None T, P T, P None None None None None None None Z, C, DC None Z Z
1 1
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Contents Binary Instruction 0 0001 00rr rrrr 0 0001 01rr rrrr 0 0001 10rr rrrr 0 0001 11rr rrrr 0 0010 00rr rrrr 0 0010 01rr rrrr 0 0010 10rr rrrr 0 0010 11rr rrrr 0 0011 00rr rrrr 0 0011 01rr rrrr 0 0011 10rr rrrr 0 0011 11rr rrrr 0 0100 00rr rrrr 0 0100 01rr rrrr 0 0100 10rr rrrr 0 0100 11rr rrrr 0 0101 00rr rrrr 0 0101 01rr rrrr 0 0101 10rr rrrr 0 0101 11rr rrrr 0 0110 00rr rrrr 0 0110 01rr rrrr 0 0110 10rr rrrr 0 0110 11rr rrrr 0 0111 00rr rrrr 0 0111 01rr rrrr 0 0111 10rr rrrr 0 0111 11rr rrrr 0 100b bbrr rrrr 0 101b bbrr rrrr 0 110b bbrr rrrr 0 111b bbrr rrrr 1 00kk kkkk kkkk 1 01kk kkkk kkkk 1 1000 kkkk kkkk 1 1001 kkkk kkkk 1 1010 kkkk kkkk 1 1011 kkkk kkkk 1 1100 kkkk kkkk 1 1101 kkkk kkkk 1 1110 0000 0kkk Hex 01rr 01rr 01rr 01rr 02rr 02rr 02rr 02rr 03rr 03rr 03rr 03rr 04rr 04rr 04rr 04rr 05rr 05rr 05rr 05rr 06rr 06rr 06rr 06rr 07rr 07rr 07rr 07rr 0xxx 0xxx 0xxx 0xxx 1kkk 1kkk 18kk 19kk 1Akk 1Bkk 1Ckk 1Dkk 1E0k Mnemonic SUB A,R SUB R,A DECA R DEC R OR A,R OR R,A AND A,R AND R,A XOR A,R XOR R,A ADD A,R ADD R,A MOV A,R MOV R,R COMA R COM R INCA R INC R DJZA R DJZ R RRCA R RRC R RLCA R RLC R SWAPA R SWAP R JZA R JZ R BC R,b BS R,b JBC R,b JBS R,b CALL k JMP k MOV A,k OR A,k AND A,k XOR A,k RETL k SUB A,k Operation R-A A R-A R R-1 A R-1 R A VR A A VR R A&RA A&RR ARA ARR A+RA A+RR RA RR /R A /R R R+1 A R+1 R R-1 A, skip if zero R-1 R, skip if zero R(n) A(n-1), R(0) C, C A(7) R(n) R(n-1), R(0) C, C R(7) R(n) A(n+1), R(7) C, C A(0) R(n) R(n+1), R(7) C, C R(0) R(0-3) A(4-7), R(4-7) A(0-3) R(0-3) R(4-7) R+1 A, skip if zero R+1 R, skip if zero 0 R(b) 1 R(b) if R(b)=0, skip if R(b)=1, skip PC+1 [SP], (Page, k) PC (Page, k) PC kA AkA A&kA AkA k A, [Top of Stack] PC k-A A Status Affected Z, C, DC Z, C, DC Z Z Z Z Z Z Z Z Z, C, DC Z, C, DC Z Z Z Z Z Z None None C C C C None None None None None None None None None None None Z Z Z None Z, C, DC None
2
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Contents Binary Instruction 1 1111 kkkk kkkk
1 2
Hex 1Fkk
Mnemonic ADD A,k
Operation k+A A
Status Affected Z, C, DC
Note: This instruction is applicable to IOCx only. This instruction is not recommended for RE, RF operation.
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C Code Option
Bit 0 /Protect Bit 1 USB Bit 2 /D+ resistor Bit 3 OST0 Bit 4 OST1 Bit 5 FRQ0 Bit 6 FRQ1 Bit 7 PKG0 Bit 8 PKG1 Bit 9 Reversed Bit 10 /AD hold
Bit 11
Bit 12
Bit 13~15 EPX_SEL
Bit 16~17 EP1 Type
Bit 18 EP1 Direction
Bit 19~20
Bit 22~22
Bit 23 EP2 Direction
Reserved Reserved
EP1 Max Size EP2 Type
Bit 24~25 EP2 Max Size
Bit 26~27 EP3 Type
Bit 28 EP3 Direction
Bit 29~30 EP3 Max Size
Bit 31~32 EP4 Type
Bit 33 EP4 Direction
Bit 34~35 EP4 Max Size
Bit 36~37 EP5 Type
Bit 38 EP5 Direction
Bit 39~40 EP5 Max Size
Bit 41~42 reserved
Bit 43~59 USER ID
Bit 60~63 reserved
Bit 0 (/Protect): Protect bit. 1 : Disable 0 : Enable. Bit 1 (USB): Operation mode. 1 : USB mode 0 : Non-USB mode. Close UDC & Transceiver function. Bit 2 (/D+ resistor): D+ Resistor pull-high switch. 1 : Disable internal USB D+ pull-high resistor. 0 : Enable internal USB D+ pull-high resistor. Bit 4~3 (OST1~OST0): Oscillator start time. WDT time-out time. 00 : 500 s 01 : 2 ms 10 : 4 ms 11 : 8 ms Bit 6~5 (FRQ1~FRQ0): System clock frequency switch. 00 : 8MHz, External Crystal x 2 01 : 16MHz, External Crystal x 4 10 : 24MHz, External Crystal x 6 11 : Not Defined
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Bits 8~7 (PKG1~PKG0): Package switch. 00 : 20 pins 01 : 24 pins 10 : 40 pins 11 : 44 pins Bit 9 (Reverse): set" 0" as default value Bit 10 (/ADHold): Setting MCU when AD converting 0 : Hold MCU when AD converting. 1 : Keep MCU running when AD converting. Bit 11 ~ Bit 12 : Reserved Reserve, Set as "0, 0" Bits 15 ~ 13 (EPX_SEL2 ~ EPX_SEL0): Endpoint function selection
EPX Status / EPX FIFO Max Size EPX_SEL[2 : 0] (USB Mode) 000 001 010 011 100 101 110 111 EP1 Enable / 64 bit Enable / 64 bit Enable / 64 bit Enable / 64 bit Enable / 64 bit Enable / 64 bit Enable / 32 bit Enable / 32 bit EP2 Disable / NA Enable / 64 bit Enable / 32 bit Enable / 32 bit Enable / 32 bit Enable / 16 bit Enable / 32 bit Enable / 32 bit EP3 Disable / NA Disable / NA Enable / 32 bit Enable / 16 bit Enable / 16 bit Enable / 16 bit Enable / 32 bit Enable / 32 bit EP4 Disable / NA Disable / NA Disable / NA Enable / 16 bit Enable / 8 bit Enable / 16 bit Enable / 32 bit Enable / 16 bit EP5 Disable / NA Disable / NA Disable / NA Disable / NA Enable / 8 bit Enable / 16 bit Disable / NA Enable / 16 bit
Bits 16 ~ 40 : EPx Type : 00 Not defined 01 Isochronous mode transfer 10 Bulk mode transfer 11 Interrupt mode transfer EPx Direction : 0 Output way 1 Input way
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Contents
EPx Max Size : 00 8 bytes 01 16 bytes 10 32 bytes 11 64 bytes If EPx Max Size selection is larger than Endpoint function selection, EPX FIFO size will depend on the size of Endpoint function selector (EPX_Sel0~2]). Bits 41 ~ 42 (Reserved): reserved bit Default : 1 Bits 43~ Bit 59 (USER ID): Define by user. Bits 60~63 (Reserved): reserved bit
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Product Specification (V1.11) 02.10.2007
EM78M680
USB Full Speed Microcontroller
D. Application Circuit:
Product Specification (V1.1) 02.10.2007
(This specification is subject to change without further notice)
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